xref: /llvm-project/llvm/test/CodeGen/AArch64/vector_splat-const-shift-of-constmasked.ll (revision 82d330e0e04a55ee95dc93980761545a01543fde) 
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple=aarch64-unknown-linux-gnu < %s | FileCheck %s
3
4; The mask is all-ones, potentially shifted.
5
6;------------------------------------------------------------------------------;
7; 128-bit vector; 8-bit elements = 16 elements
8;------------------------------------------------------------------------------;
9
10; lshr
11
12define <16 x i8> @test_128_i8_x_16_7_mask_lshr_1(<16 x i8> %a0) {
13; CHECK-LABEL: test_128_i8_x_16_7_mask_lshr_1:
14; CHECK:       // %bb.0:
15; CHECK-NEXT:    movi v1.16b, #7
16; CHECK-NEXT:    and v0.16b, v0.16b, v1.16b
17; CHECK-NEXT:    ushr v0.16b, v0.16b, #1
18; CHECK-NEXT:    ret
19  %t0 = and <16 x i8> %a0, <i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7>
20  %t1 = lshr <16 x i8> %t0, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>
21  ret <16 x i8> %t1
22}
23
24define <16 x i8> @test_128_i8_x_16_28_mask_lshr_1(<16 x i8> %a0) {
25; CHECK-LABEL: test_128_i8_x_16_28_mask_lshr_1:
26; CHECK:       // %bb.0:
27; CHECK-NEXT:    movi v1.16b, #28
28; CHECK-NEXT:    and v0.16b, v0.16b, v1.16b
29; CHECK-NEXT:    ushr v0.16b, v0.16b, #1
30; CHECK-NEXT:    ret
31  %t0 = and <16 x i8> %a0, <i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28>
32  %t1 = lshr <16 x i8> %t0, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>
33  ret <16 x i8> %t1
34}
35define <16 x i8> @test_128_i8_x_16_28_mask_lshr_2(<16 x i8> %a0) {
36; CHECK-LABEL: test_128_i8_x_16_28_mask_lshr_2:
37; CHECK:       // %bb.0:
38; CHECK-NEXT:    movi v1.16b, #28
39; CHECK-NEXT:    and v0.16b, v0.16b, v1.16b
40; CHECK-NEXT:    ushr v0.16b, v0.16b, #2
41; CHECK-NEXT:    ret
42  %t0 = and <16 x i8> %a0, <i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28>
43  %t1 = lshr <16 x i8> %t0, <i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2>
44  ret <16 x i8> %t1
45}
46define <16 x i8> @test_128_i8_x_16_28_mask_lshr_3(<16 x i8> %a0) {
47; CHECK-LABEL: test_128_i8_x_16_28_mask_lshr_3:
48; CHECK:       // %bb.0:
49; CHECK-NEXT:    movi v1.16b, #28
50; CHECK-NEXT:    and v0.16b, v0.16b, v1.16b
51; CHECK-NEXT:    ushr v0.16b, v0.16b, #3
52; CHECK-NEXT:    ret
53  %t0 = and <16 x i8> %a0, <i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28>
54  %t1 = lshr <16 x i8> %t0, <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>
55  ret <16 x i8> %t1
56}
57define <16 x i8> @test_128_i8_x_16_28_mask_lshr_4(<16 x i8> %a0) {
58; CHECK-LABEL: test_128_i8_x_16_28_mask_lshr_4:
59; CHECK:       // %bb.0:
60; CHECK-NEXT:    movi v1.16b, #28
61; CHECK-NEXT:    and v0.16b, v0.16b, v1.16b
62; CHECK-NEXT:    ushr v0.16b, v0.16b, #4
63; CHECK-NEXT:    ret
64  %t0 = and <16 x i8> %a0, <i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28>
65  %t1 = lshr <16 x i8> %t0, <i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4>
66  ret <16 x i8> %t1
67}
68
69define <16 x i8> @test_128_i8_x_16_224_mask_lshr_1(<16 x i8> %a0) {
70; CHECK-LABEL: test_128_i8_x_16_224_mask_lshr_1:
71; CHECK:       // %bb.0:
72; CHECK-NEXT:    movi v1.16b, #224
73; CHECK-NEXT:    and v0.16b, v0.16b, v1.16b
74; CHECK-NEXT:    ushr v0.16b, v0.16b, #1
75; CHECK-NEXT:    ret
76  %t0 = and <16 x i8> %a0, <i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224>
77  %t1 = lshr <16 x i8> %t0, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>
78  ret <16 x i8> %t1
79}
80define <16 x i8> @test_128_i8_x_16_224_mask_lshr_4(<16 x i8> %a0) {
81; CHECK-LABEL: test_128_i8_x_16_224_mask_lshr_4:
82; CHECK:       // %bb.0:
83; CHECK-NEXT:    movi v1.16b, #224
84; CHECK-NEXT:    and v0.16b, v0.16b, v1.16b
85; CHECK-NEXT:    ushr v0.16b, v0.16b, #4
86; CHECK-NEXT:    ret
87  %t0 = and <16 x i8> %a0, <i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224>
88  %t1 = lshr <16 x i8> %t0, <i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4>
89  ret <16 x i8> %t1
90}
91define <16 x i8> @test_128_i8_x_16_224_mask_lshr_5(<16 x i8> %a0) {
92; CHECK-LABEL: test_128_i8_x_16_224_mask_lshr_5:
93; CHECK:       // %bb.0:
94; CHECK-NEXT:    ushr v0.16b, v0.16b, #5
95; CHECK-NEXT:    ret
96  %t0 = and <16 x i8> %a0, <i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224>
97  %t1 = lshr <16 x i8> %t0, <i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5>
98  ret <16 x i8> %t1
99}
100define <16 x i8> @test_128_i8_x_16_224_mask_lshr_6(<16 x i8> %a0) {
101; CHECK-LABEL: test_128_i8_x_16_224_mask_lshr_6:
102; CHECK:       // %bb.0:
103; CHECK-NEXT:    ushr v0.16b, v0.16b, #6
104; CHECK-NEXT:    ret
105  %t0 = and <16 x i8> %a0, <i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224>
106  %t1 = lshr <16 x i8> %t0, <i8 6, i8 6, i8 6, i8 6, i8 6, i8 6, i8 6, i8 6, i8 6, i8 6, i8 6, i8 6, i8 6, i8 6, i8 6, i8 6>
107  ret <16 x i8> %t1
108}
109
110; ashr
111
112define <16 x i8> @test_128_i8_x_16_7_mask_ashr_1(<16 x i8> %a0) {
113; CHECK-LABEL: test_128_i8_x_16_7_mask_ashr_1:
114; CHECK:       // %bb.0:
115; CHECK-NEXT:    movi v1.16b, #7
116; CHECK-NEXT:    and v0.16b, v0.16b, v1.16b
117; CHECK-NEXT:    ushr v0.16b, v0.16b, #1
118; CHECK-NEXT:    ret
119  %t0 = and <16 x i8> %a0, <i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7>
120  %t1 = ashr <16 x i8> %t0, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>
121  ret <16 x i8> %t1
122}
123
124define <16 x i8> @test_128_i8_x_16_28_mask_ashr_1(<16 x i8> %a0) {
125; CHECK-LABEL: test_128_i8_x_16_28_mask_ashr_1:
126; CHECK:       // %bb.0:
127; CHECK-NEXT:    movi v1.16b, #28
128; CHECK-NEXT:    and v0.16b, v0.16b, v1.16b
129; CHECK-NEXT:    ushr v0.16b, v0.16b, #1
130; CHECK-NEXT:    ret
131  %t0 = and <16 x i8> %a0, <i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28>
132  %t1 = ashr <16 x i8> %t0, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>
133  ret <16 x i8> %t1
134}
135define <16 x i8> @test_128_i8_x_16_28_mask_ashr_2(<16 x i8> %a0) {
136; CHECK-LABEL: test_128_i8_x_16_28_mask_ashr_2:
137; CHECK:       // %bb.0:
138; CHECK-NEXT:    movi v1.16b, #28
139; CHECK-NEXT:    and v0.16b, v0.16b, v1.16b
140; CHECK-NEXT:    ushr v0.16b, v0.16b, #2
141; CHECK-NEXT:    ret
142  %t0 = and <16 x i8> %a0, <i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28>
143  %t1 = ashr <16 x i8> %t0, <i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2>
144  ret <16 x i8> %t1
145}
146define <16 x i8> @test_128_i8_x_16_28_mask_ashr_3(<16 x i8> %a0) {
147; CHECK-LABEL: test_128_i8_x_16_28_mask_ashr_3:
148; CHECK:       // %bb.0:
149; CHECK-NEXT:    movi v1.16b, #28
150; CHECK-NEXT:    and v0.16b, v0.16b, v1.16b
151; CHECK-NEXT:    ushr v0.16b, v0.16b, #3
152; CHECK-NEXT:    ret
153  %t0 = and <16 x i8> %a0, <i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28>
154  %t1 = ashr <16 x i8> %t0, <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>
155  ret <16 x i8> %t1
156}
157define <16 x i8> @test_128_i8_x_16_28_mask_ashr_4(<16 x i8> %a0) {
158; CHECK-LABEL: test_128_i8_x_16_28_mask_ashr_4:
159; CHECK:       // %bb.0:
160; CHECK-NEXT:    movi v1.16b, #28
161; CHECK-NEXT:    and v0.16b, v0.16b, v1.16b
162; CHECK-NEXT:    ushr v0.16b, v0.16b, #4
163; CHECK-NEXT:    ret
164  %t0 = and <16 x i8> %a0, <i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28>
165  %t1 = ashr <16 x i8> %t0, <i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4>
166  ret <16 x i8> %t1
167}
168
169define <16 x i8> @test_128_i8_x_16_224_mask_ashr_1(<16 x i8> %a0) {
170; CHECK-LABEL: test_128_i8_x_16_224_mask_ashr_1:
171; CHECK:       // %bb.0:
172; CHECK-NEXT:    movi v1.16b, #224
173; CHECK-NEXT:    and v0.16b, v0.16b, v1.16b
174; CHECK-NEXT:    sshr v0.16b, v0.16b, #1
175; CHECK-NEXT:    ret
176  %t0 = and <16 x i8> %a0, <i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224>
177  %t1 = ashr <16 x i8> %t0, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>
178  ret <16 x i8> %t1
179}
180define <16 x i8> @test_128_i8_x_16_224_mask_ashr_4(<16 x i8> %a0) {
181; CHECK-LABEL: test_128_i8_x_16_224_mask_ashr_4:
182; CHECK:       // %bb.0:
183; CHECK-NEXT:    movi v1.16b, #224
184; CHECK-NEXT:    and v0.16b, v0.16b, v1.16b
185; CHECK-NEXT:    sshr v0.16b, v0.16b, #4
186; CHECK-NEXT:    ret
187  %t0 = and <16 x i8> %a0, <i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224>
188  %t1 = ashr <16 x i8> %t0, <i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4>
189  ret <16 x i8> %t1
190}
191define <16 x i8> @test_128_i8_x_16_224_mask_ashr_5(<16 x i8> %a0) {
192; CHECK-LABEL: test_128_i8_x_16_224_mask_ashr_5:
193; CHECK:       // %bb.0:
194; CHECK-NEXT:    sshr v0.16b, v0.16b, #5
195; CHECK-NEXT:    ret
196  %t0 = and <16 x i8> %a0, <i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224>
197  %t1 = ashr <16 x i8> %t0, <i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5>
198  ret <16 x i8> %t1
199}
200define <16 x i8> @test_128_i8_x_16_224_mask_ashr_6(<16 x i8> %a0) {
201; CHECK-LABEL: test_128_i8_x_16_224_mask_ashr_6:
202; CHECK:       // %bb.0:
203; CHECK-NEXT:    sshr v0.16b, v0.16b, #6
204; CHECK-NEXT:    ret
205  %t0 = and <16 x i8> %a0, <i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224>
206  %t1 = ashr <16 x i8> %t0, <i8 6, i8 6, i8 6, i8 6, i8 6, i8 6, i8 6, i8 6, i8 6, i8 6, i8 6, i8 6, i8 6, i8 6, i8 6, i8 6>
207  ret <16 x i8> %t1
208}
209
210; shl
211
212define <16 x i8> @test_128_i8_x_16_7_mask_shl_1(<16 x i8> %a0) {
213; CHECK-LABEL: test_128_i8_x_16_7_mask_shl_1:
214; CHECK:       // %bb.0:
215; CHECK-NEXT:    movi v1.16b, #7
216; CHECK-NEXT:    and v0.16b, v0.16b, v1.16b
217; CHECK-NEXT:    add v0.16b, v0.16b, v0.16b
218; CHECK-NEXT:    ret
219  %t0 = and <16 x i8> %a0, <i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7>
220  %t1 = shl <16 x i8> %t0, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>
221  ret <16 x i8> %t1
222}
223define <16 x i8> @test_128_i8_x_16_7_mask_shl_4(<16 x i8> %a0) {
224; CHECK-LABEL: test_128_i8_x_16_7_mask_shl_4:
225; CHECK:       // %bb.0:
226; CHECK-NEXT:    movi v1.16b, #7
227; CHECK-NEXT:    and v0.16b, v0.16b, v1.16b
228; CHECK-NEXT:    shl v0.16b, v0.16b, #4
229; CHECK-NEXT:    ret
230  %t0 = and <16 x i8> %a0, <i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7>
231  %t1 = shl <16 x i8> %t0, <i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4>
232  ret <16 x i8> %t1
233}
234define <16 x i8> @test_128_i8_x_16_7_mask_shl_5(<16 x i8> %a0) {
235; CHECK-LABEL: test_128_i8_x_16_7_mask_shl_5:
236; CHECK:       // %bb.0:
237; CHECK-NEXT:    shl v0.16b, v0.16b, #5
238; CHECK-NEXT:    ret
239  %t0 = and <16 x i8> %a0, <i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7>
240  %t1 = shl <16 x i8> %t0, <i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5>
241  ret <16 x i8> %t1
242}
243define <16 x i8> @test_128_i8_x_16_7_mask_shl_6(<16 x i8> %a0) {
244; CHECK-LABEL: test_128_i8_x_16_7_mask_shl_6:
245; CHECK:       // %bb.0:
246; CHECK-NEXT:    shl v0.16b, v0.16b, #6
247; CHECK-NEXT:    ret
248  %t0 = and <16 x i8> %a0, <i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7>
249  %t1 = shl <16 x i8> %t0, <i8 6, i8 6, i8 6, i8 6, i8 6, i8 6, i8 6, i8 6, i8 6, i8 6, i8 6, i8 6, i8 6, i8 6, i8 6, i8 6>
250  ret <16 x i8> %t1
251}
252
253define <16 x i8> @test_128_i8_x_16_28_mask_shl_1(<16 x i8> %a0) {
254; CHECK-LABEL: test_128_i8_x_16_28_mask_shl_1:
255; CHECK:       // %bb.0:
256; CHECK-NEXT:    movi v1.16b, #28
257; CHECK-NEXT:    and v0.16b, v0.16b, v1.16b
258; CHECK-NEXT:    add v0.16b, v0.16b, v0.16b
259; CHECK-NEXT:    ret
260  %t0 = and <16 x i8> %a0, <i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28>
261  %t1 = shl <16 x i8> %t0, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>
262  ret <16 x i8> %t1
263}
264define <16 x i8> @test_128_i8_x_16_28_mask_shl_2(<16 x i8> %a0) {
265; CHECK-LABEL: test_128_i8_x_16_28_mask_shl_2:
266; CHECK:       // %bb.0:
267; CHECK-NEXT:    movi v1.16b, #28
268; CHECK-NEXT:    and v0.16b, v0.16b, v1.16b
269; CHECK-NEXT:    shl v0.16b, v0.16b, #2
270; CHECK-NEXT:    ret
271  %t0 = and <16 x i8> %a0, <i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28>
272  %t1 = shl <16 x i8> %t0, <i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2>
273  ret <16 x i8> %t1
274}
275define <16 x i8> @test_128_i8_x_16_28_mask_shl_3(<16 x i8> %a0) {
276; CHECK-LABEL: test_128_i8_x_16_28_mask_shl_3:
277; CHECK:       // %bb.0:
278; CHECK-NEXT:    movi v1.16b, #28
279; CHECK-NEXT:    and v0.16b, v0.16b, v1.16b
280; CHECK-NEXT:    shl v0.16b, v0.16b, #3
281; CHECK-NEXT:    ret
282  %t0 = and <16 x i8> %a0, <i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28>
283  %t1 = shl <16 x i8> %t0, <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>
284  ret <16 x i8> %t1
285}
286define <16 x i8> @test_128_i8_x_16_28_mask_shl_4(<16 x i8> %a0) {
287; CHECK-LABEL: test_128_i8_x_16_28_mask_shl_4:
288; CHECK:       // %bb.0:
289; CHECK-NEXT:    movi v1.16b, #28
290; CHECK-NEXT:    and v0.16b, v0.16b, v1.16b
291; CHECK-NEXT:    shl v0.16b, v0.16b, #4
292; CHECK-NEXT:    ret
293  %t0 = and <16 x i8> %a0, <i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28>
294  %t1 = shl <16 x i8> %t0, <i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4>
295  ret <16 x i8> %t1
296}
297
298define <16 x i8> @test_128_i8_x_16_224_mask_shl_1(<16 x i8> %a0) {
299; CHECK-LABEL: test_128_i8_x_16_224_mask_shl_1:
300; CHECK:       // %bb.0:
301; CHECK-NEXT:    movi v1.16b, #224
302; CHECK-NEXT:    and v0.16b, v0.16b, v1.16b
303; CHECK-NEXT:    add v0.16b, v0.16b, v0.16b
304; CHECK-NEXT:    ret
305  %t0 = and <16 x i8> %a0, <i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224>
306  %t1 = shl <16 x i8> %t0, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>
307  ret <16 x i8> %t1
308}
309
310;------------------------------------------------------------------------------;
311; 128-bit vector; 16-bit elements = 8 elements
312;------------------------------------------------------------------------------;
313
314; lshr
315
316define <8 x i16> @test_128_i16_x_8_127_mask_lshr_1(<8 x i16> %a0) {
317; CHECK-LABEL: test_128_i16_x_8_127_mask_lshr_1:
318; CHECK:       // %bb.0:
319; CHECK-NEXT:    movi v1.8h, #127
320; CHECK-NEXT:    and v0.16b, v0.16b, v1.16b
321; CHECK-NEXT:    ushr v0.8h, v0.8h, #1
322; CHECK-NEXT:    ret
323  %t0 = and <8 x i16> %a0, <i16 127, i16 127, i16 127, i16 127, i16 127, i16 127, i16 127, i16 127>
324  %t1 = lshr <8 x i16> %t0, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>
325  ret <8 x i16> %t1
326}
327
328define <8 x i16> @test_128_i16_x_8_2032_mask_lshr_3(<8 x i16> %a0) {
329; CHECK-LABEL: test_128_i16_x_8_2032_mask_lshr_3:
330; CHECK:       // %bb.0:
331; CHECK-NEXT:    mov w8, #2032
332; CHECK-NEXT:    dup v1.8h, w8
333; CHECK-NEXT:    and v0.16b, v0.16b, v1.16b
334; CHECK-NEXT:    ushr v0.8h, v0.8h, #3
335; CHECK-NEXT:    ret
336  %t0 = and <8 x i16> %a0, <i16 2032, i16 2032, i16 2032, i16 2032, i16 2032, i16 2032, i16 2032, i16 2032>
337  %t1 = lshr <8 x i16> %t0, <i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3>
338  ret <8 x i16> %t1
339}
340define <8 x i16> @test_128_i16_x_8_2032_mask_lshr_4(<8 x i16> %a0) {
341; CHECK-LABEL: test_128_i16_x_8_2032_mask_lshr_4:
342; CHECK:       // %bb.0:
343; CHECK-NEXT:    mov w8, #2032
344; CHECK-NEXT:    dup v1.8h, w8
345; CHECK-NEXT:    and v0.16b, v0.16b, v1.16b
346; CHECK-NEXT:    ushr v0.8h, v0.8h, #4
347; CHECK-NEXT:    ret
348  %t0 = and <8 x i16> %a0, <i16 2032, i16 2032, i16 2032, i16 2032, i16 2032, i16 2032, i16 2032, i16 2032>
349  %t1 = lshr <8 x i16> %t0, <i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4>
350  ret <8 x i16> %t1
351}
352define <8 x i16> @test_128_i16_x_8_2032_mask_lshr_5(<8 x i16> %a0) {
353; CHECK-LABEL: test_128_i16_x_8_2032_mask_lshr_5:
354; CHECK:       // %bb.0:
355; CHECK-NEXT:    mov w8, #2032
356; CHECK-NEXT:    dup v1.8h, w8
357; CHECK-NEXT:    and v0.16b, v0.16b, v1.16b
358; CHECK-NEXT:    ushr v0.8h, v0.8h, #5
359; CHECK-NEXT:    ret
360  %t0 = and <8 x i16> %a0, <i16 2032, i16 2032, i16 2032, i16 2032, i16 2032, i16 2032, i16 2032, i16 2032>
361  %t1 = lshr <8 x i16> %t0, <i16 5, i16 5, i16 5, i16 5, i16 5, i16 5, i16 5, i16 5>
362  ret <8 x i16> %t1
363}
364define <8 x i16> @test_128_i16_x_8_2032_mask_lshr_6(<8 x i16> %a0) {
365; CHECK-LABEL: test_128_i16_x_8_2032_mask_lshr_6:
366; CHECK:       // %bb.0:
367; CHECK-NEXT:    mov w8, #2032
368; CHECK-NEXT:    dup v1.8h, w8
369; CHECK-NEXT:    and v0.16b, v0.16b, v1.16b
370; CHECK-NEXT:    ushr v0.8h, v0.8h, #6
371; CHECK-NEXT:    ret
372  %t0 = and <8 x i16> %a0, <i16 2032, i16 2032, i16 2032, i16 2032, i16 2032, i16 2032, i16 2032, i16 2032>
373  %t1 = lshr <8 x i16> %t0, <i16 6, i16 6, i16 6, i16 6, i16 6, i16 6, i16 6, i16 6>
374  ret <8 x i16> %t1
375}
376
377define <8 x i16> @test_128_i16_x_8_65024_mask_lshr_1(<8 x i16> %a0) {
378; CHECK-LABEL: test_128_i16_x_8_65024_mask_lshr_1:
379; CHECK:       // %bb.0:
380; CHECK-NEXT:    movi v1.8h, #254, lsl #8
381; CHECK-NEXT:    and v0.16b, v0.16b, v1.16b
382; CHECK-NEXT:    ushr v0.8h, v0.8h, #1
383; CHECK-NEXT:    ret
384  %t0 = and <8 x i16> %a0, <i16 65024, i16 65024, i16 65024, i16 65024, i16 65024, i16 65024, i16 65024, i16 65024>
385  %t1 = lshr <8 x i16> %t0, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>
386  ret <8 x i16> %t1
387}
388define <8 x i16> @test_128_i16_x_8_65024_mask_lshr_8(<8 x i16> %a0) {
389; CHECK-LABEL: test_128_i16_x_8_65024_mask_lshr_8:
390; CHECK:       // %bb.0:
391; CHECK-NEXT:    movi v1.8h, #254, lsl #8
392; CHECK-NEXT:    and v0.16b, v0.16b, v1.16b
393; CHECK-NEXT:    ushr v0.8h, v0.8h, #8
394; CHECK-NEXT:    ret
395  %t0 = and <8 x i16> %a0, <i16 65024, i16 65024, i16 65024, i16 65024, i16 65024, i16 65024, i16 65024, i16 65024>
396  %t1 = lshr <8 x i16> %t0, <i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8>
397  ret <8 x i16> %t1
398}
399define <8 x i16> @test_128_i16_x_8_65024_mask_lshr_9(<8 x i16> %a0) {
400; CHECK-LABEL: test_128_i16_x_8_65024_mask_lshr_9:
401; CHECK:       // %bb.0:
402; CHECK-NEXT:    ushr v0.8h, v0.8h, #9
403; CHECK-NEXT:    ret
404  %t0 = and <8 x i16> %a0, <i16 65024, i16 65024, i16 65024, i16 65024, i16 65024, i16 65024, i16 65024, i16 65024>
405  %t1 = lshr <8 x i16> %t0, <i16 9, i16 9, i16 9, i16 9, i16 9, i16 9, i16 9, i16 9>
406  ret <8 x i16> %t1
407}
408define <8 x i16> @test_128_i16_x_8_65024_mask_lshr_10(<8 x i16> %a0) {
409; CHECK-LABEL: test_128_i16_x_8_65024_mask_lshr_10:
410; CHECK:       // %bb.0:
411; CHECK-NEXT:    ushr v0.8h, v0.8h, #10
412; CHECK-NEXT:    ret
413  %t0 = and <8 x i16> %a0, <i16 65024, i16 65024, i16 65024, i16 65024, i16 65024, i16 65024, i16 65024, i16 65024>
414  %t1 = lshr <8 x i16> %t0, <i16 10, i16 10, i16 10, i16 10, i16 10, i16 10, i16 10, i16 10>
415  ret <8 x i16> %t1
416}
417
418; ashr
419
420define <8 x i16> @test_128_i16_x_8_127_mask_ashr_1(<8 x i16> %a0) {
421; CHECK-LABEL: test_128_i16_x_8_127_mask_ashr_1:
422; CHECK:       // %bb.0:
423; CHECK-NEXT:    movi v1.8h, #127
424; CHECK-NEXT:    and v0.16b, v0.16b, v1.16b
425; CHECK-NEXT:    ushr v0.8h, v0.8h, #1
426; CHECK-NEXT:    ret
427  %t0 = and <8 x i16> %a0, <i16 127, i16 127, i16 127, i16 127, i16 127, i16 127, i16 127, i16 127>
428  %t1 = ashr <8 x i16> %t0, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>
429  ret <8 x i16> %t1
430}
431
432define <8 x i16> @test_128_i16_x_8_2032_mask_ashr_3(<8 x i16> %a0) {
433; CHECK-LABEL: test_128_i16_x_8_2032_mask_ashr_3:
434; CHECK:       // %bb.0:
435; CHECK-NEXT:    mov w8, #2032
436; CHECK-NEXT:    dup v1.8h, w8
437; CHECK-NEXT:    and v0.16b, v0.16b, v1.16b
438; CHECK-NEXT:    ushr v0.8h, v0.8h, #3
439; CHECK-NEXT:    ret
440  %t0 = and <8 x i16> %a0, <i16 2032, i16 2032, i16 2032, i16 2032, i16 2032, i16 2032, i16 2032, i16 2032>
441  %t1 = ashr <8 x i16> %t0, <i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3>
442  ret <8 x i16> %t1
443}
444define <8 x i16> @test_128_i16_x_8_2032_mask_ashr_4(<8 x i16> %a0) {
445; CHECK-LABEL: test_128_i16_x_8_2032_mask_ashr_4:
446; CHECK:       // %bb.0:
447; CHECK-NEXT:    mov w8, #2032
448; CHECK-NEXT:    dup v1.8h, w8
449; CHECK-NEXT:    and v0.16b, v0.16b, v1.16b
450; CHECK-NEXT:    ushr v0.8h, v0.8h, #4
451; CHECK-NEXT:    ret
452  %t0 = and <8 x i16> %a0, <i16 2032, i16 2032, i16 2032, i16 2032, i16 2032, i16 2032, i16 2032, i16 2032>
453  %t1 = ashr <8 x i16> %t0, <i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4>
454  ret <8 x i16> %t1
455}
456define <8 x i16> @test_128_i16_x_8_2032_mask_ashr_5(<8 x i16> %a0) {
457; CHECK-LABEL: test_128_i16_x_8_2032_mask_ashr_5:
458; CHECK:       // %bb.0:
459; CHECK-NEXT:    mov w8, #2032
460; CHECK-NEXT:    dup v1.8h, w8
461; CHECK-NEXT:    and v0.16b, v0.16b, v1.16b
462; CHECK-NEXT:    ushr v0.8h, v0.8h, #5
463; CHECK-NEXT:    ret
464  %t0 = and <8 x i16> %a0, <i16 2032, i16 2032, i16 2032, i16 2032, i16 2032, i16 2032, i16 2032, i16 2032>
465  %t1 = ashr <8 x i16> %t0, <i16 5, i16 5, i16 5, i16 5, i16 5, i16 5, i16 5, i16 5>
466  ret <8 x i16> %t1
467}
468define <8 x i16> @test_128_i16_x_8_2032_mask_ashr_6(<8 x i16> %a0) {
469; CHECK-LABEL: test_128_i16_x_8_2032_mask_ashr_6:
470; CHECK:       // %bb.0:
471; CHECK-NEXT:    mov w8, #2032
472; CHECK-NEXT:    dup v1.8h, w8
473; CHECK-NEXT:    and v0.16b, v0.16b, v1.16b
474; CHECK-NEXT:    ushr v0.8h, v0.8h, #6
475; CHECK-NEXT:    ret
476  %t0 = and <8 x i16> %a0, <i16 2032, i16 2032, i16 2032, i16 2032, i16 2032, i16 2032, i16 2032, i16 2032>
477  %t1 = ashr <8 x i16> %t0, <i16 6, i16 6, i16 6, i16 6, i16 6, i16 6, i16 6, i16 6>
478  ret <8 x i16> %t1
479}
480
481define <8 x i16> @test_128_i16_x_8_65024_mask_ashr_1(<8 x i16> %a0) {
482; CHECK-LABEL: test_128_i16_x_8_65024_mask_ashr_1:
483; CHECK:       // %bb.0:
484; CHECK-NEXT:    movi v1.8h, #254, lsl #8
485; CHECK-NEXT:    and v0.16b, v0.16b, v1.16b
486; CHECK-NEXT:    sshr v0.8h, v0.8h, #1
487; CHECK-NEXT:    ret
488  %t0 = and <8 x i16> %a0, <i16 65024, i16 65024, i16 65024, i16 65024, i16 65024, i16 65024, i16 65024, i16 65024>
489  %t1 = ashr <8 x i16> %t0, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>
490  ret <8 x i16> %t1
491}
492define <8 x i16> @test_128_i16_x_8_65024_mask_ashr_8(<8 x i16> %a0) {
493; CHECK-LABEL: test_128_i16_x_8_65024_mask_ashr_8:
494; CHECK:       // %bb.0:
495; CHECK-NEXT:    movi v1.8h, #254, lsl #8
496; CHECK-NEXT:    and v0.16b, v0.16b, v1.16b
497; CHECK-NEXT:    sshr v0.8h, v0.8h, #8
498; CHECK-NEXT:    ret
499  %t0 = and <8 x i16> %a0, <i16 65024, i16 65024, i16 65024, i16 65024, i16 65024, i16 65024, i16 65024, i16 65024>
500  %t1 = ashr <8 x i16> %t0, <i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8>
501  ret <8 x i16> %t1
502}
503define <8 x i16> @test_128_i16_x_8_65024_mask_ashr_9(<8 x i16> %a0) {
504; CHECK-LABEL: test_128_i16_x_8_65024_mask_ashr_9:
505; CHECK:       // %bb.0:
506; CHECK-NEXT:    sshr v0.8h, v0.8h, #9
507; CHECK-NEXT:    ret
508  %t0 = and <8 x i16> %a0, <i16 65024, i16 65024, i16 65024, i16 65024, i16 65024, i16 65024, i16 65024, i16 65024>
509  %t1 = ashr <8 x i16> %t0, <i16 9, i16 9, i16 9, i16 9, i16 9, i16 9, i16 9, i16 9>
510  ret <8 x i16> %t1
511}
512define <8 x i16> @test_128_i16_x_8_65024_mask_ashr_10(<8 x i16> %a0) {
513; CHECK-LABEL: test_128_i16_x_8_65024_mask_ashr_10:
514; CHECK:       // %bb.0:
515; CHECK-NEXT:    sshr v0.8h, v0.8h, #10
516; CHECK-NEXT:    ret
517  %t0 = and <8 x i16> %a0, <i16 65024, i16 65024, i16 65024, i16 65024, i16 65024, i16 65024, i16 65024, i16 65024>
518  %t1 = ashr <8 x i16> %t0, <i16 10, i16 10, i16 10, i16 10, i16 10, i16 10, i16 10, i16 10>
519  ret <8 x i16> %t1
520}
521
522; shl
523
524define <8 x i16> @test_128_i16_x_8_127_mask_shl_1(<8 x i16> %a0) {
525; CHECK-LABEL: test_128_i16_x_8_127_mask_shl_1:
526; CHECK:       // %bb.0:
527; CHECK-NEXT:    movi v1.8h, #127
528; CHECK-NEXT:    and v0.16b, v0.16b, v1.16b
529; CHECK-NEXT:    add v0.8h, v0.8h, v0.8h
530; CHECK-NEXT:    ret
531  %t0 = and <8 x i16> %a0, <i16 127, i16 127, i16 127, i16 127, i16 127, i16 127, i16 127, i16 127>
532  %t1 = shl <8 x i16> %t0, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>
533  ret <8 x i16> %t1
534}
535define <8 x i16> @test_128_i16_x_8_127_mask_shl_8(<8 x i16> %a0) {
536; CHECK-LABEL: test_128_i16_x_8_127_mask_shl_8:
537; CHECK:       // %bb.0:
538; CHECK-NEXT:    movi v1.8h, #127
539; CHECK-NEXT:    and v0.16b, v0.16b, v1.16b
540; CHECK-NEXT:    shl v0.8h, v0.8h, #8
541; CHECK-NEXT:    ret
542  %t0 = and <8 x i16> %a0, <i16 127, i16 127, i16 127, i16 127, i16 127, i16 127, i16 127, i16 127>
543  %t1 = shl <8 x i16> %t0, <i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8>
544  ret <8 x i16> %t1
545}
546define <8 x i16> @test_128_i16_x_8_127_mask_shl_9(<8 x i16> %a0) {
547; CHECK-LABEL: test_128_i16_x_8_127_mask_shl_9:
548; CHECK:       // %bb.0:
549; CHECK-NEXT:    shl v0.8h, v0.8h, #9
550; CHECK-NEXT:    ret
551  %t0 = and <8 x i16> %a0, <i16 127, i16 127, i16 127, i16 127, i16 127, i16 127, i16 127, i16 127>
552  %t1 = shl <8 x i16> %t0, <i16 9, i16 9, i16 9, i16 9, i16 9, i16 9, i16 9, i16 9>
553  ret <8 x i16> %t1
554}
555define <8 x i16> @test_128_i16_x_8_127_mask_shl_10(<8 x i16> %a0) {
556; CHECK-LABEL: test_128_i16_x_8_127_mask_shl_10:
557; CHECK:       // %bb.0:
558; CHECK-NEXT:    shl v0.8h, v0.8h, #10
559; CHECK-NEXT:    ret
560  %t0 = and <8 x i16> %a0, <i16 127, i16 127, i16 127, i16 127, i16 127, i16 127, i16 127, i16 127>
561  %t1 = shl <8 x i16> %t0, <i16 10, i16 10, i16 10, i16 10, i16 10, i16 10, i16 10, i16 10>
562  ret <8 x i16> %t1
563}
564
565define <8 x i16> @test_128_i16_x_8_2032_mask_shl_3(<8 x i16> %a0) {
566; CHECK-LABEL: test_128_i16_x_8_2032_mask_shl_3:
567; CHECK:       // %bb.0:
568; CHECK-NEXT:    mov w8, #2032
569; CHECK-NEXT:    dup v1.8h, w8
570; CHECK-NEXT:    and v0.16b, v0.16b, v1.16b
571; CHECK-NEXT:    shl v0.8h, v0.8h, #3
572; CHECK-NEXT:    ret
573  %t0 = and <8 x i16> %a0, <i16 2032, i16 2032, i16 2032, i16 2032, i16 2032, i16 2032, i16 2032, i16 2032>
574  %t1 = shl <8 x i16> %t0, <i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3>
575  ret <8 x i16> %t1
576}
577define <8 x i16> @test_128_i16_x_8_2032_mask_shl_4(<8 x i16> %a0) {
578; CHECK-LABEL: test_128_i16_x_8_2032_mask_shl_4:
579; CHECK:       // %bb.0:
580; CHECK-NEXT:    mov w8, #2032
581; CHECK-NEXT:    dup v1.8h, w8
582; CHECK-NEXT:    and v0.16b, v0.16b, v1.16b
583; CHECK-NEXT:    shl v0.8h, v0.8h, #4
584; CHECK-NEXT:    ret
585  %t0 = and <8 x i16> %a0, <i16 2032, i16 2032, i16 2032, i16 2032, i16 2032, i16 2032, i16 2032, i16 2032>
586  %t1 = shl <8 x i16> %t0, <i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4>
587  ret <8 x i16> %t1
588}
589define <8 x i16> @test_128_i16_x_8_2032_mask_shl_5(<8 x i16> %a0) {
590; CHECK-LABEL: test_128_i16_x_8_2032_mask_shl_5:
591; CHECK:       // %bb.0:
592; CHECK-NEXT:    mov w8, #2032
593; CHECK-NEXT:    dup v1.8h, w8
594; CHECK-NEXT:    and v0.16b, v0.16b, v1.16b
595; CHECK-NEXT:    shl v0.8h, v0.8h, #5
596; CHECK-NEXT:    ret
597  %t0 = and <8 x i16> %a0, <i16 2032, i16 2032, i16 2032, i16 2032, i16 2032, i16 2032, i16 2032, i16 2032>
598  %t1 = shl <8 x i16> %t0, <i16 5, i16 5, i16 5, i16 5, i16 5, i16 5, i16 5, i16 5>
599  ret <8 x i16> %t1
600}
601define <8 x i16> @test_128_i16_x_8_2032_mask_shl_6(<8 x i16> %a0) {
602; CHECK-LABEL: test_128_i16_x_8_2032_mask_shl_6:
603; CHECK:       // %bb.0:
604; CHECK-NEXT:    mov w8, #2032
605; CHECK-NEXT:    dup v1.8h, w8
606; CHECK-NEXT:    and v0.16b, v0.16b, v1.16b
607; CHECK-NEXT:    shl v0.8h, v0.8h, #6
608; CHECK-NEXT:    ret
609  %t0 = and <8 x i16> %a0, <i16 2032, i16 2032, i16 2032, i16 2032, i16 2032, i16 2032, i16 2032, i16 2032>
610  %t1 = shl <8 x i16> %t0, <i16 6, i16 6, i16 6, i16 6, i16 6, i16 6, i16 6, i16 6>
611  ret <8 x i16> %t1
612}
613
614define <8 x i16> @test_128_i16_x_8_65024_mask_shl_1(<8 x i16> %a0) {
615; CHECK-LABEL: test_128_i16_x_8_65024_mask_shl_1:
616; CHECK:       // %bb.0:
617; CHECK-NEXT:    movi v1.8h, #254, lsl #8
618; CHECK-NEXT:    and v0.16b, v0.16b, v1.16b
619; CHECK-NEXT:    add v0.8h, v0.8h, v0.8h
620; CHECK-NEXT:    ret
621  %t0 = and <8 x i16> %a0, <i16 65024, i16 65024, i16 65024, i16 65024, i16 65024, i16 65024, i16 65024, i16 65024>
622  %t1 = shl <8 x i16> %t0, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>
623  ret <8 x i16> %t1
624}
625
626;------------------------------------------------------------------------------;
627; 128-bit vector; 32-bit elements = 4 elements
628;------------------------------------------------------------------------------;
629
630; lshr
631
632define <4 x i32> @test_128_i32_x_4_32767_mask_lshr_1(<4 x i32> %a0) {
633; CHECK-LABEL: test_128_i32_x_4_32767_mask_lshr_1:
634; CHECK:       // %bb.0:
635; CHECK-NEXT:    movi v1.4s, #127, msl #8
636; CHECK-NEXT:    and v0.16b, v0.16b, v1.16b
637; CHECK-NEXT:    ushr v0.4s, v0.4s, #1
638; CHECK-NEXT:    ret
639  %t0 = and <4 x i32> %a0, <i32 32767, i32 32767, i32 32767, i32 32767>
640  %t1 = lshr <4 x i32> %t0, <i32 1, i32 1, i32 1, i32 1>
641  ret <4 x i32> %t1
642}
643
644define <4 x i32> @test_128_i32_x_4_8388352_mask_lshr_7(<4 x i32> %a0) {
645; CHECK-LABEL: test_128_i32_x_4_8388352_mask_lshr_7:
646; CHECK:       // %bb.0:
647; CHECK-NEXT:    mov w8, #8388352
648; CHECK-NEXT:    dup v1.4s, w8
649; CHECK-NEXT:    and v0.16b, v0.16b, v1.16b
650; CHECK-NEXT:    ushr v0.4s, v0.4s, #7
651; CHECK-NEXT:    ret
652  %t0 = and <4 x i32> %a0, <i32 8388352, i32 8388352, i32 8388352, i32 8388352>
653  %t1 = lshr <4 x i32> %t0, <i32 7, i32 7, i32 7, i32 7>
654  ret <4 x i32> %t1
655}
656define <4 x i32> @test_128_i32_x_4_8388352_mask_lshr_8(<4 x i32> %a0) {
657; CHECK-LABEL: test_128_i32_x_4_8388352_mask_lshr_8:
658; CHECK:       // %bb.0:
659; CHECK-NEXT:    mov w8, #8388352
660; CHECK-NEXT:    dup v1.4s, w8
661; CHECK-NEXT:    and v0.16b, v0.16b, v1.16b
662; CHECK-NEXT:    ushr v0.4s, v0.4s, #8
663; CHECK-NEXT:    ret
664  %t0 = and <4 x i32> %a0, <i32 8388352, i32 8388352, i32 8388352, i32 8388352>
665  %t1 = lshr <4 x i32> %t0, <i32 8, i32 8, i32 8, i32 8>
666  ret <4 x i32> %t1
667}
668define <4 x i32> @test_128_i32_x_4_8388352_mask_lshr_9(<4 x i32> %a0) {
669; CHECK-LABEL: test_128_i32_x_4_8388352_mask_lshr_9:
670; CHECK:       // %bb.0:
671; CHECK-NEXT:    mov w8, #8388352
672; CHECK-NEXT:    dup v1.4s, w8
673; CHECK-NEXT:    and v0.16b, v0.16b, v1.16b
674; CHECK-NEXT:    ushr v0.4s, v0.4s, #9
675; CHECK-NEXT:    ret
676  %t0 = and <4 x i32> %a0, <i32 8388352, i32 8388352, i32 8388352, i32 8388352>
677  %t1 = lshr <4 x i32> %t0, <i32 9, i32 9, i32 9, i32 9>
678  ret <4 x i32> %t1
679}
680define <4 x i32> @test_128_i32_x_4_8388352_mask_lshr_10(<4 x i32> %a0) {
681; CHECK-LABEL: test_128_i32_x_4_8388352_mask_lshr_10:
682; CHECK:       // %bb.0:
683; CHECK-NEXT:    mov w8, #8388352
684; CHECK-NEXT:    dup v1.4s, w8
685; CHECK-NEXT:    and v0.16b, v0.16b, v1.16b
686; CHECK-NEXT:    ushr v0.4s, v0.4s, #10
687; CHECK-NEXT:    ret
688  %t0 = and <4 x i32> %a0, <i32 8388352, i32 8388352, i32 8388352, i32 8388352>
689  %t1 = lshr <4 x i32> %t0, <i32 10, i32 10, i32 10, i32 10>
690  ret <4 x i32> %t1
691}
692
693define <4 x i32> @test_128_i32_x_4_4294836224_mask_lshr_1(<4 x i32> %a0) {
694; CHECK-LABEL: test_128_i32_x_4_4294836224_mask_lshr_1:
695; CHECK:       // %bb.0:
696; CHECK-NEXT:    mvni v1.4s, #1, msl #16
697; CHECK-NEXT:    and v0.16b, v0.16b, v1.16b
698; CHECK-NEXT:    ushr v0.4s, v0.4s, #1
699; CHECK-NEXT:    ret
700  %t0 = and <4 x i32> %a0, <i32 4294836224, i32 4294836224, i32 4294836224, i32 4294836224>
701  %t1 = lshr <4 x i32> %t0, <i32 1, i32 1, i32 1, i32 1>
702  ret <4 x i32> %t1
703}
704define <4 x i32> @test_128_i32_x_4_4294836224_mask_lshr_16(<4 x i32> %a0) {
705; CHECK-LABEL: test_128_i32_x_4_4294836224_mask_lshr_16:
706; CHECK:       // %bb.0:
707; CHECK-NEXT:    mvni v1.4s, #1, msl #16
708; CHECK-NEXT:    and v0.16b, v0.16b, v1.16b
709; CHECK-NEXT:    ushr v0.4s, v0.4s, #16
710; CHECK-NEXT:    ret
711  %t0 = and <4 x i32> %a0, <i32 4294836224, i32 4294836224, i32 4294836224, i32 4294836224>
712  %t1 = lshr <4 x i32> %t0, <i32 16, i32 16, i32 16, i32 16>
713  ret <4 x i32> %t1
714}
715define <4 x i32> @test_128_i32_x_4_4294836224_mask_lshr_17(<4 x i32> %a0) {
716; CHECK-LABEL: test_128_i32_x_4_4294836224_mask_lshr_17:
717; CHECK:       // %bb.0:
718; CHECK-NEXT:    ushr v0.4s, v0.4s, #17
719; CHECK-NEXT:    ret
720  %t0 = and <4 x i32> %a0, <i32 4294836224, i32 4294836224, i32 4294836224, i32 4294836224>
721  %t1 = lshr <4 x i32> %t0, <i32 17, i32 17, i32 17, i32 17>
722  ret <4 x i32> %t1
723}
724define <4 x i32> @test_128_i32_x_4_4294836224_mask_lshr_18(<4 x i32> %a0) {
725; CHECK-LABEL: test_128_i32_x_4_4294836224_mask_lshr_18:
726; CHECK:       // %bb.0:
727; CHECK-NEXT:    ushr v0.4s, v0.4s, #18
728; CHECK-NEXT:    ret
729  %t0 = and <4 x i32> %a0, <i32 4294836224, i32 4294836224, i32 4294836224, i32 4294836224>
730  %t1 = lshr <4 x i32> %t0, <i32 18, i32 18, i32 18, i32 18>
731  ret <4 x i32> %t1
732}
733
734; ashr
735
736define <4 x i32> @test_128_i32_x_4_32767_mask_ashr_1(<4 x i32> %a0) {
737; CHECK-LABEL: test_128_i32_x_4_32767_mask_ashr_1:
738; CHECK:       // %bb.0:
739; CHECK-NEXT:    movi v1.4s, #127, msl #8
740; CHECK-NEXT:    and v0.16b, v0.16b, v1.16b
741; CHECK-NEXT:    ushr v0.4s, v0.4s, #1
742; CHECK-NEXT:    ret
743  %t0 = and <4 x i32> %a0, <i32 32767, i32 32767, i32 32767, i32 32767>
744  %t1 = ashr <4 x i32> %t0, <i32 1, i32 1, i32 1, i32 1>
745  ret <4 x i32> %t1
746}
747
748define <4 x i32> @test_128_i32_x_4_8388352_mask_ashr_7(<4 x i32> %a0) {
749; CHECK-LABEL: test_128_i32_x_4_8388352_mask_ashr_7:
750; CHECK:       // %bb.0:
751; CHECK-NEXT:    mov w8, #8388352
752; CHECK-NEXT:    dup v1.4s, w8
753; CHECK-NEXT:    and v0.16b, v0.16b, v1.16b
754; CHECK-NEXT:    ushr v0.4s, v0.4s, #7
755; CHECK-NEXT:    ret
756  %t0 = and <4 x i32> %a0, <i32 8388352, i32 8388352, i32 8388352, i32 8388352>
757  %t1 = ashr <4 x i32> %t0, <i32 7, i32 7, i32 7, i32 7>
758  ret <4 x i32> %t1
759}
760define <4 x i32> @test_128_i32_x_4_8388352_mask_ashr_8(<4 x i32> %a0) {
761; CHECK-LABEL: test_128_i32_x_4_8388352_mask_ashr_8:
762; CHECK:       // %bb.0:
763; CHECK-NEXT:    mov w8, #8388352
764; CHECK-NEXT:    dup v1.4s, w8
765; CHECK-NEXT:    and v0.16b, v0.16b, v1.16b
766; CHECK-NEXT:    ushr v0.4s, v0.4s, #8
767; CHECK-NEXT:    ret
768  %t0 = and <4 x i32> %a0, <i32 8388352, i32 8388352, i32 8388352, i32 8388352>
769  %t1 = ashr <4 x i32> %t0, <i32 8, i32 8, i32 8, i32 8>
770  ret <4 x i32> %t1
771}
772define <4 x i32> @test_128_i32_x_4_8388352_mask_ashr_9(<4 x i32> %a0) {
773; CHECK-LABEL: test_128_i32_x_4_8388352_mask_ashr_9:
774; CHECK:       // %bb.0:
775; CHECK-NEXT:    mov w8, #8388352
776; CHECK-NEXT:    dup v1.4s, w8
777; CHECK-NEXT:    and v0.16b, v0.16b, v1.16b
778; CHECK-NEXT:    ushr v0.4s, v0.4s, #9
779; CHECK-NEXT:    ret
780  %t0 = and <4 x i32> %a0, <i32 8388352, i32 8388352, i32 8388352, i32 8388352>
781  %t1 = ashr <4 x i32> %t0, <i32 9, i32 9, i32 9, i32 9>
782  ret <4 x i32> %t1
783}
784define <4 x i32> @test_128_i32_x_4_8388352_mask_ashr_10(<4 x i32> %a0) {
785; CHECK-LABEL: test_128_i32_x_4_8388352_mask_ashr_10:
786; CHECK:       // %bb.0:
787; CHECK-NEXT:    mov w8, #8388352
788; CHECK-NEXT:    dup v1.4s, w8
789; CHECK-NEXT:    and v0.16b, v0.16b, v1.16b
790; CHECK-NEXT:    ushr v0.4s, v0.4s, #10
791; CHECK-NEXT:    ret
792  %t0 = and <4 x i32> %a0, <i32 8388352, i32 8388352, i32 8388352, i32 8388352>
793  %t1 = ashr <4 x i32> %t0, <i32 10, i32 10, i32 10, i32 10>
794  ret <4 x i32> %t1
795}
796
797define <4 x i32> @test_128_i32_x_4_4294836224_mask_ashr_1(<4 x i32> %a0) {
798; CHECK-LABEL: test_128_i32_x_4_4294836224_mask_ashr_1:
799; CHECK:       // %bb.0:
800; CHECK-NEXT:    mvni v1.4s, #1, msl #16
801; CHECK-NEXT:    and v0.16b, v0.16b, v1.16b
802; CHECK-NEXT:    sshr v0.4s, v0.4s, #1
803; CHECK-NEXT:    ret
804  %t0 = and <4 x i32> %a0, <i32 4294836224, i32 4294836224, i32 4294836224, i32 4294836224>
805  %t1 = ashr <4 x i32> %t0, <i32 1, i32 1, i32 1, i32 1>
806  ret <4 x i32> %t1
807}
808define <4 x i32> @test_128_i32_x_4_4294836224_mask_ashr_16(<4 x i32> %a0) {
809; CHECK-LABEL: test_128_i32_x_4_4294836224_mask_ashr_16:
810; CHECK:       // %bb.0:
811; CHECK-NEXT:    mvni v1.4s, #1, msl #16
812; CHECK-NEXT:    and v0.16b, v0.16b, v1.16b
813; CHECK-NEXT:    sshr v0.4s, v0.4s, #16
814; CHECK-NEXT:    ret
815  %t0 = and <4 x i32> %a0, <i32 4294836224, i32 4294836224, i32 4294836224, i32 4294836224>
816  %t1 = ashr <4 x i32> %t0, <i32 16, i32 16, i32 16, i32 16>
817  ret <4 x i32> %t1
818}
819define <4 x i32> @test_128_i32_x_4_4294836224_mask_ashr_17(<4 x i32> %a0) {
820; CHECK-LABEL: test_128_i32_x_4_4294836224_mask_ashr_17:
821; CHECK:       // %bb.0:
822; CHECK-NEXT:    sshr v0.4s, v0.4s, #17
823; CHECK-NEXT:    ret
824  %t0 = and <4 x i32> %a0, <i32 4294836224, i32 4294836224, i32 4294836224, i32 4294836224>
825  %t1 = ashr <4 x i32> %t0, <i32 17, i32 17, i32 17, i32 17>
826  ret <4 x i32> %t1
827}
828define <4 x i32> @test_128_i32_x_4_4294836224_mask_ashr_18(<4 x i32> %a0) {
829; CHECK-LABEL: test_128_i32_x_4_4294836224_mask_ashr_18:
830; CHECK:       // %bb.0:
831; CHECK-NEXT:    sshr v0.4s, v0.4s, #18
832; CHECK-NEXT:    ret
833  %t0 = and <4 x i32> %a0, <i32 4294836224, i32 4294836224, i32 4294836224, i32 4294836224>
834  %t1 = ashr <4 x i32> %t0, <i32 18, i32 18, i32 18, i32 18>
835  ret <4 x i32> %t1
836}
837
838; shl
839
840define <4 x i32> @test_128_i32_x_4_32767_mask_shl_1(<4 x i32> %a0) {
841; CHECK-LABEL: test_128_i32_x_4_32767_mask_shl_1:
842; CHECK:       // %bb.0:
843; CHECK-NEXT:    movi v1.4s, #127, msl #8
844; CHECK-NEXT:    and v0.16b, v0.16b, v1.16b
845; CHECK-NEXT:    add v0.4s, v0.4s, v0.4s
846; CHECK-NEXT:    ret
847  %t0 = and <4 x i32> %a0, <i32 32767, i32 32767, i32 32767, i32 32767>
848  %t1 = shl <4 x i32> %t0, <i32 1, i32 1, i32 1, i32 1>
849  ret <4 x i32> %t1
850}
851define <4 x i32> @test_128_i32_x_4_32767_mask_shl_16(<4 x i32> %a0) {
852; CHECK-LABEL: test_128_i32_x_4_32767_mask_shl_16:
853; CHECK:       // %bb.0:
854; CHECK-NEXT:    movi v1.4s, #127, msl #8
855; CHECK-NEXT:    and v0.16b, v0.16b, v1.16b
856; CHECK-NEXT:    shl v0.4s, v0.4s, #16
857; CHECK-NEXT:    ret
858  %t0 = and <4 x i32> %a0, <i32 32767, i32 32767, i32 32767, i32 32767>
859  %t1 = shl <4 x i32> %t0, <i32 16, i32 16, i32 16, i32 16>
860  ret <4 x i32> %t1
861}
862define <4 x i32> @test_128_i32_x_4_32767_mask_shl_17(<4 x i32> %a0) {
863; CHECK-LABEL: test_128_i32_x_4_32767_mask_shl_17:
864; CHECK:       // %bb.0:
865; CHECK-NEXT:    shl v0.4s, v0.4s, #17
866; CHECK-NEXT:    ret
867  %t0 = and <4 x i32> %a0, <i32 32767, i32 32767, i32 32767, i32 32767>
868  %t1 = shl <4 x i32> %t0, <i32 17, i32 17, i32 17, i32 17>
869  ret <4 x i32> %t1
870}
871define <4 x i32> @test_128_i32_x_4_32767_mask_shl_18(<4 x i32> %a0) {
872; CHECK-LABEL: test_128_i32_x_4_32767_mask_shl_18:
873; CHECK:       // %bb.0:
874; CHECK-NEXT:    shl v0.4s, v0.4s, #18
875; CHECK-NEXT:    ret
876  %t0 = and <4 x i32> %a0, <i32 32767, i32 32767, i32 32767, i32 32767>
877  %t1 = shl <4 x i32> %t0, <i32 18, i32 18, i32 18, i32 18>
878  ret <4 x i32> %t1
879}
880
881define <4 x i32> @test_128_i32_x_4_8388352_mask_shl_7(<4 x i32> %a0) {
882; CHECK-LABEL: test_128_i32_x_4_8388352_mask_shl_7:
883; CHECK:       // %bb.0:
884; CHECK-NEXT:    mov w8, #8388352
885; CHECK-NEXT:    dup v1.4s, w8
886; CHECK-NEXT:    and v0.16b, v0.16b, v1.16b
887; CHECK-NEXT:    shl v0.4s, v0.4s, #7
888; CHECK-NEXT:    ret
889  %t0 = and <4 x i32> %a0, <i32 8388352, i32 8388352, i32 8388352, i32 8388352>
890  %t1 = shl <4 x i32> %t0, <i32 7, i32 7, i32 7, i32 7>
891  ret <4 x i32> %t1
892}
893define <4 x i32> @test_128_i32_x_4_8388352_mask_shl_8(<4 x i32> %a0) {
894; CHECK-LABEL: test_128_i32_x_4_8388352_mask_shl_8:
895; CHECK:       // %bb.0:
896; CHECK-NEXT:    mov w8, #8388352
897; CHECK-NEXT:    dup v1.4s, w8
898; CHECK-NEXT:    and v0.16b, v0.16b, v1.16b
899; CHECK-NEXT:    shl v0.4s, v0.4s, #8
900; CHECK-NEXT:    ret
901  %t0 = and <4 x i32> %a0, <i32 8388352, i32 8388352, i32 8388352, i32 8388352>
902  %t1 = shl <4 x i32> %t0, <i32 8, i32 8, i32 8, i32 8>
903  ret <4 x i32> %t1
904}
905define <4 x i32> @test_128_i32_x_4_8388352_mask_shl_9(<4 x i32> %a0) {
906; CHECK-LABEL: test_128_i32_x_4_8388352_mask_shl_9:
907; CHECK:       // %bb.0:
908; CHECK-NEXT:    mov w8, #8388352
909; CHECK-NEXT:    dup v1.4s, w8
910; CHECK-NEXT:    and v0.16b, v0.16b, v1.16b
911; CHECK-NEXT:    shl v0.4s, v0.4s, #9
912; CHECK-NEXT:    ret
913  %t0 = and <4 x i32> %a0, <i32 8388352, i32 8388352, i32 8388352, i32 8388352>
914  %t1 = shl <4 x i32> %t0, <i32 9, i32 9, i32 9, i32 9>
915  ret <4 x i32> %t1
916}
917define <4 x i32> @test_128_i32_x_4_8388352_mask_shl_10(<4 x i32> %a0) {
918; CHECK-LABEL: test_128_i32_x_4_8388352_mask_shl_10:
919; CHECK:       // %bb.0:
920; CHECK-NEXT:    mov w8, #8388352
921; CHECK-NEXT:    dup v1.4s, w8
922; CHECK-NEXT:    and v0.16b, v0.16b, v1.16b
923; CHECK-NEXT:    shl v0.4s, v0.4s, #10
924; CHECK-NEXT:    ret
925  %t0 = and <4 x i32> %a0, <i32 8388352, i32 8388352, i32 8388352, i32 8388352>
926  %t1 = shl <4 x i32> %t0, <i32 10, i32 10, i32 10, i32 10>
927  ret <4 x i32> %t1
928}
929
930define <4 x i32> @test_128_i32_x_4_4294836224_mask_shl_1(<4 x i32> %a0) {
931; CHECK-LABEL: test_128_i32_x_4_4294836224_mask_shl_1:
932; CHECK:       // %bb.0:
933; CHECK-NEXT:    mvni v1.4s, #1, msl #16
934; CHECK-NEXT:    and v0.16b, v0.16b, v1.16b
935; CHECK-NEXT:    add v0.4s, v0.4s, v0.4s
936; CHECK-NEXT:    ret
937  %t0 = and <4 x i32> %a0, <i32 4294836224, i32 4294836224, i32 4294836224, i32 4294836224>
938  %t1 = shl <4 x i32> %t0, <i32 1, i32 1, i32 1, i32 1>
939  ret <4 x i32> %t1
940}
941
942;------------------------------------------------------------------------------;
943; 128-bit vector; 64-bit elements = 2 elements
944;------------------------------------------------------------------------------;
945
946; lshr
947
948define <2 x i64> @test_128_i64_x_2_2147483647_mask_lshr_1(<2 x i64> %a0) {
949; CHECK-LABEL: test_128_i64_x_2_2147483647_mask_lshr_1:
950; CHECK:       // %bb.0:
951; CHECK-NEXT:    mov w8, #2147483647
952; CHECK-NEXT:    dup v1.2d, x8
953; CHECK-NEXT:    and v0.16b, v0.16b, v1.16b
954; CHECK-NEXT:    ushr v0.2d, v0.2d, #1
955; CHECK-NEXT:    ret
956  %t0 = and <2 x i64> %a0, <i64 2147483647, i64 2147483647>
957  %t1 = lshr <2 x i64> %t0, <i64 1, i64 1>
958  ret <2 x i64> %t1
959}
960
961define <2 x i64> @test_128_i64_x_2_140737488289792_mask_lshr_15(<2 x i64> %a0) {
962; CHECK-LABEL: test_128_i64_x_2_140737488289792_mask_lshr_15:
963; CHECK:       // %bb.0:
964; CHECK-NEXT:    mov x8, #140737488289792
965; CHECK-NEXT:    dup v1.2d, x8
966; CHECK-NEXT:    and v0.16b, v0.16b, v1.16b
967; CHECK-NEXT:    ushr v0.2d, v0.2d, #15
968; CHECK-NEXT:    ret
969  %t0 = and <2 x i64> %a0, <i64 140737488289792, i64 140737488289792>
970  %t1 = lshr <2 x i64> %t0, <i64 15, i64 15>
971  ret <2 x i64> %t1
972}
973define <2 x i64> @test_128_i64_x_2_140737488289792_mask_lshr_16(<2 x i64> %a0) {
974; CHECK-LABEL: test_128_i64_x_2_140737488289792_mask_lshr_16:
975; CHECK:       // %bb.0:
976; CHECK-NEXT:    mov x8, #140737488289792
977; CHECK-NEXT:    dup v1.2d, x8
978; CHECK-NEXT:    and v0.16b, v0.16b, v1.16b
979; CHECK-NEXT:    ushr v0.2d, v0.2d, #16
980; CHECK-NEXT:    ret
981  %t0 = and <2 x i64> %a0, <i64 140737488289792, i64 140737488289792>
982  %t1 = lshr <2 x i64> %t0, <i64 16, i64 16>
983  ret <2 x i64> %t1
984}
985define <2 x i64> @test_128_i64_x_2_140737488289792_mask_lshr_17(<2 x i64> %a0) {
986; CHECK-LABEL: test_128_i64_x_2_140737488289792_mask_lshr_17:
987; CHECK:       // %bb.0:
988; CHECK-NEXT:    mov x8, #140737488289792
989; CHECK-NEXT:    dup v1.2d, x8
990; CHECK-NEXT:    and v0.16b, v0.16b, v1.16b
991; CHECK-NEXT:    ushr v0.2d, v0.2d, #17
992; CHECK-NEXT:    ret
993  %t0 = and <2 x i64> %a0, <i64 140737488289792, i64 140737488289792>
994  %t1 = lshr <2 x i64> %t0, <i64 17, i64 17>
995  ret <2 x i64> %t1
996}
997define <2 x i64> @test_128_i64_x_2_140737488289792_mask_lshr_18(<2 x i64> %a0) {
998; CHECK-LABEL: test_128_i64_x_2_140737488289792_mask_lshr_18:
999; CHECK:       // %bb.0:
1000; CHECK-NEXT:    mov x8, #140737488289792
1001; CHECK-NEXT:    dup v1.2d, x8
1002; CHECK-NEXT:    and v0.16b, v0.16b, v1.16b
1003; CHECK-NEXT:    ushr v0.2d, v0.2d, #18
1004; CHECK-NEXT:    ret
1005  %t0 = and <2 x i64> %a0, <i64 140737488289792, i64 140737488289792>
1006  %t1 = lshr <2 x i64> %t0, <i64 18, i64 18>
1007  ret <2 x i64> %t1
1008}
1009
1010define <2 x i64> @test_128_i64_x_2_18446744065119617024_mask_lshr_1(<2 x i64> %a0) {
1011; CHECK-LABEL: test_128_i64_x_2_18446744065119617024_mask_lshr_1:
1012; CHECK:       // %bb.0:
1013; CHECK-NEXT:    mov x8, #-8589934592
1014; CHECK-NEXT:    dup v1.2d, x8
1015; CHECK-NEXT:    and v0.16b, v0.16b, v1.16b
1016; CHECK-NEXT:    ushr v0.2d, v0.2d, #1
1017; CHECK-NEXT:    ret
1018  %t0 = and <2 x i64> %a0, <i64 18446744065119617024, i64 18446744065119617024>
1019  %t1 = lshr <2 x i64> %t0, <i64 1, i64 1>
1020  ret <2 x i64> %t1
1021}
1022define <2 x i64> @test_128_i64_x_2_18446744065119617024_mask_lshr_32(<2 x i64> %a0) {
1023; CHECK-LABEL: test_128_i64_x_2_18446744065119617024_mask_lshr_32:
1024; CHECK:       // %bb.0:
1025; CHECK-NEXT:    mov x8, #-8589934592
1026; CHECK-NEXT:    dup v1.2d, x8
1027; CHECK-NEXT:    and v0.16b, v0.16b, v1.16b
1028; CHECK-NEXT:    ushr v0.2d, v0.2d, #32
1029; CHECK-NEXT:    ret
1030  %t0 = and <2 x i64> %a0, <i64 18446744065119617024, i64 18446744065119617024>
1031  %t1 = lshr <2 x i64> %t0, <i64 32, i64 32>
1032  ret <2 x i64> %t1
1033}
1034define <2 x i64> @test_128_i64_x_2_18446744065119617024_mask_lshr_33(<2 x i64> %a0) {
1035; CHECK-LABEL: test_128_i64_x_2_18446744065119617024_mask_lshr_33:
1036; CHECK:       // %bb.0:
1037; CHECK-NEXT:    ushr v0.2d, v0.2d, #33
1038; CHECK-NEXT:    ret
1039  %t0 = and <2 x i64> %a0, <i64 18446744065119617024, i64 18446744065119617024>
1040  %t1 = lshr <2 x i64> %t0, <i64 33, i64 33>
1041  ret <2 x i64> %t1
1042}
1043define <2 x i64> @test_128_i64_x_2_18446744065119617024_mask_lshr_34(<2 x i64> %a0) {
1044; CHECK-LABEL: test_128_i64_x_2_18446744065119617024_mask_lshr_34:
1045; CHECK:       // %bb.0:
1046; CHECK-NEXT:    ushr v0.2d, v0.2d, #34
1047; CHECK-NEXT:    ret
1048  %t0 = and <2 x i64> %a0, <i64 18446744065119617024, i64 18446744065119617024>
1049  %t1 = lshr <2 x i64> %t0, <i64 34, i64 34>
1050  ret <2 x i64> %t1
1051}
1052
1053; ashr
1054
1055define <2 x i64> @test_128_i64_x_2_2147483647_mask_ashr_1(<2 x i64> %a0) {
1056; CHECK-LABEL: test_128_i64_x_2_2147483647_mask_ashr_1:
1057; CHECK:       // %bb.0:
1058; CHECK-NEXT:    mov w8, #2147483647
1059; CHECK-NEXT:    dup v1.2d, x8
1060; CHECK-NEXT:    and v0.16b, v0.16b, v1.16b
1061; CHECK-NEXT:    ushr v0.2d, v0.2d, #1
1062; CHECK-NEXT:    ret
1063  %t0 = and <2 x i64> %a0, <i64 2147483647, i64 2147483647>
1064  %t1 = ashr <2 x i64> %t0, <i64 1, i64 1>
1065  ret <2 x i64> %t1
1066}
1067
1068define <2 x i64> @test_128_i64_x_2_140737488289792_mask_ashr_15(<2 x i64> %a0) {
1069; CHECK-LABEL: test_128_i64_x_2_140737488289792_mask_ashr_15:
1070; CHECK:       // %bb.0:
1071; CHECK-NEXT:    mov x8, #140737488289792
1072; CHECK-NEXT:    dup v1.2d, x8
1073; CHECK-NEXT:    and v0.16b, v0.16b, v1.16b
1074; CHECK-NEXT:    ushr v0.2d, v0.2d, #15
1075; CHECK-NEXT:    ret
1076  %t0 = and <2 x i64> %a0, <i64 140737488289792, i64 140737488289792>
1077  %t1 = ashr <2 x i64> %t0, <i64 15, i64 15>
1078  ret <2 x i64> %t1
1079}
1080define <2 x i64> @test_128_i64_x_2_140737488289792_mask_ashr_16(<2 x i64> %a0) {
1081; CHECK-LABEL: test_128_i64_x_2_140737488289792_mask_ashr_16:
1082; CHECK:       // %bb.0:
1083; CHECK-NEXT:    mov x8, #140737488289792
1084; CHECK-NEXT:    dup v1.2d, x8
1085; CHECK-NEXT:    and v0.16b, v0.16b, v1.16b
1086; CHECK-NEXT:    ushr v0.2d, v0.2d, #16
1087; CHECK-NEXT:    ret
1088  %t0 = and <2 x i64> %a0, <i64 140737488289792, i64 140737488289792>
1089  %t1 = ashr <2 x i64> %t0, <i64 16, i64 16>
1090  ret <2 x i64> %t1
1091}
1092define <2 x i64> @test_128_i64_x_2_140737488289792_mask_ashr_17(<2 x i64> %a0) {
1093; CHECK-LABEL: test_128_i64_x_2_140737488289792_mask_ashr_17:
1094; CHECK:       // %bb.0:
1095; CHECK-NEXT:    mov x8, #140737488289792
1096; CHECK-NEXT:    dup v1.2d, x8
1097; CHECK-NEXT:    and v0.16b, v0.16b, v1.16b
1098; CHECK-NEXT:    ushr v0.2d, v0.2d, #17
1099; CHECK-NEXT:    ret
1100  %t0 = and <2 x i64> %a0, <i64 140737488289792, i64 140737488289792>
1101  %t1 = ashr <2 x i64> %t0, <i64 17, i64 17>
1102  ret <2 x i64> %t1
1103}
1104define <2 x i64> @test_128_i64_x_2_140737488289792_mask_ashr_18(<2 x i64> %a0) {
1105; CHECK-LABEL: test_128_i64_x_2_140737488289792_mask_ashr_18:
1106; CHECK:       // %bb.0:
1107; CHECK-NEXT:    mov x8, #140737488289792
1108; CHECK-NEXT:    dup v1.2d, x8
1109; CHECK-NEXT:    and v0.16b, v0.16b, v1.16b
1110; CHECK-NEXT:    ushr v0.2d, v0.2d, #18
1111; CHECK-NEXT:    ret
1112  %t0 = and <2 x i64> %a0, <i64 140737488289792, i64 140737488289792>
1113  %t1 = ashr <2 x i64> %t0, <i64 18, i64 18>
1114  ret <2 x i64> %t1
1115}
1116
1117define <2 x i64> @test_128_i64_x_2_18446744065119617024_mask_ashr_1(<2 x i64> %a0) {
1118; CHECK-LABEL: test_128_i64_x_2_18446744065119617024_mask_ashr_1:
1119; CHECK:       // %bb.0:
1120; CHECK-NEXT:    mov x8, #-8589934592
1121; CHECK-NEXT:    dup v1.2d, x8
1122; CHECK-NEXT:    and v0.16b, v0.16b, v1.16b
1123; CHECK-NEXT:    sshr v0.2d, v0.2d, #1
1124; CHECK-NEXT:    ret
1125  %t0 = and <2 x i64> %a0, <i64 18446744065119617024, i64 18446744065119617024>
1126  %t1 = ashr <2 x i64> %t0, <i64 1, i64 1>
1127  ret <2 x i64> %t1
1128}
1129define <2 x i64> @test_128_i64_x_2_18446744065119617024_mask_ashr_32(<2 x i64> %a0) {
1130; CHECK-LABEL: test_128_i64_x_2_18446744065119617024_mask_ashr_32:
1131; CHECK:       // %bb.0:
1132; CHECK-NEXT:    mov x8, #-8589934592
1133; CHECK-NEXT:    dup v1.2d, x8
1134; CHECK-NEXT:    and v0.16b, v0.16b, v1.16b
1135; CHECK-NEXT:    sshr v0.2d, v0.2d, #32
1136; CHECK-NEXT:    ret
1137  %t0 = and <2 x i64> %a0, <i64 18446744065119617024, i64 18446744065119617024>
1138  %t1 = ashr <2 x i64> %t0, <i64 32, i64 32>
1139  ret <2 x i64> %t1
1140}
1141define <2 x i64> @test_128_i64_x_2_18446744065119617024_mask_ashr_33(<2 x i64> %a0) {
1142; CHECK-LABEL: test_128_i64_x_2_18446744065119617024_mask_ashr_33:
1143; CHECK:       // %bb.0:
1144; CHECK-NEXT:    sshr v0.2d, v0.2d, #33
1145; CHECK-NEXT:    ret
1146  %t0 = and <2 x i64> %a0, <i64 18446744065119617024, i64 18446744065119617024>
1147  %t1 = ashr <2 x i64> %t0, <i64 33, i64 33>
1148  ret <2 x i64> %t1
1149}
1150define <2 x i64> @test_128_i64_x_2_18446744065119617024_mask_ashr_34(<2 x i64> %a0) {
1151; CHECK-LABEL: test_128_i64_x_2_18446744065119617024_mask_ashr_34:
1152; CHECK:       // %bb.0:
1153; CHECK-NEXT:    sshr v0.2d, v0.2d, #34
1154; CHECK-NEXT:    ret
1155  %t0 = and <2 x i64> %a0, <i64 18446744065119617024, i64 18446744065119617024>
1156  %t1 = ashr <2 x i64> %t0, <i64 34, i64 34>
1157  ret <2 x i64> %t1
1158}
1159
1160; shl
1161
1162define <2 x i64> @test_128_i64_x_2_2147483647_mask_shl_1(<2 x i64> %a0) {
1163; CHECK-LABEL: test_128_i64_x_2_2147483647_mask_shl_1:
1164; CHECK:       // %bb.0:
1165; CHECK-NEXT:    mov w8, #2147483647
1166; CHECK-NEXT:    dup v1.2d, x8
1167; CHECK-NEXT:    and v0.16b, v0.16b, v1.16b
1168; CHECK-NEXT:    add v0.2d, v0.2d, v0.2d
1169; CHECK-NEXT:    ret
1170  %t0 = and <2 x i64> %a0, <i64 2147483647, i64 2147483647>
1171  %t1 = shl <2 x i64> %t0, <i64 1, i64 1>
1172  ret <2 x i64> %t1
1173}
1174define <2 x i64> @test_128_i64_x_2_2147483647_mask_shl_32(<2 x i64> %a0) {
1175; CHECK-LABEL: test_128_i64_x_2_2147483647_mask_shl_32:
1176; CHECK:       // %bb.0:
1177; CHECK-NEXT:    mov w8, #2147483647
1178; CHECK-NEXT:    dup v1.2d, x8
1179; CHECK-NEXT:    and v0.16b, v0.16b, v1.16b
1180; CHECK-NEXT:    shl v0.2d, v0.2d, #32
1181; CHECK-NEXT:    ret
1182  %t0 = and <2 x i64> %a0, <i64 2147483647, i64 2147483647>
1183  %t1 = shl <2 x i64> %t0, <i64 32, i64 32>
1184  ret <2 x i64> %t1
1185}
1186define <2 x i64> @test_128_i64_x_2_2147483647_mask_shl_33(<2 x i64> %a0) {
1187; CHECK-LABEL: test_128_i64_x_2_2147483647_mask_shl_33:
1188; CHECK:       // %bb.0:
1189; CHECK-NEXT:    shl v0.2d, v0.2d, #33
1190; CHECK-NEXT:    ret
1191  %t0 = and <2 x i64> %a0, <i64 2147483647, i64 2147483647>
1192  %t1 = shl <2 x i64> %t0, <i64 33, i64 33>
1193  ret <2 x i64> %t1
1194}
1195define <2 x i64> @test_128_i64_x_2_2147483647_mask_shl_34(<2 x i64> %a0) {
1196; CHECK-LABEL: test_128_i64_x_2_2147483647_mask_shl_34:
1197; CHECK:       // %bb.0:
1198; CHECK-NEXT:    shl v0.2d, v0.2d, #34
1199; CHECK-NEXT:    ret
1200  %t0 = and <2 x i64> %a0, <i64 2147483647, i64 2147483647>
1201  %t1 = shl <2 x i64> %t0, <i64 34, i64 34>
1202  ret <2 x i64> %t1
1203}
1204
1205define <2 x i64> @test_128_i64_x_2_140737488289792_mask_shl_15(<2 x i64> %a0) {
1206; CHECK-LABEL: test_128_i64_x_2_140737488289792_mask_shl_15:
1207; CHECK:       // %bb.0:
1208; CHECK-NEXT:    mov x8, #140737488289792
1209; CHECK-NEXT:    dup v1.2d, x8
1210; CHECK-NEXT:    and v0.16b, v0.16b, v1.16b
1211; CHECK-NEXT:    shl v0.2d, v0.2d, #15
1212; CHECK-NEXT:    ret
1213  %t0 = and <2 x i64> %a0, <i64 140737488289792, i64 140737488289792>
1214  %t1 = shl <2 x i64> %t0, <i64 15, i64 15>
1215  ret <2 x i64> %t1
1216}
1217define <2 x i64> @test_128_i64_x_2_140737488289792_mask_shl_16(<2 x i64> %a0) {
1218; CHECK-LABEL: test_128_i64_x_2_140737488289792_mask_shl_16:
1219; CHECK:       // %bb.0:
1220; CHECK-NEXT:    mov x8, #140737488289792
1221; CHECK-NEXT:    dup v1.2d, x8
1222; CHECK-NEXT:    and v0.16b, v0.16b, v1.16b
1223; CHECK-NEXT:    shl v0.2d, v0.2d, #16
1224; CHECK-NEXT:    ret
1225  %t0 = and <2 x i64> %a0, <i64 140737488289792, i64 140737488289792>
1226  %t1 = shl <2 x i64> %t0, <i64 16, i64 16>
1227  ret <2 x i64> %t1
1228}
1229define <2 x i64> @test_128_i64_x_2_140737488289792_mask_shl_17(<2 x i64> %a0) {
1230; CHECK-LABEL: test_128_i64_x_2_140737488289792_mask_shl_17:
1231; CHECK:       // %bb.0:
1232; CHECK-NEXT:    mov x8, #140737488289792
1233; CHECK-NEXT:    dup v1.2d, x8
1234; CHECK-NEXT:    and v0.16b, v0.16b, v1.16b
1235; CHECK-NEXT:    shl v0.2d, v0.2d, #17
1236; CHECK-NEXT:    ret
1237  %t0 = and <2 x i64> %a0, <i64 140737488289792, i64 140737488289792>
1238  %t1 = shl <2 x i64> %t0, <i64 17, i64 17>
1239  ret <2 x i64> %t1
1240}
1241define <2 x i64> @test_128_i64_x_2_140737488289792_mask_shl_18(<2 x i64> %a0) {
1242; CHECK-LABEL: test_128_i64_x_2_140737488289792_mask_shl_18:
1243; CHECK:       // %bb.0:
1244; CHECK-NEXT:    mov x8, #140737488289792
1245; CHECK-NEXT:    dup v1.2d, x8
1246; CHECK-NEXT:    and v0.16b, v0.16b, v1.16b
1247; CHECK-NEXT:    shl v0.2d, v0.2d, #18
1248; CHECK-NEXT:    ret
1249  %t0 = and <2 x i64> %a0, <i64 140737488289792, i64 140737488289792>
1250  %t1 = shl <2 x i64> %t0, <i64 18, i64 18>
1251  ret <2 x i64> %t1
1252}
1253
1254define <2 x i64> @test_128_i64_x_2_18446744065119617024_mask_shl_1(<2 x i64> %a0) {
1255; CHECK-LABEL: test_128_i64_x_2_18446744065119617024_mask_shl_1:
1256; CHECK:       // %bb.0:
1257; CHECK-NEXT:    mov x8, #-8589934592
1258; CHECK-NEXT:    dup v1.2d, x8
1259; CHECK-NEXT:    and v0.16b, v0.16b, v1.16b
1260; CHECK-NEXT:    add v0.2d, v0.2d, v0.2d
1261; CHECK-NEXT:    ret
1262  %t0 = and <2 x i64> %a0, <i64 18446744065119617024, i64 18446744065119617024>
1263  %t1 = shl <2 x i64> %t0, <i64 1, i64 1>
1264  ret <2 x i64> %t1
1265}
1266