xref: /llvm-project/llvm/test/CodeGen/AArch64/vector-insert-shuffle-cycle.ll (revision 742fb8b5c7036409f08ab0706f00057ac29ac773)
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc %s -o - | FileCheck %s
3
4target triple = "arm64-apple-ios13.4.0"
5
6; Make we do not get stuck in a cycle in DAGCombiner.
7
8define void @test(i1 %c, ptr %ptr) {
9; CHECK-LABEL: test:
10; CHECK:       ; %bb.0: ; %entry
11; CHECK-NEXT:    movi d0, #0000000000000000
12; CHECK-NEXT:    tbz w0, #0, LBB0_2
13; CHECK-NEXT:  ; %bb.1: ; %bb1
14; CHECK-NEXT:    ldr d0, [x1]
15; CHECK-NEXT:  LBB0_2: ; %bb2
16; CHECK-NEXT:    str d0, [x8]
17; CHECK-NEXT:    ret
18entry:
19  br i1 %c, label %bb1, label %bb2
20
21bb1:
22  %lv1 = load <1 x double>, ptr %ptr, align 16
23  br label %bb2
24
25bb2:
26  %p = phi <1 x double> [ %lv1, %bb1 ], [ zeroinitializer, %entry ]
27  %vecext19 = extractelement <1 x double> %p, i32 0
28  %arrayidx21 = getelementptr inbounds [4 x <4 x double>], ptr undef, i64 0, i64 3
29  %lv2 = load <4 x double>, ptr %arrayidx21, align 16
30  %vecins22 = insertelement <4 x double> %lv2, double %vecext19, i32 2
31  store <4 x double> %vecins22, ptr %arrayidx21, align 16
32  ret void
33}
34