xref: /llvm-project/llvm/test/CodeGen/AArch64/vecreduce-fadd-legalization.ll (revision 7a605ab7bfbc681c34335684f45b7da32d495db1) 
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc < %s -mtriple=aarch64-none-linux-gnu -mattr=+neon | FileCheck %s --check-prefix=CHECK
3
4declare half @llvm.vector.reduce.fadd.f16.v1f16(half, <1 x half>)
5declare float @llvm.vector.reduce.fadd.f32.v1f32(float, <1 x float>)
6declare double @llvm.vector.reduce.fadd.f64.v1f64(double, <1 x double>)
7declare fp128 @llvm.vector.reduce.fadd.f128.v1f128(fp128, <1 x fp128>)
8
9declare float @llvm.vector.reduce.fadd.f32.v3f32(float, <3 x float>)
10declare float @llvm.vector.reduce.fadd.f32.v5f32(float, <5 x float>)
11declare fp128 @llvm.vector.reduce.fadd.f128.v2f128(fp128, <2 x fp128>)
12declare float @llvm.vector.reduce.fadd.f32.v16f32(float, <16 x float>)
13
14define half @test_v1f16(<1 x half> %a) nounwind {
15; CHECK-LABEL: test_v1f16:
16; CHECK:       // %bb.0:
17; CHECK-NEXT:    ret
18  %b = call reassoc half @llvm.vector.reduce.fadd.f16.v1f16(half -0.0, <1 x half> %a)
19  ret half %b
20}
21
22define float @test_v1f32(<1 x float> %a) nounwind {
23; CHECK-LABEL: test_v1f32:
24; CHECK:       // %bb.0:
25; CHECK-NEXT:    // kill: def $d0 killed $d0 def $q0
26; CHECK-NEXT:    // kill: def $s0 killed $s0 killed $q0
27; CHECK-NEXT:    ret
28  %b = call reassoc float @llvm.vector.reduce.fadd.f32.v1f32(float -0.0, <1 x float> %a)
29  ret float %b
30}
31
32define double @test_v1f64(<1 x double> %a) nounwind {
33; CHECK-LABEL: test_v1f64:
34; CHECK:       // %bb.0:
35; CHECK-NEXT:    ret
36  %b = call reassoc double @llvm.vector.reduce.fadd.f64.v1f64(double -0.0, <1 x double> %a)
37  ret double %b
38}
39
40define fp128 @test_v1f128(<1 x fp128> %a) nounwind {
41; CHECK-LABEL: test_v1f128:
42; CHECK:       // %bb.0:
43; CHECK-NEXT:    ret
44  %b = call reassoc fp128 @llvm.vector.reduce.fadd.f128.v1f128(fp128 0xL00000000000000008000000000000000, <1 x fp128> %a)
45  ret fp128 %b
46}
47
48define float @test_v3f32(<3 x float> %a) nounwind {
49; CHECK-LABEL: test_v3f32:
50; CHECK:       // %bb.0:
51; CHECK-NEXT:    movi v1.2s, #128, lsl #24
52; CHECK-NEXT:    mov v0.s[3], v1.s[0]
53; CHECK-NEXT:    faddp v0.4s, v0.4s, v0.4s
54; CHECK-NEXT:    faddp s0, v0.2s
55; CHECK-NEXT:    ret
56  %b = call reassoc float @llvm.vector.reduce.fadd.f32.v3f32(float -0.0, <3 x float> %a)
57  ret float %b
58}
59
60define float @test_v5f32(<5 x float> %a) nounwind {
61; CHECK-LABEL: test_v5f32:
62; CHECK:       // %bb.0:
63; CHECK-NEXT:    // kill: def $s0 killed $s0 def $q0
64; CHECK-NEXT:    // kill: def $s1 killed $s1 def $q1
65; CHECK-NEXT:    // kill: def $s2 killed $s2 def $q2
66; CHECK-NEXT:    movi v5.4s, #128, lsl #24
67; CHECK-NEXT:    // kill: def $s4 killed $s4 def $q4
68; CHECK-NEXT:    // kill: def $s3 killed $s3 def $q3
69; CHECK-NEXT:    mov v0.s[1], v1.s[0]
70; CHECK-NEXT:    mov v5.s[0], v4.s[0]
71; CHECK-NEXT:    mov v0.s[2], v2.s[0]
72; CHECK-NEXT:    mov v0.s[3], v3.s[0]
73; CHECK-NEXT:    fadd v0.4s, v0.4s, v5.4s
74; CHECK-NEXT:    faddp v0.4s, v0.4s, v0.4s
75; CHECK-NEXT:    faddp s0, v0.2s
76; CHECK-NEXT:    ret
77  %b = call reassoc float @llvm.vector.reduce.fadd.f32.v5f32(float -0.0, <5 x float> %a)
78  ret float %b
79}
80
81define fp128 @test_v2f128(<2 x fp128> %a) nounwind {
82; CHECK-LABEL: test_v2f128:
83; CHECK:       // %bb.0:
84; CHECK-NEXT:    b __addtf3
85  %b = call reassoc fp128 @llvm.vector.reduce.fadd.f128.v2f128(fp128 0xL00000000000000008000000000000000, <2 x fp128> %a)
86  ret fp128 %b
87}
88
89define float @test_v16f32(<16 x float> %a) nounwind {
90; CHECK-LABEL: test_v16f32:
91; CHECK:       // %bb.0:
92; CHECK-NEXT:    fadd v1.4s, v1.4s, v3.4s
93; CHECK-NEXT:    fadd v0.4s, v0.4s, v2.4s
94; CHECK-NEXT:    fadd v0.4s, v0.4s, v1.4s
95; CHECK-NEXT:    faddp v0.4s, v0.4s, v0.4s
96; CHECK-NEXT:    faddp s0, v0.2s
97; CHECK-NEXT:    ret
98  %b = call reassoc float @llvm.vector.reduce.fadd.f32.v16f32(float -0.0, <16 x float> %a)
99  ret float %b
100}
101