xref: /llvm-project/llvm/test/CodeGen/AArch64/vecreduce-and-legalization.ll (revision db158c7c830807caeeb0691739c41f1d522029e9) 
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc < %s -mtriple=aarch64-none-linux-gnu -mattr=+neon | FileCheck %s --check-prefix=CHECK
3
4declare i1 @llvm.vector.reduce.and.v1i1(<1 x i1> %a)
5declare i8 @llvm.vector.reduce.and.v1i8(<1 x i8> %a)
6declare i16 @llvm.vector.reduce.and.v1i16(<1 x i16> %a)
7declare i24 @llvm.vector.reduce.and.v1i24(<1 x i24> %a)
8declare i32 @llvm.vector.reduce.and.v1i32(<1 x i32> %a)
9declare i64 @llvm.vector.reduce.and.v1i64(<1 x i64> %a)
10declare i128 @llvm.vector.reduce.and.v1i128(<1 x i128> %a)
11
12declare i8 @llvm.vector.reduce.and.v3i8(<3 x i8> %a)
13declare i8 @llvm.vector.reduce.and.v9i8(<9 x i8> %a)
14declare i32 @llvm.vector.reduce.and.v3i32(<3 x i32> %a)
15declare i1 @llvm.vector.reduce.and.v4i1(<4 x i1> %a)
16declare i24 @llvm.vector.reduce.and.v4i24(<4 x i24> %a)
17declare i128 @llvm.vector.reduce.and.v2i128(<2 x i128> %a)
18declare i32 @llvm.vector.reduce.and.v16i32(<16 x i32> %a)
19
20define i1 @test_v1i1(<1 x i1> %a) nounwind {
21; CHECK-LABEL: test_v1i1:
22; CHECK:       // %bb.0:
23; CHECK-NEXT:    and w0, w0, #0x1
24; CHECK-NEXT:    ret
25  %b = call i1 @llvm.vector.reduce.and.v1i1(<1 x i1> %a)
26  ret i1 %b
27}
28
29define i8 @test_v1i8(<1 x i8> %a) nounwind {
30; CHECK-LABEL: test_v1i8:
31; CHECK:       // %bb.0:
32; CHECK-NEXT:    // kill: def $d0 killed $d0 def $q0
33; CHECK-NEXT:    umov w0, v0.b[0]
34; CHECK-NEXT:    ret
35  %b = call i8 @llvm.vector.reduce.and.v1i8(<1 x i8> %a)
36  ret i8 %b
37}
38
39define i16 @test_v1i16(<1 x i16> %a) nounwind {
40; CHECK-LABEL: test_v1i16:
41; CHECK:       // %bb.0:
42; CHECK-NEXT:    // kill: def $d0 killed $d0 def $q0
43; CHECK-NEXT:    umov w0, v0.h[0]
44; CHECK-NEXT:    ret
45  %b = call i16 @llvm.vector.reduce.and.v1i16(<1 x i16> %a)
46  ret i16 %b
47}
48
49define i24 @test_v1i24(<1 x i24> %a) nounwind {
50; CHECK-LABEL: test_v1i24:
51; CHECK:       // %bb.0:
52; CHECK-NEXT:    ret
53  %b = call i24 @llvm.vector.reduce.and.v1i24(<1 x i24> %a)
54  ret i24 %b
55}
56
57define i32 @test_v1i32(<1 x i32> %a) nounwind {
58; CHECK-LABEL: test_v1i32:
59; CHECK:       // %bb.0:
60; CHECK-NEXT:    // kill: def $d0 killed $d0 def $q0
61; CHECK-NEXT:    fmov w0, s0
62; CHECK-NEXT:    ret
63  %b = call i32 @llvm.vector.reduce.and.v1i32(<1 x i32> %a)
64  ret i32 %b
65}
66
67define i64 @test_v1i64(<1 x i64> %a) nounwind {
68; CHECK-LABEL: test_v1i64:
69; CHECK:       // %bb.0:
70; CHECK-NEXT:    // kill: def $d0 killed $d0 def $q0
71; CHECK-NEXT:    fmov x0, d0
72; CHECK-NEXT:    ret
73  %b = call i64 @llvm.vector.reduce.and.v1i64(<1 x i64> %a)
74  ret i64 %b
75}
76
77define i128 @test_v1i128(<1 x i128> %a) nounwind {
78; CHECK-LABEL: test_v1i128:
79; CHECK:       // %bb.0:
80; CHECK-NEXT:    ret
81  %b = call i128 @llvm.vector.reduce.and.v1i128(<1 x i128> %a)
82  ret i128 %b
83}
84
85define i8 @test_v3i8(<3 x i8> %a) nounwind {
86; CHECK-LABEL: test_v3i8:
87; CHECK:       // %bb.0:
88; CHECK-NEXT:    movi d0, #0xff00ff00ff00ff
89; CHECK-NEXT:    mov v0.h[0], w0
90; CHECK-NEXT:    mov v0.h[1], w1
91; CHECK-NEXT:    mov v0.h[2], w2
92; CHECK-NEXT:    fmov x8, d0
93; CHECK-NEXT:    and x8, x8, x8, lsr #32
94; CHECK-NEXT:    lsr x9, x8, #16
95; CHECK-NEXT:    and w0, w8, w9
96; CHECK-NEXT:    ret
97  %b = call i8 @llvm.vector.reduce.and.v3i8(<3 x i8> %a)
98  ret i8 %b
99}
100
101define i8 @test_v9i8(<9 x i8> %a) nounwind {
102; CHECK-LABEL: test_v9i8:
103; CHECK:       // %bb.0:
104; CHECK-NEXT:    mov v1.16b, v0.16b
105; CHECK-NEXT:    mov w8, #-1 // =0xffffffff
106; CHECK-NEXT:    mov v1.b[9], w8
107; CHECK-NEXT:    mov v1.b[10], w8
108; CHECK-NEXT:    mov v1.b[11], w8
109; CHECK-NEXT:    mov v1.b[12], w8
110; CHECK-NEXT:    mov v1.b[13], w8
111; CHECK-NEXT:    mov v1.b[14], w8
112; CHECK-NEXT:    mov v1.b[15], w8
113; CHECK-NEXT:    ext v1.16b, v1.16b, v1.16b, #8
114; CHECK-NEXT:    and v0.8b, v0.8b, v1.8b
115; CHECK-NEXT:    fmov x8, d0
116; CHECK-NEXT:    and x8, x8, x8, lsr #32
117; CHECK-NEXT:    and x8, x8, x8, lsr #16
118; CHECK-NEXT:    lsr x9, x8, #8
119; CHECK-NEXT:    and w0, w8, w9
120; CHECK-NEXT:    ret
121  %b = call i8 @llvm.vector.reduce.and.v9i8(<9 x i8> %a)
122  ret i8 %b
123}
124
125define i32 @test_v3i32(<3 x i32> %a) nounwind {
126; CHECK-LABEL: test_v3i32:
127; CHECK:       // %bb.0:
128; CHECK-NEXT:    ext v1.16b, v0.16b, v0.16b, #8
129; CHECK-NEXT:    fmov x8, d0
130; CHECK-NEXT:    lsr x8, x8, #32
131; CHECK-NEXT:    and v1.8b, v0.8b, v1.8b
132; CHECK-NEXT:    fmov x9, d1
133; CHECK-NEXT:    and w0, w9, w8
134; CHECK-NEXT:    ret
135  %b = call i32 @llvm.vector.reduce.and.v3i32(<3 x i32> %a)
136  ret i32 %b
137}
138
139define i1 @test_v4i1(<4 x i1> %a) nounwind {
140; CHECK-LABEL: test_v4i1:
141; CHECK:       // %bb.0:
142; CHECK-NEXT:    shl v0.4h, v0.4h, #15
143; CHECK-NEXT:    cmlt v0.4h, v0.4h, #0
144; CHECK-NEXT:    uminv h0, v0.4h
145; CHECK-NEXT:    fmov w8, s0
146; CHECK-NEXT:    and w0, w8, #0x1
147; CHECK-NEXT:    ret
148  %b = call i1 @llvm.vector.reduce.and.v4i1(<4 x i1> %a)
149  ret i1 %b
150}
151
152define i24 @test_v4i24(<4 x i24> %a) nounwind {
153; CHECK-LABEL: test_v4i24:
154; CHECK:       // %bb.0:
155; CHECK-NEXT:    ext v1.16b, v0.16b, v0.16b, #8
156; CHECK-NEXT:    and v0.8b, v0.8b, v1.8b
157; CHECK-NEXT:    fmov x8, d0
158; CHECK-NEXT:    lsr x9, x8, #32
159; CHECK-NEXT:    and w0, w8, w9
160; CHECK-NEXT:    ret
161  %b = call i24 @llvm.vector.reduce.and.v4i24(<4 x i24> %a)
162  ret i24 %b
163}
164
165define i128 @test_v2i128(<2 x i128> %a) nounwind {
166; CHECK-LABEL: test_v2i128:
167; CHECK:       // %bb.0:
168; CHECK-NEXT:    and x1, x1, x3
169; CHECK-NEXT:    and x0, x0, x2
170; CHECK-NEXT:    ret
171  %b = call i128 @llvm.vector.reduce.and.v2i128(<2 x i128> %a)
172  ret i128 %b
173}
174
175define i32 @test_v16i32(<16 x i32> %a) nounwind {
176; CHECK-LABEL: test_v16i32:
177; CHECK:       // %bb.0:
178; CHECK-NEXT:    and v1.16b, v1.16b, v3.16b
179; CHECK-NEXT:    and v0.16b, v0.16b, v2.16b
180; CHECK-NEXT:    and v0.16b, v0.16b, v1.16b
181; CHECK-NEXT:    ext v1.16b, v0.16b, v0.16b, #8
182; CHECK-NEXT:    and v0.8b, v0.8b, v1.8b
183; CHECK-NEXT:    fmov x8, d0
184; CHECK-NEXT:    lsr x9, x8, #32
185; CHECK-NEXT:    and w0, w8, w9
186; CHECK-NEXT:    ret
187  %b = call i32 @llvm.vector.reduce.and.v16i32(<16 x i32> %a)
188  ret i32 %b
189}
190