xref: /llvm-project/llvm/test/CodeGen/AArch64/vec_umulo.ll (revision db158c7c830807caeeb0691739c41f1d522029e9) 
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc < %s -mtriple=aarch64-none-linux-gnu -mattr=+neon | FileCheck %s --check-prefix=CHECK
3
4declare {<1 x i32>, <1 x i1>} @llvm.umul.with.overflow.v1i32(<1 x i32>, <1 x i32>)
5declare {<2 x i32>, <2 x i1>} @llvm.umul.with.overflow.v2i32(<2 x i32>, <2 x i32>)
6declare {<3 x i32>, <3 x i1>} @llvm.umul.with.overflow.v3i32(<3 x i32>, <3 x i32>)
7declare {<4 x i32>, <4 x i1>} @llvm.umul.with.overflow.v4i32(<4 x i32>, <4 x i32>)
8declare {<6 x i32>, <6 x i1>} @llvm.umul.with.overflow.v6i32(<6 x i32>, <6 x i32>)
9declare {<8 x i32>, <8 x i1>} @llvm.umul.with.overflow.v8i32(<8 x i32>, <8 x i32>)
10
11declare {<16 x i8>, <16 x i1>} @llvm.umul.with.overflow.v16i8(<16 x i8>, <16 x i8>)
12declare {<8 x i16>, <8 x i1>} @llvm.umul.with.overflow.v8i16(<8 x i16>, <8 x i16>)
13declare {<2 x i64>, <2 x i1>} @llvm.umul.with.overflow.v2i64(<2 x i64>, <2 x i64>)
14
15declare {<4 x i24>, <4 x i1>} @llvm.umul.with.overflow.v4i24(<4 x i24>, <4 x i24>)
16declare {<4 x i1>, <4 x i1>} @llvm.umul.with.overflow.v4i1(<4 x i1>, <4 x i1>)
17declare {<2 x i128>, <2 x i1>} @llvm.umul.with.overflow.v2i128(<2 x i128>, <2 x i128>)
18
19define <1 x i32> @umulo_v1i32(<1 x i32> %a0, <1 x i32> %a1, ptr %p2) nounwind {
20; CHECK-LABEL: umulo_v1i32:
21; CHECK:       // %bb.0:
22; CHECK-NEXT:    umull v1.2d, v0.2s, v1.2s
23; CHECK-NEXT:    shrn v0.2s, v1.2d, #32
24; CHECK-NEXT:    xtn v1.2s, v1.2d
25; CHECK-NEXT:    cmtst v0.2s, v0.2s, v0.2s
26; CHECK-NEXT:    str s1, [x0]
27; CHECK-NEXT:    ret
28  %t = call {<1 x i32>, <1 x i1>} @llvm.umul.with.overflow.v1i32(<1 x i32> %a0, <1 x i32> %a1)
29  %val = extractvalue {<1 x i32>, <1 x i1>} %t, 0
30  %obit = extractvalue {<1 x i32>, <1 x i1>} %t, 1
31  %res = sext <1 x i1> %obit to <1 x i32>
32  store <1 x i32> %val, ptr %p2
33  ret <1 x i32> %res
34}
35
36define <2 x i32> @umulo_v2i32(<2 x i32> %a0, <2 x i32> %a1, ptr %p2) nounwind {
37; CHECK-LABEL: umulo_v2i32:
38; CHECK:       // %bb.0:
39; CHECK-NEXT:    umull v1.2d, v0.2s, v1.2s
40; CHECK-NEXT:    shrn v0.2s, v1.2d, #32
41; CHECK-NEXT:    xtn v1.2s, v1.2d
42; CHECK-NEXT:    cmtst v0.2s, v0.2s, v0.2s
43; CHECK-NEXT:    str d1, [x0]
44; CHECK-NEXT:    ret
45  %t = call {<2 x i32>, <2 x i1>} @llvm.umul.with.overflow.v2i32(<2 x i32> %a0, <2 x i32> %a1)
46  %val = extractvalue {<2 x i32>, <2 x i1>} %t, 0
47  %obit = extractvalue {<2 x i32>, <2 x i1>} %t, 1
48  %res = sext <2 x i1> %obit to <2 x i32>
49  store <2 x i32> %val, ptr %p2
50  ret <2 x i32> %res
51}
52
53define <3 x i32> @umulo_v3i32(<3 x i32> %a0, <3 x i32> %a1, ptr %p2) nounwind {
54; CHECK-LABEL: umulo_v3i32:
55; CHECK:       // %bb.0:
56; CHECK-NEXT:    umull2 v2.2d, v0.4s, v1.4s
57; CHECK-NEXT:    umull v3.2d, v0.2s, v1.2s
58; CHECK-NEXT:    add x8, x0, #8
59; CHECK-NEXT:    mul v1.4s, v0.4s, v1.4s
60; CHECK-NEXT:    uzp2 v2.4s, v3.4s, v2.4s
61; CHECK-NEXT:    st1 { v1.s }[2], [x8]
62; CHECK-NEXT:    str d1, [x0]
63; CHECK-NEXT:    cmtst v2.4s, v2.4s, v2.4s
64; CHECK-NEXT:    mov v0.16b, v2.16b
65; CHECK-NEXT:    ret
66  %t = call {<3 x i32>, <3 x i1>} @llvm.umul.with.overflow.v3i32(<3 x i32> %a0, <3 x i32> %a1)
67  %val = extractvalue {<3 x i32>, <3 x i1>} %t, 0
68  %obit = extractvalue {<3 x i32>, <3 x i1>} %t, 1
69  %res = sext <3 x i1> %obit to <3 x i32>
70  store <3 x i32> %val, ptr %p2
71  ret <3 x i32> %res
72}
73
74define <4 x i32> @umulo_v4i32(<4 x i32> %a0, <4 x i32> %a1, ptr %p2) nounwind {
75; CHECK-LABEL: umulo_v4i32:
76; CHECK:       // %bb.0:
77; CHECK-NEXT:    umull2 v2.2d, v0.4s, v1.4s
78; CHECK-NEXT:    umull v3.2d, v0.2s, v1.2s
79; CHECK-NEXT:    mul v1.4s, v0.4s, v1.4s
80; CHECK-NEXT:    uzp2 v2.4s, v3.4s, v2.4s
81; CHECK-NEXT:    str q1, [x0]
82; CHECK-NEXT:    cmtst v2.4s, v2.4s, v2.4s
83; CHECK-NEXT:    mov v0.16b, v2.16b
84; CHECK-NEXT:    ret
85  %t = call {<4 x i32>, <4 x i1>} @llvm.umul.with.overflow.v4i32(<4 x i32> %a0, <4 x i32> %a1)
86  %val = extractvalue {<4 x i32>, <4 x i1>} %t, 0
87  %obit = extractvalue {<4 x i32>, <4 x i1>} %t, 1
88  %res = sext <4 x i1> %obit to <4 x i32>
89  store <4 x i32> %val, ptr %p2
90  ret <4 x i32> %res
91}
92
93define <6 x i32> @umulo_v6i32(<6 x i32> %a0, <6 x i32> %a1, ptr %p2) nounwind {
94; CHECK-LABEL: umulo_v6i32:
95; CHECK:       // %bb.0:
96; CHECK-NEXT:    fmov s0, w0
97; CHECK-NEXT:    fmov s1, w6
98; CHECK-NEXT:    mov x8, sp
99; CHECK-NEXT:    fmov s3, w4
100; CHECK-NEXT:    ldr s2, [sp, #16]
101; CHECK-NEXT:    add x9, sp, #24
102; CHECK-NEXT:    mov v0.s[1], w1
103; CHECK-NEXT:    mov v1.s[1], w7
104; CHECK-NEXT:    ld1 { v2.s }[1], [x9]
105; CHECK-NEXT:    mov v3.s[1], w5
106; CHECK-NEXT:    mov v0.s[2], w2
107; CHECK-NEXT:    ld1 { v1.s }[2], [x8]
108; CHECK-NEXT:    add x8, sp, #8
109; CHECK-NEXT:    umull2 v6.2d, v3.4s, v2.4s
110; CHECK-NEXT:    umull v7.2d, v3.2s, v2.2s
111; CHECK-NEXT:    mul v2.4s, v3.4s, v2.4s
112; CHECK-NEXT:    ld1 { v1.s }[3], [x8]
113; CHECK-NEXT:    ldr x8, [sp, #32]
114; CHECK-NEXT:    mov v0.s[3], w3
115; CHECK-NEXT:    str d2, [x8, #16]
116; CHECK-NEXT:    umull2 v4.2d, v0.4s, v1.4s
117; CHECK-NEXT:    umull v5.2d, v0.2s, v1.2s
118; CHECK-NEXT:    mul v0.4s, v0.4s, v1.4s
119; CHECK-NEXT:    uzp2 v4.4s, v5.4s, v4.4s
120; CHECK-NEXT:    uzp2 v5.4s, v7.4s, v6.4s
121; CHECK-NEXT:    str q0, [x8]
122; CHECK-NEXT:    cmtst v4.4s, v4.4s, v4.4s
123; CHECK-NEXT:    cmtst v5.4s, v5.4s, v5.4s
124; CHECK-NEXT:    mov w1, v4.s[1]
125; CHECK-NEXT:    mov w2, v4.s[2]
126; CHECK-NEXT:    mov w5, v5.s[1]
127; CHECK-NEXT:    mov w3, v4.s[3]
128; CHECK-NEXT:    fmov w4, s5
129; CHECK-NEXT:    fmov w0, s4
130; CHECK-NEXT:    ret
131  %t = call {<6 x i32>, <6 x i1>} @llvm.umul.with.overflow.v6i32(<6 x i32> %a0, <6 x i32> %a1)
132  %val = extractvalue {<6 x i32>, <6 x i1>} %t, 0
133  %obit = extractvalue {<6 x i32>, <6 x i1>} %t, 1
134  %res = sext <6 x i1> %obit to <6 x i32>
135  store <6 x i32> %val, ptr %p2
136  ret <6 x i32> %res
137}
138
139define <8 x i32> @umulo_v8i32(<8 x i32> %a0, <8 x i32> %a1, ptr %p2) nounwind {
140; CHECK-LABEL: umulo_v8i32:
141; CHECK:       // %bb.0:
142; CHECK-NEXT:    umull2 v4.2d, v0.4s, v2.4s
143; CHECK-NEXT:    umull v5.2d, v0.2s, v2.2s
144; CHECK-NEXT:    umull2 v6.2d, v1.4s, v3.4s
145; CHECK-NEXT:    umull v7.2d, v1.2s, v3.2s
146; CHECK-NEXT:    mul v1.4s, v1.4s, v3.4s
147; CHECK-NEXT:    mul v2.4s, v0.4s, v2.4s
148; CHECK-NEXT:    uzp2 v4.4s, v5.4s, v4.4s
149; CHECK-NEXT:    uzp2 v5.4s, v7.4s, v6.4s
150; CHECK-NEXT:    stp q2, q1, [x0]
151; CHECK-NEXT:    cmtst v4.4s, v4.4s, v4.4s
152; CHECK-NEXT:    cmtst v5.4s, v5.4s, v5.4s
153; CHECK-NEXT:    mov v0.16b, v4.16b
154; CHECK-NEXT:    mov v1.16b, v5.16b
155; CHECK-NEXT:    ret
156  %t = call {<8 x i32>, <8 x i1>} @llvm.umul.with.overflow.v8i32(<8 x i32> %a0, <8 x i32> %a1)
157  %val = extractvalue {<8 x i32>, <8 x i1>} %t, 0
158  %obit = extractvalue {<8 x i32>, <8 x i1>} %t, 1
159  %res = sext <8 x i1> %obit to <8 x i32>
160  store <8 x i32> %val, ptr %p2
161  ret <8 x i32> %res
162}
163
164define <16 x i32> @umulo_v16i8(<16 x i8> %a0, <16 x i8> %a1, ptr %p2) nounwind {
165; CHECK-LABEL: umulo_v16i8:
166; CHECK:       // %bb.0:
167; CHECK-NEXT:    umull2 v2.8h, v0.16b, v1.16b
168; CHECK-NEXT:    umull v3.8h, v0.8b, v1.8b
169; CHECK-NEXT:    mul v6.16b, v0.16b, v1.16b
170; CHECK-NEXT:    uzp2 v2.16b, v3.16b, v2.16b
171; CHECK-NEXT:    str q6, [x0]
172; CHECK-NEXT:    cmtst v2.16b, v2.16b, v2.16b
173; CHECK-NEXT:    ext v3.16b, v2.16b, v2.16b, #8
174; CHECK-NEXT:    zip1 v4.8b, v2.8b, v0.8b
175; CHECK-NEXT:    zip2 v2.8b, v2.8b, v0.8b
176; CHECK-NEXT:    zip1 v5.8b, v3.8b, v0.8b
177; CHECK-NEXT:    zip2 v3.8b, v3.8b, v0.8b
178; CHECK-NEXT:    ushll v4.4s, v4.4h, #0
179; CHECK-NEXT:    ushll v2.4s, v2.4h, #0
180; CHECK-NEXT:    shl v4.4s, v4.4s, #31
181; CHECK-NEXT:    ushll v5.4s, v5.4h, #0
182; CHECK-NEXT:    ushll v3.4s, v3.4h, #0
183; CHECK-NEXT:    shl v2.4s, v2.4s, #31
184; CHECK-NEXT:    cmlt v0.4s, v4.4s, #0
185; CHECK-NEXT:    shl v5.4s, v5.4s, #31
186; CHECK-NEXT:    shl v3.4s, v3.4s, #31
187; CHECK-NEXT:    cmlt v1.4s, v2.4s, #0
188; CHECK-NEXT:    cmlt v2.4s, v5.4s, #0
189; CHECK-NEXT:    cmlt v3.4s, v3.4s, #0
190; CHECK-NEXT:    ret
191  %t = call {<16 x i8>, <16 x i1>} @llvm.umul.with.overflow.v16i8(<16 x i8> %a0, <16 x i8> %a1)
192  %val = extractvalue {<16 x i8>, <16 x i1>} %t, 0
193  %obit = extractvalue {<16 x i8>, <16 x i1>} %t, 1
194  %res = sext <16 x i1> %obit to <16 x i32>
195  store <16 x i8> %val, ptr %p2
196  ret <16 x i32> %res
197}
198
199define <8 x i32> @umulo_v8i16(<8 x i16> %a0, <8 x i16> %a1, ptr %p2) nounwind {
200; CHECK-LABEL: umulo_v8i16:
201; CHECK:       // %bb.0:
202; CHECK-NEXT:    umull2 v2.4s, v0.8h, v1.8h
203; CHECK-NEXT:    umull v3.4s, v0.4h, v1.4h
204; CHECK-NEXT:    mul v4.8h, v0.8h, v1.8h
205; CHECK-NEXT:    uzp2 v2.8h, v3.8h, v2.8h
206; CHECK-NEXT:    str q4, [x0]
207; CHECK-NEXT:    cmtst v2.8h, v2.8h, v2.8h
208; CHECK-NEXT:    xtn v2.8b, v2.8h
209; CHECK-NEXT:    zip1 v3.8b, v2.8b, v0.8b
210; CHECK-NEXT:    zip2 v2.8b, v2.8b, v0.8b
211; CHECK-NEXT:    ushll v3.4s, v3.4h, #0
212; CHECK-NEXT:    ushll v2.4s, v2.4h, #0
213; CHECK-NEXT:    shl v3.4s, v3.4s, #31
214; CHECK-NEXT:    shl v2.4s, v2.4s, #31
215; CHECK-NEXT:    cmlt v0.4s, v3.4s, #0
216; CHECK-NEXT:    cmlt v1.4s, v2.4s, #0
217; CHECK-NEXT:    ret
218  %t = call {<8 x i16>, <8 x i1>} @llvm.umul.with.overflow.v8i16(<8 x i16> %a0, <8 x i16> %a1)
219  %val = extractvalue {<8 x i16>, <8 x i1>} %t, 0
220  %obit = extractvalue {<8 x i16>, <8 x i1>} %t, 1
221  %res = sext <8 x i1> %obit to <8 x i32>
222  store <8 x i16> %val, ptr %p2
223  ret <8 x i32> %res
224}
225
226define <2 x i32> @umulo_v2i64(<2 x i64> %a0, <2 x i64> %a1, ptr %p2) nounwind {
227; CHECK-LABEL: umulo_v2i64:
228; CHECK:       // %bb.0:
229; CHECK-NEXT:    mov x8, v1.d[1]
230; CHECK-NEXT:    mov x9, v0.d[1]
231; CHECK-NEXT:    fmov x11, d1
232; CHECK-NEXT:    fmov x12, d0
233; CHECK-NEXT:    umulh x10, x9, x8
234; CHECK-NEXT:    umulh x13, x12, x11
235; CHECK-NEXT:    mul x11, x12, x11
236; CHECK-NEXT:    cmp xzr, x10
237; CHECK-NEXT:    csetm x10, ne
238; CHECK-NEXT:    mul x8, x9, x8
239; CHECK-NEXT:    cmp xzr, x13
240; CHECK-NEXT:    csetm x13, ne
241; CHECK-NEXT:    fmov d0, x13
242; CHECK-NEXT:    fmov d1, x11
243; CHECK-NEXT:    mov v0.d[1], x10
244; CHECK-NEXT:    mov v1.d[1], x8
245; CHECK-NEXT:    xtn v0.2s, v0.2d
246; CHECK-NEXT:    str q1, [x0]
247; CHECK-NEXT:    ret
248  %t = call {<2 x i64>, <2 x i1>} @llvm.umul.with.overflow.v2i64(<2 x i64> %a0, <2 x i64> %a1)
249  %val = extractvalue {<2 x i64>, <2 x i1>} %t, 0
250  %obit = extractvalue {<2 x i64>, <2 x i1>} %t, 1
251  %res = sext <2 x i1> %obit to <2 x i32>
252  store <2 x i64> %val, ptr %p2
253  ret <2 x i32> %res
254}
255
256define <4 x i32> @umulo_v4i24(<4 x i24> %a0, <4 x i24> %a1, ptr %p2) nounwind {
257; CHECK-LABEL: umulo_v4i24:
258; CHECK:       // %bb.0:
259; CHECK-NEXT:    bic v1.4s, #255, lsl #24
260; CHECK-NEXT:    bic v0.4s, #255, lsl #24
261; CHECK-NEXT:    umull2 v2.2d, v0.4s, v1.4s
262; CHECK-NEXT:    umull v3.2d, v0.2s, v1.2s
263; CHECK-NEXT:    mul v0.4s, v0.4s, v1.4s
264; CHECK-NEXT:    uzp2 v1.4s, v3.4s, v2.4s
265; CHECK-NEXT:    ushr v2.4s, v0.4s, #24
266; CHECK-NEXT:    mov w8, v0.s[3]
267; CHECK-NEXT:    mov w9, v0.s[2]
268; CHECK-NEXT:    mov w10, v0.s[1]
269; CHECK-NEXT:    fmov w11, s0
270; CHECK-NEXT:    cmtst v2.4s, v2.4s, v2.4s
271; CHECK-NEXT:    cmeq v1.4s, v1.4s, #0
272; CHECK-NEXT:    sturh w8, [x0, #9]
273; CHECK-NEXT:    lsr w8, w8, #16
274; CHECK-NEXT:    strh w9, [x0, #6]
275; CHECK-NEXT:    lsr w9, w9, #16
276; CHECK-NEXT:    strb w8, [x0, #11]
277; CHECK-NEXT:    lsr w8, w10, #16
278; CHECK-NEXT:    orn v0.16b, v2.16b, v1.16b
279; CHECK-NEXT:    strb w9, [x0, #8]
280; CHECK-NEXT:    lsr w9, w11, #16
281; CHECK-NEXT:    sturh w10, [x0, #3]
282; CHECK-NEXT:    strh w11, [x0]
283; CHECK-NEXT:    strb w8, [x0, #5]
284; CHECK-NEXT:    strb w9, [x0, #2]
285; CHECK-NEXT:    ret
286  %t = call {<4 x i24>, <4 x i1>} @llvm.umul.with.overflow.v4i24(<4 x i24> %a0, <4 x i24> %a1)
287  %val = extractvalue {<4 x i24>, <4 x i1>} %t, 0
288  %obit = extractvalue {<4 x i24>, <4 x i1>} %t, 1
289  %res = sext <4 x i1> %obit to <4 x i32>
290  store <4 x i24> %val, ptr %p2
291  ret <4 x i32> %res
292}
293
294define <4 x i32> @umulo_v4i1(<4 x i1> %a0, <4 x i1> %a1, ptr %p2) nounwind {
295; CHECK-LABEL: umulo_v4i1:
296; CHECK:       // %bb.0:
297; CHECK-NEXT:    and v0.8b, v0.8b, v1.8b
298; CHECK-NEXT:    adrp x8, .LCPI10_0
299; CHECK-NEXT:    ldr d1, [x8, :lo12:.LCPI10_0]
300; CHECK-NEXT:    shl v0.4h, v0.4h, #15
301; CHECK-NEXT:    cmlt v0.4h, v0.4h, #0
302; CHECK-NEXT:    and v0.8b, v0.8b, v1.8b
303; CHECK-NEXT:    addv h1, v0.4h
304; CHECK-NEXT:    movi v0.2d, #0000000000000000
305; CHECK-NEXT:    fmov w8, s1
306; CHECK-NEXT:    strb w8, [x0]
307; CHECK-NEXT:    ret
308  %t = call {<4 x i1>, <4 x i1>} @llvm.umul.with.overflow.v4i1(<4 x i1> %a0, <4 x i1> %a1)
309  %val = extractvalue {<4 x i1>, <4 x i1>} %t, 0
310  %obit = extractvalue {<4 x i1>, <4 x i1>} %t, 1
311  %res = sext <4 x i1> %obit to <4 x i32>
312  store <4 x i1> %val, ptr %p2
313  ret <4 x i32> %res
314}
315
316define <2 x i32> @umulo_v2i128(<2 x i128> %a0, <2 x i128> %a1, ptr %p2) nounwind {
317; CHECK-LABEL: umulo_v2i128:
318; CHECK:       // %bb.0:
319; CHECK-NEXT:    mul x9, x7, x2
320; CHECK-NEXT:    cmp x3, #0
321; CHECK-NEXT:    ccmp x7, #0, #4, ne
322; CHECK-NEXT:    umulh x10, x3, x6
323; CHECK-NEXT:    umulh x8, x7, x2
324; CHECK-NEXT:    madd x9, x3, x6, x9
325; CHECK-NEXT:    ccmp xzr, x10, #0, eq
326; CHECK-NEXT:    umulh x11, x2, x6
327; CHECK-NEXT:    ccmp xzr, x8, #0, eq
328; CHECK-NEXT:    mul x13, x5, x0
329; CHECK-NEXT:    cset w8, ne
330; CHECK-NEXT:    umulh x14, x1, x4
331; CHECK-NEXT:    adds x9, x11, x9
332; CHECK-NEXT:    umulh x12, x5, x0
333; CHECK-NEXT:    csinc w8, w8, wzr, lo
334; CHECK-NEXT:    cmp x1, #0
335; CHECK-NEXT:    ccmp x5, #0, #4, ne
336; CHECK-NEXT:    madd x10, x1, x4, x13
337; CHECK-NEXT:    ccmp xzr, x14, #0, eq
338; CHECK-NEXT:    umulh x11, x0, x4
339; CHECK-NEXT:    ccmp xzr, x12, #0, eq
340; CHECK-NEXT:    cset w12, ne
341; CHECK-NEXT:    adds x10, x11, x10
342; CHECK-NEXT:    csinc w11, w12, wzr, lo
343; CHECK-NEXT:    ldr x12, [sp]
344; CHECK-NEXT:    fmov s0, w11
345; CHECK-NEXT:    mul x11, x0, x4
346; CHECK-NEXT:    mov v0.s[1], w8
347; CHECK-NEXT:    mul x8, x2, x6
348; CHECK-NEXT:    stp x11, x10, [x12]
349; CHECK-NEXT:    shl v0.2s, v0.2s, #31
350; CHECK-NEXT:    stp x8, x9, [x12, #16]
351; CHECK-NEXT:    cmlt v0.2s, v0.2s, #0
352; CHECK-NEXT:    ret
353  %t = call {<2 x i128>, <2 x i1>} @llvm.umul.with.overflow.v2i128(<2 x i128> %a0, <2 x i128> %a1)
354  %val = extractvalue {<2 x i128>, <2 x i1>} %t, 0
355  %obit = extractvalue {<2 x i128>, <2 x i1>} %t, 1
356  %res = sext <2 x i1> %obit to <2 x i32>
357  store <2 x i128> %val, ptr %p2
358  ret <2 x i32> %res
359}
360