1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc -mtriple=aarch64-unknown-unknown -O3 -cgp-icmp-eq2icmp-st -verify-machineinstrs < %s | FileCheck %s 3 4; Test cases are generated from: 5; long long NAME(PARAM a, PARAM b) { 6; if (LHS > RHS) 7; return b; 8; if (LHS < RHS) 9; return a;\ 10; return a * b; 11; } 12; Please note funtion name is defined as <PARAM>_<LHS>_<RHS>. Take ll_a_op_b__1 13; for example. ll is PARAM, a_op_b (i.e., a << b) is LHS, _1 (i.e., -1) is RHS. 14 15target datalayout = "e-m:e-i64:64-n32:64" 16 17define i64 @ll_a_op_b__2(i64 %a, i64 %b) { 18; CHECK-LABEL: ll_a_op_b__2: 19; CHECK: // %bb.0: // %entry 20; CHECK-NEXT: lsl x8, x0, x1 21; CHECK-NEXT: cmn x8, #2 22; CHECK-NEXT: csinc x8, x1, xzr, eq 23; CHECK-NEXT: mul x8, x8, x0 24; CHECK-NEXT: csel x0, x1, x8, gt 25; CHECK-NEXT: ret 26entry: 27 %shl = shl i64 %a, %b 28 %cmp = icmp sgt i64 %shl, -2 29 br i1 %cmp, label %return, label %if.end 30 31if.end: ; preds = %entry 32 %cmp2 = icmp eq i64 %shl, -2 33 %mul = select i1 %cmp2, i64 %b, i64 1 34 %spec.select = mul nsw i64 %mul, %a 35 ret i64 %spec.select 36 37return: ; preds = %entry 38 ret i64 %b 39} 40 41define i64 @ll_a_op_b__1(i64 %a, i64 %b) { 42; CHECK-LABEL: ll_a_op_b__1: 43; CHECK: // %bb.0: // %entry 44; CHECK-NEXT: lsl x8, x0, x1 45; CHECK-NEXT: cmn x8, #1 46; CHECK-NEXT: csinc x9, x1, xzr, eq 47; CHECK-NEXT: cmp x8, #0 48; CHECK-NEXT: mul x9, x9, x0 49; CHECK-NEXT: csel x0, x1, x9, ge 50; CHECK-NEXT: ret 51entry: 52 %shl = shl i64 %a, %b 53 %cmp = icmp sgt i64 %shl, -1 54 br i1 %cmp, label %return, label %if.end 55 56if.end: ; preds = %entry 57 %cmp2 = icmp eq i64 %shl, -1 58 %mul = select i1 %cmp2, i64 %b, i64 1 59 %spec.select = mul nsw i64 %mul, %a 60 ret i64 %spec.select 61 62return: ; preds = %entry 63 ret i64 %b 64} 65 66define i64 @ll_a_op_b_0(i64 %a, i64 %b) { 67; CHECK-LABEL: ll_a_op_b_0: 68; CHECK: // %bb.0: // %entry 69; CHECK-NEXT: lsl x8, x0, x1 70; CHECK-NEXT: cmp x8, #0 71; CHECK-NEXT: csinc x8, x1, xzr, eq 72; CHECK-NEXT: mul x8, x8, x0 73; CHECK-NEXT: csel x0, x1, x8, gt 74; CHECK-NEXT: ret 75entry: 76 %shl = shl i64 %a, %b 77 %cmp = icmp sgt i64 %shl, 0 78 br i1 %cmp, label %return, label %if.end 79 80if.end: ; preds = %entry 81 %cmp2 = icmp eq i64 %shl, 0 82 %mul = select i1 %cmp2, i64 %b, i64 1 83 %spec.select = mul nsw i64 %mul, %a 84 ret i64 %spec.select 85 86return: ; preds = %entry 87 ret i64 %b 88} 89 90define i64 @ll_a_op_b_1(i64 %a, i64 %b) { 91; CHECK-LABEL: ll_a_op_b_1: 92; CHECK: // %bb.0: // %entry 93; CHECK-NEXT: lsl x8, x0, x1 94; CHECK-NEXT: cmp x8, #1 95; CHECK-NEXT: csinc x8, x1, xzr, eq 96; CHECK-NEXT: mul x8, x8, x0 97; CHECK-NEXT: csel x0, x1, x8, gt 98; CHECK-NEXT: ret 99entry: 100 %shl = shl i64 %a, %b 101 %cmp = icmp sgt i64 %shl, 1 102 br i1 %cmp, label %return, label %if.end 103 104if.end: ; preds = %entry 105 %cmp2 = icmp eq i64 %shl, 1 106 %mul = select i1 %cmp2, i64 %b, i64 1 107 %spec.select = mul nsw i64 %mul, %a 108 ret i64 %spec.select 109 110return: ; preds = %entry 111 ret i64 %b 112} 113 114define i64 @ll_a_op_b_2(i64 %a, i64 %b) { 115; CHECK-LABEL: ll_a_op_b_2: 116; CHECK: // %bb.0: // %entry 117; CHECK-NEXT: lsl x8, x0, x1 118; CHECK-NEXT: cmp x8, #2 119; CHECK-NEXT: csinc x8, x1, xzr, eq 120; CHECK-NEXT: mul x8, x8, x0 121; CHECK-NEXT: csel x0, x1, x8, gt 122; CHECK-NEXT: ret 123entry: 124 %shl = shl i64 %a, %b 125 %cmp = icmp sgt i64 %shl, 2 126 br i1 %cmp, label %return, label %if.end 127 128if.end: ; preds = %entry 129 %cmp2 = icmp eq i64 %shl, 2 130 %mul = select i1 %cmp2, i64 %b, i64 1 131 %spec.select = mul nsw i64 %mul, %a 132 ret i64 %spec.select 133 134return: ; preds = %entry 135 ret i64 %b 136} 137 138define i64 @ll_a__2(i64 %a, i64 %b) { 139; CHECK-LABEL: ll_a__2: 140; CHECK: // %bb.0: // %entry 141; CHECK-NEXT: cmn x0, #2 142; CHECK-NEXT: csinc x8, x1, xzr, eq 143; CHECK-NEXT: mul x8, x8, x0 144; CHECK-NEXT: csel x0, x1, x8, gt 145; CHECK-NEXT: ret 146entry: 147 %cmp = icmp sgt i64 %a, -2 148 br i1 %cmp, label %return, label %if.end 149 150if.end: ; preds = %entry 151 %cmp1 = icmp eq i64 %a, -2 152 %mul = select i1 %cmp1, i64 %b, i64 1 153 %spec.select = mul nsw i64 %mul, %a 154 ret i64 %spec.select 155 156return: ; preds = %entry 157 ret i64 %b 158} 159 160define i64 @ll_a__1(i64 %a, i64 %b) { 161; CHECK-LABEL: ll_a__1: 162; CHECK: // %bb.0: // %entry 163; CHECK-NEXT: cmn x0, #1 164; CHECK-NEXT: csinc x8, x1, xzr, eq 165; CHECK-NEXT: cmp x0, #0 166; CHECK-NEXT: mul x8, x8, x0 167; CHECK-NEXT: csel x0, x1, x8, ge 168; CHECK-NEXT: ret 169entry: 170 %cmp = icmp sgt i64 %a, -1 171 br i1 %cmp, label %return, label %if.end 172 173if.end: ; preds = %entry 174 %cmp1 = icmp eq i64 %a, -1 175 %mul = select i1 %cmp1, i64 %b, i64 1 176 %spec.select = mul nsw i64 %mul, %a 177 ret i64 %spec.select 178 179return: ; preds = %entry 180 ret i64 %b 181} 182 183define i64 @ll_a_0(i64 %a, i64 %b) { 184; CHECK-LABEL: ll_a_0: 185; CHECK: // %bb.0: // %entry 186; CHECK-NEXT: cmp x0, #0 187; CHECK-NEXT: csinc x8, x1, xzr, eq 188; CHECK-NEXT: mul x8, x8, x0 189; CHECK-NEXT: csel x0, x1, x8, gt 190; CHECK-NEXT: ret 191entry: 192 %cmp = icmp sgt i64 %a, 0 193 br i1 %cmp, label %return, label %if.end 194 195if.end: ; preds = %entry 196 %cmp1 = icmp eq i64 %a, 0 197 %mul = select i1 %cmp1, i64 %b, i64 1 198 %spec.select = mul nsw i64 %mul, %a 199 ret i64 %spec.select 200 201return: ; preds = %entry 202 ret i64 %b 203} 204 205define i64 @ll_a_1(i64 %a, i64 %b) { 206; CHECK-LABEL: ll_a_1: 207; CHECK: // %bb.0: // %entry 208; CHECK-NEXT: cmp x0, #1 209; CHECK-NEXT: csinc x8, x1, xzr, eq 210; CHECK-NEXT: mul x8, x8, x0 211; CHECK-NEXT: csel x0, x1, x8, gt 212; CHECK-NEXT: ret 213entry: 214 %cmp = icmp sgt i64 %a, 1 215 br i1 %cmp, label %return, label %if.end 216 217if.end: ; preds = %entry 218 %cmp1 = icmp eq i64 %a, 1 219 %mul = select i1 %cmp1, i64 %b, i64 1 220 %spec.select = mul nsw i64 %mul, %a 221 ret i64 %spec.select 222 223return: ; preds = %entry 224 ret i64 %b 225} 226 227define i64 @ll_a_2(i64 %a, i64 %b) { 228; CHECK-LABEL: ll_a_2: 229; CHECK: // %bb.0: // %entry 230; CHECK-NEXT: cmp x0, #2 231; CHECK-NEXT: csinc x8, x1, xzr, eq 232; CHECK-NEXT: mul x8, x8, x0 233; CHECK-NEXT: csel x0, x1, x8, gt 234; CHECK-NEXT: ret 235entry: 236 %cmp = icmp sgt i64 %a, 2 237 br i1 %cmp, label %return, label %if.end 238 239if.end: ; preds = %entry 240 %cmp1 = icmp eq i64 %a, 2 241 %mul = select i1 %cmp1, i64 %b, i64 1 242 %spec.select = mul nsw i64 %mul, %a 243 ret i64 %spec.select 244 245return: ; preds = %entry 246 ret i64 %b 247} 248 249define i64 @i_a_op_b__2(i32 signext %a, i32 signext %b) { 250; CHECK-LABEL: i_a_op_b__2: 251; CHECK: // %bb.0: // %entry 252; CHECK-NEXT: lsl w8, w0, w1 253; CHECK-NEXT: cmn w8, #2 254; CHECK-NEXT: csinc w8, w1, wzr, eq 255; CHECK-NEXT: mul w8, w8, w0 256; CHECK-NEXT: csel w8, w1, w8, gt 257; CHECK-NEXT: sxtw x0, w8 258; CHECK-NEXT: ret 259entry: 260 %shl = shl i32 %a, %b 261 %cmp = icmp sgt i32 %shl, -2 262 br i1 %cmp, label %return, label %if.end 263 264if.end: ; preds = %entry 265 %cmp2 = icmp eq i32 %shl, -2 266 %mul = select i1 %cmp2, i32 %b, i32 1 267 %spec.select = mul nsw i32 %mul, %a 268 br label %return 269 270return: ; preds = %if.end, %entry 271 %retval.0.in = phi i32 [ %b, %entry ], [ %spec.select, %if.end ] 272 %retval.0 = sext i32 %retval.0.in to i64 273 ret i64 %retval.0 274} 275 276define i64 @i_a_op_b__1(i32 signext %a, i32 signext %b) { 277; CHECK-LABEL: i_a_op_b__1: 278; CHECK: // %bb.0: // %entry 279; CHECK-NEXT: lsl w8, w0, w1 280; CHECK-NEXT: cmn w8, #1 281; CHECK-NEXT: csinc w9, w1, wzr, eq 282; CHECK-NEXT: cmp w8, #0 283; CHECK-NEXT: mul w9, w9, w0 284; CHECK-NEXT: csel w8, w1, w9, ge 285; CHECK-NEXT: sxtw x0, w8 286; CHECK-NEXT: ret 287entry: 288 %shl = shl i32 %a, %b 289 %cmp = icmp sgt i32 %shl, -1 290 br i1 %cmp, label %return, label %if.end 291 292if.end: ; preds = %entry 293 %cmp2 = icmp eq i32 %shl, -1 294 %mul = select i1 %cmp2, i32 %b, i32 1 295 %spec.select = mul nsw i32 %mul, %a 296 br label %return 297 298return: ; preds = %if.end, %entry 299 %retval.0.in = phi i32 [ %b, %entry ], [ %spec.select, %if.end ] 300 %retval.0 = sext i32 %retval.0.in to i64 301 ret i64 %retval.0 302} 303 304define i64 @i_a_op_b_0(i32 signext %a, i32 signext %b) { 305; CHECK-LABEL: i_a_op_b_0: 306; CHECK: // %bb.0: // %entry 307; CHECK-NEXT: lsl w8, w0, w1 308; CHECK-NEXT: cmp w8, #0 309; CHECK-NEXT: csinc w8, w1, wzr, eq 310; CHECK-NEXT: mul w8, w8, w0 311; CHECK-NEXT: csel w8, w1, w8, gt 312; CHECK-NEXT: sxtw x0, w8 313; CHECK-NEXT: ret 314entry: 315 %shl = shl i32 %a, %b 316 %cmp = icmp sgt i32 %shl, 0 317 br i1 %cmp, label %return, label %if.end 318 319if.end: ; preds = %entry 320 %cmp2 = icmp eq i32 %shl, 0 321 %mul = select i1 %cmp2, i32 %b, i32 1 322 %spec.select = mul nsw i32 %mul, %a 323 br label %return 324 325return: ; preds = %if.end, %entry 326 %retval.0.in = phi i32 [ %b, %entry ], [ %spec.select, %if.end ] 327 %retval.0 = sext i32 %retval.0.in to i64 328 ret i64 %retval.0 329} 330 331define i64 @i_a_op_b_1(i32 signext %a, i32 signext %b) { 332; CHECK-LABEL: i_a_op_b_1: 333; CHECK: // %bb.0: // %entry 334; CHECK-NEXT: lsl w8, w0, w1 335; CHECK-NEXT: cmp w8, #1 336; CHECK-NEXT: csinc w8, w1, wzr, eq 337; CHECK-NEXT: mul w8, w8, w0 338; CHECK-NEXT: csel w8, w1, w8, gt 339; CHECK-NEXT: sxtw x0, w8 340; CHECK-NEXT: ret 341entry: 342 %shl = shl i32 %a, %b 343 %cmp = icmp sgt i32 %shl, 1 344 br i1 %cmp, label %return, label %if.end 345 346if.end: ; preds = %entry 347 %cmp2 = icmp eq i32 %shl, 1 348 %mul = select i1 %cmp2, i32 %b, i32 1 349 %spec.select = mul nsw i32 %mul, %a 350 br label %return 351 352return: ; preds = %if.end, %entry 353 %retval.0.in = phi i32 [ %b, %entry ], [ %spec.select, %if.end ] 354 %retval.0 = sext i32 %retval.0.in to i64 355 ret i64 %retval.0 356} 357 358define i64 @i_a_op_b_2(i32 signext %a, i32 signext %b) { 359; CHECK-LABEL: i_a_op_b_2: 360; CHECK: // %bb.0: // %entry 361; CHECK-NEXT: lsl w8, w0, w1 362; CHECK-NEXT: cmp w8, #2 363; CHECK-NEXT: csinc w8, w1, wzr, eq 364; CHECK-NEXT: mul w8, w8, w0 365; CHECK-NEXT: csel w8, w1, w8, gt 366; CHECK-NEXT: sxtw x0, w8 367; CHECK-NEXT: ret 368entry: 369 %shl = shl i32 %a, %b 370 %cmp = icmp sgt i32 %shl, 2 371 br i1 %cmp, label %return, label %if.end 372 373if.end: ; preds = %entry 374 %cmp2 = icmp eq i32 %shl, 2 375 %mul = select i1 %cmp2, i32 %b, i32 1 376 %spec.select = mul nsw i32 %mul, %a 377 br label %return 378 379return: ; preds = %if.end, %entry 380 %retval.0.in = phi i32 [ %b, %entry ], [ %spec.select, %if.end ] 381 %retval.0 = sext i32 %retval.0.in to i64 382 ret i64 %retval.0 383} 384 385define i64 @i_a__2(i32 signext %a, i32 signext %b) { 386; CHECK-LABEL: i_a__2: 387; CHECK: // %bb.0: // %entry 388; CHECK-NEXT: cmn w0, #2 389; CHECK-NEXT: csinc w8, w1, wzr, eq 390; CHECK-NEXT: mul w8, w8, w0 391; CHECK-NEXT: csel w8, w1, w8, gt 392; CHECK-NEXT: sxtw x0, w8 393; CHECK-NEXT: ret 394entry: 395 %cmp = icmp sgt i32 %a, -2 396 br i1 %cmp, label %return, label %if.end 397 398if.end: ; preds = %entry 399 %cmp1 = icmp eq i32 %a, -2 400 %mul = select i1 %cmp1, i32 %b, i32 1 401 %spec.select = mul nsw i32 %mul, %a 402 br label %return 403 404return: ; preds = %if.end, %entry 405 %retval.0.in = phi i32 [ %b, %entry ], [ %spec.select, %if.end ] 406 %retval.0 = sext i32 %retval.0.in to i64 407 ret i64 %retval.0 408} 409 410define i64 @i_a__1(i32 signext %a, i32 signext %b) { 411; CHECK-LABEL: i_a__1: 412; CHECK: // %bb.0: // %entry 413; CHECK-NEXT: cmn w0, #1 414; CHECK-NEXT: csinc w8, w1, wzr, eq 415; CHECK-NEXT: cmp w0, #0 416; CHECK-NEXT: mul w8, w8, w0 417; CHECK-NEXT: csel w8, w1, w8, ge 418; CHECK-NEXT: sxtw x0, w8 419; CHECK-NEXT: ret 420entry: 421 %cmp = icmp sgt i32 %a, -1 422 br i1 %cmp, label %return, label %if.end 423 424if.end: ; preds = %entry 425 %cmp1 = icmp eq i32 %a, -1 426 %mul = select i1 %cmp1, i32 %b, i32 1 427 %spec.select = mul nsw i32 %mul, %a 428 br label %return 429 430return: ; preds = %if.end, %entry 431 %retval.0.in = phi i32 [ %b, %entry ], [ %spec.select, %if.end ] 432 %retval.0 = sext i32 %retval.0.in to i64 433 ret i64 %retval.0 434} 435 436define i64 @i_a_0(i32 signext %a, i32 signext %b) { 437; CHECK-LABEL: i_a_0: 438; CHECK: // %bb.0: // %entry 439; CHECK-NEXT: cmp w0, #0 440; CHECK-NEXT: csinc w8, w1, wzr, eq 441; CHECK-NEXT: mul w8, w8, w0 442; CHECK-NEXT: csel w8, w1, w8, gt 443; CHECK-NEXT: sxtw x0, w8 444; CHECK-NEXT: ret 445entry: 446 %cmp = icmp sgt i32 %a, 0 447 br i1 %cmp, label %return, label %if.end 448 449if.end: ; preds = %entry 450 %cmp1 = icmp eq i32 %a, 0 451 %mul = select i1 %cmp1, i32 %b, i32 1 452 %spec.select = mul nsw i32 %mul, %a 453 br label %return 454 455return: ; preds = %if.end, %entry 456 %retval.0.in = phi i32 [ %b, %entry ], [ %spec.select, %if.end ] 457 %retval.0 = sext i32 %retval.0.in to i64 458 ret i64 %retval.0 459} 460 461define i64 @i_a_1(i32 signext %a, i32 signext %b) { 462; CHECK-LABEL: i_a_1: 463; CHECK: // %bb.0: // %entry 464; CHECK-NEXT: cmp w0, #1 465; CHECK-NEXT: csinc w8, w1, wzr, eq 466; CHECK-NEXT: mul w8, w8, w0 467; CHECK-NEXT: csel w8, w1, w8, gt 468; CHECK-NEXT: sxtw x0, w8 469; CHECK-NEXT: ret 470entry: 471 %cmp = icmp sgt i32 %a, 1 472 br i1 %cmp, label %return, label %if.end 473 474if.end: ; preds = %entry 475 %cmp1 = icmp eq i32 %a, 1 476 %mul = select i1 %cmp1, i32 %b, i32 1 477 %spec.select = mul nsw i32 %mul, %a 478 br label %return 479 480return: ; preds = %if.end, %entry 481 %retval.0.in = phi i32 [ %b, %entry ], [ %spec.select, %if.end ] 482 %retval.0 = sext i32 %retval.0.in to i64 483 ret i64 %retval.0 484} 485 486define i64 @i_a_2(i32 signext %a, i32 signext %b) { 487; CHECK-LABEL: i_a_2: 488; CHECK: // %bb.0: // %entry 489; CHECK-NEXT: cmp w0, #2 490; CHECK-NEXT: csinc w8, w1, wzr, eq 491; CHECK-NEXT: mul w8, w8, w0 492; CHECK-NEXT: csel w8, w1, w8, gt 493; CHECK-NEXT: sxtw x0, w8 494; CHECK-NEXT: ret 495entry: 496 %cmp = icmp sgt i32 %a, 2 497 br i1 %cmp, label %return, label %if.end 498 499if.end: ; preds = %entry 500 %cmp1 = icmp eq i32 %a, 2 501 %mul = select i1 %cmp1, i32 %b, i32 1 502 %spec.select = mul nsw i32 %mul, %a 503 br label %return 504 505return: ; preds = %if.end, %entry 506 %retval.0.in = phi i32 [ %b, %entry ], [ %spec.select, %if.end ] 507 %retval.0 = sext i32 %retval.0.in to i64 508 ret i64 %retval.0 509} 510