xref: /llvm-project/llvm/test/CodeGen/AArch64/urem-seteq-vec-tautological.ll (revision db158c7c830807caeeb0691739c41f1d522029e9) 
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple=aarch64-unknown-linux-gnu < %s | FileCheck %s
3
4define <4 x i1> @t0_all_tautological(<4 x i32> %X) nounwind {
5; CHECK-LABEL: t0_all_tautological:
6; CHECK:       // %bb.0:
7; CHECK-NEXT:    adrp x8, .LCPI0_0
8; CHECK-NEXT:    ldr q1, [x8, :lo12:.LCPI0_0]
9; CHECK-NEXT:    adrp x8, .LCPI0_1
10; CHECK-NEXT:    and v0.16b, v0.16b, v1.16b
11; CHECK-NEXT:    ldr q1, [x8, :lo12:.LCPI0_1]
12; CHECK-NEXT:    cmeq v0.4s, v0.4s, v1.4s
13; CHECK-NEXT:    xtn v0.4h, v0.4s
14; CHECK-NEXT:    ret
15  %urem = urem <4 x i32> %X, <i32 1, i32 1, i32 2, i32 2>
16  %cmp = icmp eq <4 x i32> %urem, <i32 0, i32 1, i32 2, i32 3>
17  ret <4 x i1> %cmp
18}
19
20define <4 x i1> @t1_all_odd_eq(<4 x i32> %X) nounwind {
21; CHECK-LABEL: t1_all_odd_eq:
22; CHECK:       // %bb.0:
23; CHECK-NEXT:    mov w8, #43691 // =0xaaab
24; CHECK-NEXT:    movk w8, #43690, lsl #16
25; CHECK-NEXT:    dup v1.4s, w8
26; CHECK-NEXT:    adrp x8, .LCPI1_0
27; CHECK-NEXT:    mul v0.4s, v0.4s, v1.4s
28; CHECK-NEXT:    ldr q1, [x8, :lo12:.LCPI1_0]
29; CHECK-NEXT:    cmhs v0.4s, v1.4s, v0.4s
30; CHECK-NEXT:    movi d1, #0xffff0000ffff0000
31; CHECK-NEXT:    xtn v0.4h, v0.4s
32; CHECK-NEXT:    eor v0.8b, v0.8b, v1.8b
33; CHECK-NEXT:    ret
34  %urem = urem <4 x i32> %X, <i32 3, i32 1, i32 1, i32 9>
35  %cmp = icmp eq <4 x i32> %urem, <i32 0, i32 42, i32 0, i32 42>
36  ret <4 x i1> %cmp
37}
38
39define <4 x i1> @t1_all_odd_ne(<4 x i32> %X) nounwind {
40; CHECK-LABEL: t1_all_odd_ne:
41; CHECK:       // %bb.0:
42; CHECK-NEXT:    mov w8, #43691 // =0xaaab
43; CHECK-NEXT:    movk w8, #43690, lsl #16
44; CHECK-NEXT:    dup v1.4s, w8
45; CHECK-NEXT:    adrp x8, .LCPI2_0
46; CHECK-NEXT:    mul v0.4s, v0.4s, v1.4s
47; CHECK-NEXT:    ldr q1, [x8, :lo12:.LCPI2_0]
48; CHECK-NEXT:    cmhi v0.4s, v0.4s, v1.4s
49; CHECK-NEXT:    movi d1, #0xffff0000ffff0000
50; CHECK-NEXT:    xtn v0.4h, v0.4s
51; CHECK-NEXT:    eor v0.8b, v0.8b, v1.8b
52; CHECK-NEXT:    ret
53  %urem = urem <4 x i32> %X, <i32 3, i32 1, i32 1, i32 9>
54  %cmp = icmp ne <4 x i32> %urem, <i32 0, i32 42, i32 0, i32 42>
55  ret <4 x i1> %cmp
56}
57
58define <8 x i1> @t2_narrow(<8 x i16> %X) nounwind {
59; CHECK-LABEL: t2_narrow:
60; CHECK:       // %bb.0:
61; CHECK-NEXT:    mov w8, #43691 // =0xaaab
62; CHECK-NEXT:    dup v1.8h, w8
63; CHECK-NEXT:    adrp x8, .LCPI3_0
64; CHECK-NEXT:    mul v0.8h, v0.8h, v1.8h
65; CHECK-NEXT:    ldr q1, [x8, :lo12:.LCPI3_0]
66; CHECK-NEXT:    cmhs v0.8h, v1.8h, v0.8h
67; CHECK-NEXT:    movi d1, #0xffff0000ffff0000
68; CHECK-NEXT:    xtn v0.8b, v0.8h
69; CHECK-NEXT:    eor v0.8b, v0.8b, v1.8b
70; CHECK-NEXT:    ret
71  %urem = urem <8 x i16> %X, <i16 3, i16 1, i16 1, i16 9, i16 3, i16 1, i16 1, i16 9>
72  %cmp = icmp eq <8 x i16> %urem, <i16 0, i16 0, i16 42, i16 42, i16 0, i16 0, i16 42, i16 42>
73  ret <8 x i1> %cmp
74}
75
76define <2 x i1> @t3_wide(<2 x i64> %X) nounwind {
77; CHECK-LABEL: t3_wide:
78; CHECK:       // %bb.0:
79; CHECK-NEXT:    fmov x10, d0
80; CHECK-NEXT:    mov x8, #-6148914691236517206 // =0xaaaaaaaaaaaaaaaa
81; CHECK-NEXT:    mov x9, v0.d[1]
82; CHECK-NEXT:    movk x8, #43691
83; CHECK-NEXT:    mul x10, x10, x8
84; CHECK-NEXT:    mul x8, x9, x8
85; CHECK-NEXT:    fmov d0, x10
86; CHECK-NEXT:    mov v0.d[1], x8
87; CHECK-NEXT:    adrp x8, .LCPI4_0
88; CHECK-NEXT:    ldr q1, [x8, :lo12:.LCPI4_0]
89; CHECK-NEXT:    cmhs v0.2d, v1.2d, v0.2d
90; CHECK-NEXT:    movi d1, #0xffffffff00000000
91; CHECK-NEXT:    xtn v0.2s, v0.2d
92; CHECK-NEXT:    eor v0.8b, v0.8b, v1.8b
93; CHECK-NEXT:    ret
94  %urem = urem <2 x i64> %X, <i64 3, i64 1>
95  %cmp = icmp eq <2 x i64> %urem, <i64 0, i64 42>
96  ret <2 x i1> %cmp
97}
98