1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc -mtriple=aarch64-unknown-linux-gnu < %s | FileCheck %s 3 4define <4 x i1> @t32_3(<4 x i32> %X) nounwind { 5; CHECK-LABEL: t32_3: 6; CHECK: // %bb.0: 7; CHECK-NEXT: adrp x8, .LCPI0_0 8; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI0_0] 9; CHECK-NEXT: mov w8, #43691 // =0xaaab 10; CHECK-NEXT: movk w8, #43690, lsl #16 11; CHECK-NEXT: sub v0.4s, v0.4s, v1.4s 12; CHECK-NEXT: dup v1.4s, w8 13; CHECK-NEXT: adrp x8, .LCPI0_1 14; CHECK-NEXT: mul v0.4s, v0.4s, v1.4s 15; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI0_1] 16; CHECK-NEXT: cmhs v0.4s, v1.4s, v0.4s 17; CHECK-NEXT: xtn v0.4h, v0.4s 18; CHECK-NEXT: ret 19 %urem = urem <4 x i32> %X, <i32 3, i32 3, i32 3, i32 3> 20 %cmp = icmp eq <4 x i32> %urem, <i32 0, i32 1, i32 2, i32 2> 21 ret <4 x i1> %cmp 22} 23 24define <4 x i1> @t32_5(<4 x i32> %X) nounwind { 25; CHECK-LABEL: t32_5: 26; CHECK: // %bb.0: 27; CHECK-NEXT: adrp x8, .LCPI1_0 28; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI1_0] 29; CHECK-NEXT: mov w8, #52429 // =0xcccd 30; CHECK-NEXT: movk w8, #52428, lsl #16 31; CHECK-NEXT: sub v0.4s, v0.4s, v1.4s 32; CHECK-NEXT: dup v1.4s, w8 33; CHECK-NEXT: mov w8, #13106 // =0x3332 34; CHECK-NEXT: movk w8, #13107, lsl #16 35; CHECK-NEXT: mul v0.4s, v0.4s, v1.4s 36; CHECK-NEXT: dup v1.4s, w8 37; CHECK-NEXT: cmhs v0.4s, v1.4s, v0.4s 38; CHECK-NEXT: xtn v0.4h, v0.4s 39; CHECK-NEXT: ret 40 %urem = urem <4 x i32> %X, <i32 5, i32 5, i32 5, i32 5> 41 %cmp = icmp eq <4 x i32> %urem, <i32 1, i32 2, i32 3, i32 4> 42 ret <4 x i1> %cmp 43} 44 45define <4 x i1> @t32_6_part0(<4 x i32> %X) nounwind { 46; CHECK-LABEL: t32_6_part0: 47; CHECK: // %bb.0: 48; CHECK-NEXT: adrp x8, .LCPI2_0 49; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI2_0] 50; CHECK-NEXT: mov w8, #43691 // =0xaaab 51; CHECK-NEXT: movk w8, #43690, lsl #16 52; CHECK-NEXT: sub v0.4s, v0.4s, v1.4s 53; CHECK-NEXT: dup v1.4s, w8 54; CHECK-NEXT: mul v0.4s, v0.4s, v1.4s 55; CHECK-NEXT: movi v1.16b, #170 56; CHECK-NEXT: shl v2.4s, v0.4s, #31 57; CHECK-NEXT: fneg v1.4s, v1.4s 58; CHECK-NEXT: usra v2.4s, v0.4s, #1 59; CHECK-NEXT: cmhs v0.4s, v1.4s, v2.4s 60; CHECK-NEXT: xtn v0.4h, v0.4s 61; CHECK-NEXT: ret 62 %urem = urem <4 x i32> %X, <i32 6, i32 6, i32 6, i32 6> 63 %cmp = icmp eq <4 x i32> %urem, <i32 0, i32 1, i32 2, i32 3> 64 ret <4 x i1> %cmp 65} 66 67define <4 x i1> @t32_6_part1(<4 x i32> %X) nounwind { 68; CHECK-LABEL: t32_6_part1: 69; CHECK: // %bb.0: 70; CHECK-NEXT: adrp x8, .LCPI3_0 71; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI3_0] 72; CHECK-NEXT: mov w8, #43691 // =0xaaab 73; CHECK-NEXT: movk w8, #43690, lsl #16 74; CHECK-NEXT: sub v0.4s, v0.4s, v1.4s 75; CHECK-NEXT: dup v1.4s, w8 76; CHECK-NEXT: adrp x8, .LCPI3_1 77; CHECK-NEXT: mul v0.4s, v0.4s, v1.4s 78; CHECK-NEXT: shl v1.4s, v0.4s, #31 79; CHECK-NEXT: usra v1.4s, v0.4s, #1 80; CHECK-NEXT: ldr q0, [x8, :lo12:.LCPI3_1] 81; CHECK-NEXT: cmhs v0.4s, v0.4s, v1.4s 82; CHECK-NEXT: xtn v0.4h, v0.4s 83; CHECK-NEXT: ret 84 %urem = urem <4 x i32> %X, <i32 6, i32 6, i32 6, i32 6> 85 %cmp = icmp eq <4 x i32> %urem, <i32 4, i32 5, i32 0, i32 0> 86 ret <4 x i1> %cmp 87} 88 89define <4 x i1> @t32_tautological(<4 x i32> %X) nounwind { 90; CHECK-LABEL: t32_tautological: 91; CHECK: // %bb.0: 92; CHECK-NEXT: adrp x8, .LCPI4_0 93; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI4_0] 94; CHECK-NEXT: mov w8, #43691 // =0xaaab 95; CHECK-NEXT: movk w8, #43690, lsl #16 96; CHECK-NEXT: sub v0.4s, v0.4s, v1.4s 97; CHECK-NEXT: dup v1.4s, w8 98; CHECK-NEXT: adrp x8, .LCPI4_1 99; CHECK-NEXT: mul v0.4s, v0.4s, v1.4s 100; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI4_1] 101; CHECK-NEXT: cmhs v0.4s, v1.4s, v0.4s 102; CHECK-NEXT: movi d1, #0x00ffffffff0000 103; CHECK-NEXT: xtn v0.4h, v0.4s 104; CHECK-NEXT: eor v0.8b, v0.8b, v1.8b 105; CHECK-NEXT: ret 106 %urem = urem <4 x i32> %X, <i32 1, i32 1, i32 2, i32 3> 107 %cmp = icmp eq <4 x i32> %urem, <i32 0, i32 1, i32 2, i32 2> 108 ret <4 x i1> %cmp 109} 110