xref: /llvm-project/llvm/test/CodeGen/AArch64/urem-seteq-vec-nonsplat.ll (revision db158c7c830807caeeb0691739c41f1d522029e9) 
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple=aarch64-unknown-linux-gnu < %s | FileCheck %s
3
4; Odd+Even divisors
5define <4 x i32> @test_urem_odd_even(<4 x i32> %X) nounwind {
6; CHECK-LABEL: test_urem_odd_even:
7; CHECK:       // %bb.0:
8; CHECK-NEXT:    adrp x8, .LCPI0_0
9; CHECK-NEXT:    adrp x9, .LCPI0_2
10; CHECK-NEXT:    ldr q1, [x8, :lo12:.LCPI0_0]
11; CHECK-NEXT:    adrp x8, .LCPI0_1
12; CHECK-NEXT:    ldr q2, [x9, :lo12:.LCPI0_2]
13; CHECK-NEXT:    mul v0.4s, v0.4s, v1.4s
14; CHECK-NEXT:    ldr q1, [x8, :lo12:.LCPI0_1]
15; CHECK-NEXT:    adrp x8, .LCPI0_3
16; CHECK-NEXT:    ushl v1.4s, v0.4s, v1.4s
17; CHECK-NEXT:    ushl v0.4s, v0.4s, v2.4s
18; CHECK-NEXT:    movi v2.4s, #1
19; CHECK-NEXT:    orr v0.16b, v0.16b, v1.16b
20; CHECK-NEXT:    ldr q1, [x8, :lo12:.LCPI0_3]
21; CHECK-NEXT:    cmhs v0.4s, v1.4s, v0.4s
22; CHECK-NEXT:    and v0.16b, v0.16b, v2.16b
23; CHECK-NEXT:    ret
24  %urem = urem <4 x i32> %X, <i32 5, i32 14, i32 25, i32 100>
25  %cmp = icmp eq <4 x i32> %urem, <i32 0, i32 0, i32 0, i32 0>
26  %ret = zext <4 x i1> %cmp to <4 x i32>
27  ret <4 x i32> %ret
28}
29
30;==============================================================================;
31
32; One all-ones divisor in odd divisor
33define <4 x i32> @test_urem_odd_allones_eq(<4 x i32> %X) nounwind {
34; CHECK-LABEL: test_urem_odd_allones_eq:
35; CHECK:       // %bb.0:
36; CHECK-NEXT:    adrp x8, .LCPI1_0
37; CHECK-NEXT:    movi v2.4s, #1
38; CHECK-NEXT:    ldr q1, [x8, :lo12:.LCPI1_0]
39; CHECK-NEXT:    adrp x8, .LCPI1_1
40; CHECK-NEXT:    mul v0.4s, v0.4s, v1.4s
41; CHECK-NEXT:    ldr q1, [x8, :lo12:.LCPI1_1]
42; CHECK-NEXT:    cmhs v0.4s, v1.4s, v0.4s
43; CHECK-NEXT:    and v0.16b, v0.16b, v2.16b
44; CHECK-NEXT:    ret
45  %urem = urem <4 x i32> %X, <i32 5, i32 5, i32 4294967295, i32 5>
46  %cmp = icmp eq <4 x i32> %urem, <i32 0, i32 0, i32 0, i32 0>
47  %ret = zext <4 x i1> %cmp to <4 x i32>
48  ret <4 x i32> %ret
49}
50define <4 x i32> @test_urem_odd_allones_ne(<4 x i32> %X) nounwind {
51; CHECK-LABEL: test_urem_odd_allones_ne:
52; CHECK:       // %bb.0:
53; CHECK-NEXT:    adrp x8, .LCPI2_0
54; CHECK-NEXT:    movi v2.4s, #1
55; CHECK-NEXT:    ldr q1, [x8, :lo12:.LCPI2_0]
56; CHECK-NEXT:    adrp x8, .LCPI2_1
57; CHECK-NEXT:    mul v0.4s, v0.4s, v1.4s
58; CHECK-NEXT:    ldr q1, [x8, :lo12:.LCPI2_1]
59; CHECK-NEXT:    cmhi v0.4s, v0.4s, v1.4s
60; CHECK-NEXT:    and v0.16b, v0.16b, v2.16b
61; CHECK-NEXT:    ret
62  %urem = urem <4 x i32> %X, <i32 5, i32 5, i32 4294967295, i32 5>
63  %cmp = icmp ne <4 x i32> %urem, <i32 0, i32 0, i32 0, i32 0>
64  %ret = zext <4 x i1> %cmp to <4 x i32>
65  ret <4 x i32> %ret
66}
67
68; One all-ones divisor in even divisor
69define <4 x i32> @test_urem_even_allones_eq(<4 x i32> %X) nounwind {
70; CHECK-LABEL: test_urem_even_allones_eq:
71; CHECK:       // %bb.0:
72; CHECK-NEXT:    adrp x8, .LCPI3_0
73; CHECK-NEXT:    adrp x9, .LCPI3_2
74; CHECK-NEXT:    ldr q1, [x8, :lo12:.LCPI3_0]
75; CHECK-NEXT:    adrp x8, .LCPI3_1
76; CHECK-NEXT:    ldr q2, [x9, :lo12:.LCPI3_2]
77; CHECK-NEXT:    mul v0.4s, v0.4s, v1.4s
78; CHECK-NEXT:    ldr q1, [x8, :lo12:.LCPI3_1]
79; CHECK-NEXT:    adrp x8, .LCPI3_3
80; CHECK-NEXT:    ushl v1.4s, v0.4s, v1.4s
81; CHECK-NEXT:    ushl v0.4s, v0.4s, v2.4s
82; CHECK-NEXT:    movi v2.4s, #1
83; CHECK-NEXT:    orr v0.16b, v0.16b, v1.16b
84; CHECK-NEXT:    ldr q1, [x8, :lo12:.LCPI3_3]
85; CHECK-NEXT:    cmhs v0.4s, v1.4s, v0.4s
86; CHECK-NEXT:    and v0.16b, v0.16b, v2.16b
87; CHECK-NEXT:    ret
88  %urem = urem <4 x i32> %X, <i32 14, i32 14, i32 4294967295, i32 14>
89  %cmp = icmp eq <4 x i32> %urem, <i32 0, i32 0, i32 0, i32 0>
90  %ret = zext <4 x i1> %cmp to <4 x i32>
91  ret <4 x i32> %ret
92}
93define <4 x i32> @test_urem_even_allones_ne(<4 x i32> %X) nounwind {
94; CHECK-LABEL: test_urem_even_allones_ne:
95; CHECK:       // %bb.0:
96; CHECK-NEXT:    adrp x8, .LCPI4_0
97; CHECK-NEXT:    adrp x9, .LCPI4_2
98; CHECK-NEXT:    ldr q1, [x8, :lo12:.LCPI4_0]
99; CHECK-NEXT:    adrp x8, .LCPI4_1
100; CHECK-NEXT:    ldr q2, [x9, :lo12:.LCPI4_2]
101; CHECK-NEXT:    mul v0.4s, v0.4s, v1.4s
102; CHECK-NEXT:    ldr q1, [x8, :lo12:.LCPI4_1]
103; CHECK-NEXT:    adrp x8, .LCPI4_3
104; CHECK-NEXT:    ushl v1.4s, v0.4s, v1.4s
105; CHECK-NEXT:    ushl v0.4s, v0.4s, v2.4s
106; CHECK-NEXT:    movi v2.4s, #1
107; CHECK-NEXT:    orr v0.16b, v0.16b, v1.16b
108; CHECK-NEXT:    ldr q1, [x8, :lo12:.LCPI4_3]
109; CHECK-NEXT:    cmhi v0.4s, v0.4s, v1.4s
110; CHECK-NEXT:    and v0.16b, v0.16b, v2.16b
111; CHECK-NEXT:    ret
112  %urem = urem <4 x i32> %X, <i32 14, i32 14, i32 4294967295, i32 14>
113  %cmp = icmp ne <4 x i32> %urem, <i32 0, i32 0, i32 0, i32 0>
114  %ret = zext <4 x i1> %cmp to <4 x i32>
115  ret <4 x i32> %ret
116}
117
118; One all-ones divisor in odd+even divisor
119define <4 x i32> @test_urem_odd_even_allones_eq(<4 x i32> %X) nounwind {
120; CHECK-LABEL: test_urem_odd_even_allones_eq:
121; CHECK:       // %bb.0:
122; CHECK-NEXT:    adrp x8, .LCPI5_0
123; CHECK-NEXT:    adrp x9, .LCPI5_2
124; CHECK-NEXT:    ldr q1, [x8, :lo12:.LCPI5_0]
125; CHECK-NEXT:    adrp x8, .LCPI5_1
126; CHECK-NEXT:    ldr q2, [x9, :lo12:.LCPI5_2]
127; CHECK-NEXT:    mul v0.4s, v0.4s, v1.4s
128; CHECK-NEXT:    ldr q1, [x8, :lo12:.LCPI5_1]
129; CHECK-NEXT:    adrp x8, .LCPI5_3
130; CHECK-NEXT:    ushl v1.4s, v0.4s, v1.4s
131; CHECK-NEXT:    ushl v0.4s, v0.4s, v2.4s
132; CHECK-NEXT:    movi v2.4s, #1
133; CHECK-NEXT:    orr v0.16b, v0.16b, v1.16b
134; CHECK-NEXT:    ldr q1, [x8, :lo12:.LCPI5_3]
135; CHECK-NEXT:    cmhs v0.4s, v1.4s, v0.4s
136; CHECK-NEXT:    and v0.16b, v0.16b, v2.16b
137; CHECK-NEXT:    ret
138  %urem = urem <4 x i32> %X, <i32 5, i32 14, i32 4294967295, i32 100>
139  %cmp = icmp eq <4 x i32> %urem, <i32 0, i32 0, i32 0, i32 0>
140  %ret = zext <4 x i1> %cmp to <4 x i32>
141  ret <4 x i32> %ret
142}
143define <4 x i32> @test_urem_odd_even_allones_ne(<4 x i32> %X) nounwind {
144; CHECK-LABEL: test_urem_odd_even_allones_ne:
145; CHECK:       // %bb.0:
146; CHECK-NEXT:    adrp x8, .LCPI6_0
147; CHECK-NEXT:    adrp x9, .LCPI6_2
148; CHECK-NEXT:    ldr q1, [x8, :lo12:.LCPI6_0]
149; CHECK-NEXT:    adrp x8, .LCPI6_1
150; CHECK-NEXT:    ldr q2, [x9, :lo12:.LCPI6_2]
151; CHECK-NEXT:    mul v0.4s, v0.4s, v1.4s
152; CHECK-NEXT:    ldr q1, [x8, :lo12:.LCPI6_1]
153; CHECK-NEXT:    adrp x8, .LCPI6_3
154; CHECK-NEXT:    ushl v1.4s, v0.4s, v1.4s
155; CHECK-NEXT:    ushl v0.4s, v0.4s, v2.4s
156; CHECK-NEXT:    movi v2.4s, #1
157; CHECK-NEXT:    orr v0.16b, v0.16b, v1.16b
158; CHECK-NEXT:    ldr q1, [x8, :lo12:.LCPI6_3]
159; CHECK-NEXT:    cmhi v0.4s, v0.4s, v1.4s
160; CHECK-NEXT:    and v0.16b, v0.16b, v2.16b
161; CHECK-NEXT:    ret
162  %urem = urem <4 x i32> %X, <i32 5, i32 14, i32 4294967295, i32 100>
163  %cmp = icmp ne <4 x i32> %urem, <i32 0, i32 0, i32 0, i32 0>
164  %ret = zext <4 x i1> %cmp to <4 x i32>
165  ret <4 x i32> %ret
166}
167
168;------------------------------------------------------------------------------;
169
170; One power-of-two divisor in odd divisor
171define <4 x i32> @test_urem_odd_poweroftwo(<4 x i32> %X) nounwind {
172; CHECK-LABEL: test_urem_odd_poweroftwo:
173; CHECK:       // %bb.0:
174; CHECK-NEXT:    adrp x8, .LCPI7_0
175; CHECK-NEXT:    adrp x9, .LCPI7_2
176; CHECK-NEXT:    ldr q1, [x8, :lo12:.LCPI7_0]
177; CHECK-NEXT:    adrp x8, .LCPI7_1
178; CHECK-NEXT:    ldr q2, [x9, :lo12:.LCPI7_2]
179; CHECK-NEXT:    mul v0.4s, v0.4s, v1.4s
180; CHECK-NEXT:    ldr q1, [x8, :lo12:.LCPI7_1]
181; CHECK-NEXT:    adrp x8, .LCPI7_3
182; CHECK-NEXT:    ushl v1.4s, v0.4s, v1.4s
183; CHECK-NEXT:    ushl v0.4s, v0.4s, v2.4s
184; CHECK-NEXT:    movi v2.4s, #1
185; CHECK-NEXT:    orr v0.16b, v0.16b, v1.16b
186; CHECK-NEXT:    ldr q1, [x8, :lo12:.LCPI7_3]
187; CHECK-NEXT:    cmhs v0.4s, v1.4s, v0.4s
188; CHECK-NEXT:    and v0.16b, v0.16b, v2.16b
189; CHECK-NEXT:    ret
190  %urem = urem <4 x i32> %X, <i32 5, i32 5, i32 16, i32 5>
191  %cmp = icmp eq <4 x i32> %urem, <i32 0, i32 0, i32 0, i32 0>
192  %ret = zext <4 x i1> %cmp to <4 x i32>
193  ret <4 x i32> %ret
194}
195
196; One power-of-two divisor in even divisor
197define <4 x i32> @test_urem_even_poweroftwo(<4 x i32> %X) nounwind {
198; CHECK-LABEL: test_urem_even_poweroftwo:
199; CHECK:       // %bb.0:
200; CHECK-NEXT:    adrp x8, .LCPI8_0
201; CHECK-NEXT:    adrp x9, .LCPI8_2
202; CHECK-NEXT:    ldr q1, [x8, :lo12:.LCPI8_0]
203; CHECK-NEXT:    adrp x8, .LCPI8_1
204; CHECK-NEXT:    ldr q2, [x9, :lo12:.LCPI8_2]
205; CHECK-NEXT:    mul v0.4s, v0.4s, v1.4s
206; CHECK-NEXT:    ldr q1, [x8, :lo12:.LCPI8_1]
207; CHECK-NEXT:    adrp x8, .LCPI8_3
208; CHECK-NEXT:    ushl v1.4s, v0.4s, v1.4s
209; CHECK-NEXT:    ushl v0.4s, v0.4s, v2.4s
210; CHECK-NEXT:    movi v2.4s, #1
211; CHECK-NEXT:    orr v0.16b, v0.16b, v1.16b
212; CHECK-NEXT:    ldr q1, [x8, :lo12:.LCPI8_3]
213; CHECK-NEXT:    cmhs v0.4s, v1.4s, v0.4s
214; CHECK-NEXT:    and v0.16b, v0.16b, v2.16b
215; CHECK-NEXT:    ret
216  %urem = urem <4 x i32> %X, <i32 14, i32 14, i32 16, i32 14>
217  %cmp = icmp eq <4 x i32> %urem, <i32 0, i32 0, i32 0, i32 0>
218  %ret = zext <4 x i1> %cmp to <4 x i32>
219  ret <4 x i32> %ret
220}
221
222; One power-of-two divisor in odd+even divisor
223define <4 x i32> @test_urem_odd_even_poweroftwo(<4 x i32> %X) nounwind {
224; CHECK-LABEL: test_urem_odd_even_poweroftwo:
225; CHECK:       // %bb.0:
226; CHECK-NEXT:    adrp x8, .LCPI9_0
227; CHECK-NEXT:    adrp x9, .LCPI9_2
228; CHECK-NEXT:    ldr q1, [x8, :lo12:.LCPI9_0]
229; CHECK-NEXT:    adrp x8, .LCPI9_1
230; CHECK-NEXT:    ldr q2, [x9, :lo12:.LCPI9_2]
231; CHECK-NEXT:    mul v0.4s, v0.4s, v1.4s
232; CHECK-NEXT:    ldr q1, [x8, :lo12:.LCPI9_1]
233; CHECK-NEXT:    adrp x8, .LCPI9_3
234; CHECK-NEXT:    ushl v1.4s, v0.4s, v1.4s
235; CHECK-NEXT:    ushl v0.4s, v0.4s, v2.4s
236; CHECK-NEXT:    movi v2.4s, #1
237; CHECK-NEXT:    orr v0.16b, v0.16b, v1.16b
238; CHECK-NEXT:    ldr q1, [x8, :lo12:.LCPI9_3]
239; CHECK-NEXT:    cmhs v0.4s, v1.4s, v0.4s
240; CHECK-NEXT:    and v0.16b, v0.16b, v2.16b
241; CHECK-NEXT:    ret
242  %urem = urem <4 x i32> %X, <i32 5, i32 14, i32 16, i32 100>
243  %cmp = icmp eq <4 x i32> %urem, <i32 0, i32 0, i32 0, i32 0>
244  %ret = zext <4 x i1> %cmp to <4 x i32>
245  ret <4 x i32> %ret
246}
247
248;------------------------------------------------------------------------------;
249
250; One one divisor in odd divisor
251define <4 x i32> @test_urem_odd_one(<4 x i32> %X) nounwind {
252; CHECK-LABEL: test_urem_odd_one:
253; CHECK:       // %bb.0:
254; CHECK-NEXT:    mov w8, #52429 // =0xcccd
255; CHECK-NEXT:    movi v2.4s, #1
256; CHECK-NEXT:    movk w8, #52428, lsl #16
257; CHECK-NEXT:    dup v1.4s, w8
258; CHECK-NEXT:    adrp x8, .LCPI10_0
259; CHECK-NEXT:    mul v0.4s, v0.4s, v1.4s
260; CHECK-NEXT:    ldr q1, [x8, :lo12:.LCPI10_0]
261; CHECK-NEXT:    cmhs v0.4s, v1.4s, v0.4s
262; CHECK-NEXT:    and v0.16b, v0.16b, v2.16b
263; CHECK-NEXT:    ret
264  %urem = urem <4 x i32> %X, <i32 5, i32 5, i32 1, i32 5>
265  %cmp = icmp eq <4 x i32> %urem, <i32 0, i32 0, i32 0, i32 0>
266  %ret = zext <4 x i1> %cmp to <4 x i32>
267  ret <4 x i32> %ret
268}
269
270; One one divisor in even divisor
271define <4 x i32> @test_urem_even_one(<4 x i32> %X) nounwind {
272; CHECK-LABEL: test_urem_even_one:
273; CHECK:       // %bb.0:
274; CHECK-NEXT:    mov w8, #28087 // =0x6db7
275; CHECK-NEXT:    movi v2.4s, #1
276; CHECK-NEXT:    movk w8, #46811, lsl #16
277; CHECK-NEXT:    dup v1.4s, w8
278; CHECK-NEXT:    adrp x8, .LCPI11_0
279; CHECK-NEXT:    mul v0.4s, v0.4s, v1.4s
280; CHECK-NEXT:    shl v1.4s, v0.4s, #31
281; CHECK-NEXT:    usra v1.4s, v0.4s, #1
282; CHECK-NEXT:    ldr q0, [x8, :lo12:.LCPI11_0]
283; CHECK-NEXT:    cmhs v0.4s, v0.4s, v1.4s
284; CHECK-NEXT:    and v0.16b, v0.16b, v2.16b
285; CHECK-NEXT:    ret
286  %urem = urem <4 x i32> %X, <i32 14, i32 14, i32 1, i32 14>
287  %cmp = icmp eq <4 x i32> %urem, <i32 0, i32 0, i32 0, i32 0>
288  %ret = zext <4 x i1> %cmp to <4 x i32>
289  ret <4 x i32> %ret
290}
291
292; One one divisor in odd+even divisor
293define <4 x i32> @test_urem_odd_even_one(<4 x i32> %X) nounwind {
294; CHECK-LABEL: test_urem_odd_even_one:
295; CHECK:       // %bb.0:
296; CHECK-NEXT:    adrp x8, .LCPI12_0
297; CHECK-NEXT:    adrp x9, .LCPI12_2
298; CHECK-NEXT:    ldr q1, [x8, :lo12:.LCPI12_0]
299; CHECK-NEXT:    adrp x8, .LCPI12_1
300; CHECK-NEXT:    ldr q2, [x9, :lo12:.LCPI12_2]
301; CHECK-NEXT:    mul v0.4s, v0.4s, v1.4s
302; CHECK-NEXT:    ldr q1, [x8, :lo12:.LCPI12_1]
303; CHECK-NEXT:    adrp x8, .LCPI12_3
304; CHECK-NEXT:    ushl v1.4s, v0.4s, v1.4s
305; CHECK-NEXT:    ushl v0.4s, v0.4s, v2.4s
306; CHECK-NEXT:    movi v2.4s, #1
307; CHECK-NEXT:    orr v0.16b, v0.16b, v1.16b
308; CHECK-NEXT:    ldr q1, [x8, :lo12:.LCPI12_3]
309; CHECK-NEXT:    cmhs v0.4s, v1.4s, v0.4s
310; CHECK-NEXT:    and v0.16b, v0.16b, v2.16b
311; CHECK-NEXT:    ret
312  %urem = urem <4 x i32> %X, <i32 5, i32 14, i32 1, i32 100>
313  %cmp = icmp eq <4 x i32> %urem, <i32 0, i32 0, i32 0, i32 0>
314  %ret = zext <4 x i1> %cmp to <4 x i32>
315  ret <4 x i32> %ret
316}
317
318;------------------------------------------------------------------------------;
319
320; One INT_MIN divisor in odd divisor
321define <4 x i32> @test_urem_odd_INT_MIN(<4 x i32> %X) nounwind {
322; CHECK-LABEL: test_urem_odd_INT_MIN:
323; CHECK:       // %bb.0:
324; CHECK-NEXT:    adrp x8, .LCPI13_0
325; CHECK-NEXT:    adrp x9, .LCPI13_2
326; CHECK-NEXT:    ldr q1, [x8, :lo12:.LCPI13_0]
327; CHECK-NEXT:    adrp x8, .LCPI13_1
328; CHECK-NEXT:    ldr q2, [x9, :lo12:.LCPI13_2]
329; CHECK-NEXT:    mul v0.4s, v0.4s, v1.4s
330; CHECK-NEXT:    ldr q1, [x8, :lo12:.LCPI13_1]
331; CHECK-NEXT:    adrp x8, .LCPI13_3
332; CHECK-NEXT:    ushl v1.4s, v0.4s, v1.4s
333; CHECK-NEXT:    ushl v0.4s, v0.4s, v2.4s
334; CHECK-NEXT:    movi v2.4s, #1
335; CHECK-NEXT:    orr v0.16b, v0.16b, v1.16b
336; CHECK-NEXT:    ldr q1, [x8, :lo12:.LCPI13_3]
337; CHECK-NEXT:    cmhs v0.4s, v1.4s, v0.4s
338; CHECK-NEXT:    and v0.16b, v0.16b, v2.16b
339; CHECK-NEXT:    ret
340  %urem = urem <4 x i32> %X, <i32 5, i32 5, i32 2147483648, i32 5>
341  %cmp = icmp eq <4 x i32> %urem, <i32 0, i32 0, i32 0, i32 0>
342  %ret = zext <4 x i1> %cmp to <4 x i32>
343  ret <4 x i32> %ret
344}
345
346; One INT_MIN divisor in even divisor
347define <4 x i32> @test_urem_even_INT_MIN(<4 x i32> %X) nounwind {
348; CHECK-LABEL: test_urem_even_INT_MIN:
349; CHECK:       // %bb.0:
350; CHECK-NEXT:    adrp x8, .LCPI14_0
351; CHECK-NEXT:    adrp x9, .LCPI14_2
352; CHECK-NEXT:    ldr q1, [x8, :lo12:.LCPI14_0]
353; CHECK-NEXT:    adrp x8, .LCPI14_1
354; CHECK-NEXT:    ldr q2, [x9, :lo12:.LCPI14_2]
355; CHECK-NEXT:    mul v0.4s, v0.4s, v1.4s
356; CHECK-NEXT:    ldr q1, [x8, :lo12:.LCPI14_1]
357; CHECK-NEXT:    adrp x8, .LCPI14_3
358; CHECK-NEXT:    ushl v1.4s, v0.4s, v1.4s
359; CHECK-NEXT:    ushl v0.4s, v0.4s, v2.4s
360; CHECK-NEXT:    movi v2.4s, #1
361; CHECK-NEXT:    orr v0.16b, v0.16b, v1.16b
362; CHECK-NEXT:    ldr q1, [x8, :lo12:.LCPI14_3]
363; CHECK-NEXT:    cmhs v0.4s, v1.4s, v0.4s
364; CHECK-NEXT:    and v0.16b, v0.16b, v2.16b
365; CHECK-NEXT:    ret
366  %urem = urem <4 x i32> %X, <i32 14, i32 14, i32 2147483648, i32 14>
367  %cmp = icmp eq <4 x i32> %urem, <i32 0, i32 0, i32 0, i32 0>
368  %ret = zext <4 x i1> %cmp to <4 x i32>
369  ret <4 x i32> %ret
370}
371
372; One INT_MIN divisor in odd+even divisor
373define <4 x i32> @test_urem_odd_even_INT_MIN(<4 x i32> %X) nounwind {
374; CHECK-LABEL: test_urem_odd_even_INT_MIN:
375; CHECK:       // %bb.0:
376; CHECK-NEXT:    adrp x8, .LCPI15_0
377; CHECK-NEXT:    adrp x9, .LCPI15_2
378; CHECK-NEXT:    ldr q1, [x8, :lo12:.LCPI15_0]
379; CHECK-NEXT:    adrp x8, .LCPI15_1
380; CHECK-NEXT:    ldr q2, [x9, :lo12:.LCPI15_2]
381; CHECK-NEXT:    mul v0.4s, v0.4s, v1.4s
382; CHECK-NEXT:    ldr q1, [x8, :lo12:.LCPI15_1]
383; CHECK-NEXT:    adrp x8, .LCPI15_3
384; CHECK-NEXT:    ushl v1.4s, v0.4s, v1.4s
385; CHECK-NEXT:    ushl v0.4s, v0.4s, v2.4s
386; CHECK-NEXT:    movi v2.4s, #1
387; CHECK-NEXT:    orr v0.16b, v0.16b, v1.16b
388; CHECK-NEXT:    ldr q1, [x8, :lo12:.LCPI15_3]
389; CHECK-NEXT:    cmhs v0.4s, v1.4s, v0.4s
390; CHECK-NEXT:    and v0.16b, v0.16b, v2.16b
391; CHECK-NEXT:    ret
392  %urem = urem <4 x i32> %X, <i32 5, i32 14, i32 2147483648, i32 100>
393  %cmp = icmp eq <4 x i32> %urem, <i32 0, i32 0, i32 0, i32 0>
394  %ret = zext <4 x i1> %cmp to <4 x i32>
395  ret <4 x i32> %ret
396}
397
398;==============================================================================;
399
400; One all-ones divisor and power-of-two divisor divisor in odd divisor
401define <4 x i32> @test_urem_odd_allones_and_poweroftwo(<4 x i32> %X) nounwind {
402; CHECK-LABEL: test_urem_odd_allones_and_poweroftwo:
403; CHECK:       // %bb.0:
404; CHECK-NEXT:    adrp x8, .LCPI16_0
405; CHECK-NEXT:    adrp x9, .LCPI16_2
406; CHECK-NEXT:    ldr q1, [x8, :lo12:.LCPI16_0]
407; CHECK-NEXT:    adrp x8, .LCPI16_1
408; CHECK-NEXT:    ldr q2, [x9, :lo12:.LCPI16_2]
409; CHECK-NEXT:    mul v0.4s, v0.4s, v1.4s
410; CHECK-NEXT:    ldr q1, [x8, :lo12:.LCPI16_1]
411; CHECK-NEXT:    adrp x8, .LCPI16_3
412; CHECK-NEXT:    ushl v1.4s, v0.4s, v1.4s
413; CHECK-NEXT:    ushl v0.4s, v0.4s, v2.4s
414; CHECK-NEXT:    movi v2.4s, #1
415; CHECK-NEXT:    orr v0.16b, v0.16b, v1.16b
416; CHECK-NEXT:    ldr q1, [x8, :lo12:.LCPI16_3]
417; CHECK-NEXT:    cmhs v0.4s, v1.4s, v0.4s
418; CHECK-NEXT:    and v0.16b, v0.16b, v2.16b
419; CHECK-NEXT:    ret
420  %urem = urem <4 x i32> %X, <i32 5, i32 4294967295, i32 16, i32 5>
421  %cmp = icmp eq <4 x i32> %urem, <i32 0, i32 0, i32 0, i32 0>
422  %ret = zext <4 x i1> %cmp to <4 x i32>
423  ret <4 x i32> %ret
424}
425
426; One all-ones divisor and power-of-two divisor divisor in even divisor
427define <4 x i32> @test_urem_even_allones_and_poweroftwo(<4 x i32> %X) nounwind {
428; CHECK-LABEL: test_urem_even_allones_and_poweroftwo:
429; CHECK:       // %bb.0:
430; CHECK-NEXT:    adrp x8, .LCPI17_0
431; CHECK-NEXT:    adrp x9, .LCPI17_2
432; CHECK-NEXT:    ldr q1, [x8, :lo12:.LCPI17_0]
433; CHECK-NEXT:    adrp x8, .LCPI17_1
434; CHECK-NEXT:    ldr q2, [x9, :lo12:.LCPI17_2]
435; CHECK-NEXT:    mul v0.4s, v0.4s, v1.4s
436; CHECK-NEXT:    ldr q1, [x8, :lo12:.LCPI17_1]
437; CHECK-NEXT:    adrp x8, .LCPI17_3
438; CHECK-NEXT:    ushl v1.4s, v0.4s, v1.4s
439; CHECK-NEXT:    ushl v0.4s, v0.4s, v2.4s
440; CHECK-NEXT:    movi v2.4s, #1
441; CHECK-NEXT:    orr v0.16b, v0.16b, v1.16b
442; CHECK-NEXT:    ldr q1, [x8, :lo12:.LCPI17_3]
443; CHECK-NEXT:    cmhs v0.4s, v1.4s, v0.4s
444; CHECK-NEXT:    and v0.16b, v0.16b, v2.16b
445; CHECK-NEXT:    ret
446  %urem = urem <4 x i32> %X, <i32 14, i32 4294967295, i32 16, i32 14>
447  %cmp = icmp eq <4 x i32> %urem, <i32 0, i32 0, i32 0, i32 0>
448  %ret = zext <4 x i1> %cmp to <4 x i32>
449  ret <4 x i32> %ret
450}
451
452; One all-ones divisor and power-of-two divisor divisor in odd+even divisor
453define <4 x i32> @test_urem_odd_even_allones_and_poweroftwo(<4 x i32> %X) nounwind {
454; CHECK-LABEL: test_urem_odd_even_allones_and_poweroftwo:
455; CHECK:       // %bb.0:
456; CHECK-NEXT:    adrp x8, .LCPI18_0
457; CHECK-NEXT:    adrp x9, .LCPI18_2
458; CHECK-NEXT:    ldr q1, [x8, :lo12:.LCPI18_0]
459; CHECK-NEXT:    adrp x8, .LCPI18_1
460; CHECK-NEXT:    ldr q2, [x9, :lo12:.LCPI18_2]
461; CHECK-NEXT:    mul v0.4s, v0.4s, v1.4s
462; CHECK-NEXT:    ldr q1, [x8, :lo12:.LCPI18_1]
463; CHECK-NEXT:    adrp x8, .LCPI18_3
464; CHECK-NEXT:    ushl v1.4s, v0.4s, v1.4s
465; CHECK-NEXT:    ushl v0.4s, v0.4s, v2.4s
466; CHECK-NEXT:    movi v2.4s, #1
467; CHECK-NEXT:    orr v0.16b, v0.16b, v1.16b
468; CHECK-NEXT:    ldr q1, [x8, :lo12:.LCPI18_3]
469; CHECK-NEXT:    cmhs v0.4s, v1.4s, v0.4s
470; CHECK-NEXT:    and v0.16b, v0.16b, v2.16b
471; CHECK-NEXT:    ret
472  %urem = urem <4 x i32> %X, <i32 5, i32 4294967295, i32 16, i32 100>
473  %cmp = icmp eq <4 x i32> %urem, <i32 0, i32 0, i32 0, i32 0>
474  %ret = zext <4 x i1> %cmp to <4 x i32>
475  ret <4 x i32> %ret
476}
477
478;------------------------------------------------------------------------------;
479
480; One all-ones divisor and one one divisor in odd divisor
481define <4 x i32> @test_urem_odd_allones_and_one(<4 x i32> %X) nounwind {
482; CHECK-LABEL: test_urem_odd_allones_and_one:
483; CHECK:       // %bb.0:
484; CHECK-NEXT:    adrp x8, .LCPI19_0
485; CHECK-NEXT:    movi v2.4s, #1
486; CHECK-NEXT:    ldr q1, [x8, :lo12:.LCPI19_0]
487; CHECK-NEXT:    adrp x8, .LCPI19_1
488; CHECK-NEXT:    mul v0.4s, v0.4s, v1.4s
489; CHECK-NEXT:    ldr q1, [x8, :lo12:.LCPI19_1]
490; CHECK-NEXT:    cmhs v0.4s, v1.4s, v0.4s
491; CHECK-NEXT:    and v0.16b, v0.16b, v2.16b
492; CHECK-NEXT:    ret
493  %urem = urem <4 x i32> %X, <i32 5, i32 4294967295, i32 1, i32 5>
494  %cmp = icmp eq <4 x i32> %urem, <i32 0, i32 0, i32 0, i32 0>
495  %ret = zext <4 x i1> %cmp to <4 x i32>
496  ret <4 x i32> %ret
497}
498
499; One all-ones divisor and one one divisor in even divisor
500define <4 x i32> @test_urem_even_allones_and_one(<4 x i32> %X) nounwind {
501; CHECK-LABEL: test_urem_even_allones_and_one:
502; CHECK:       // %bb.0:
503; CHECK-NEXT:    adrp x8, .LCPI20_0
504; CHECK-NEXT:    adrp x9, .LCPI20_2
505; CHECK-NEXT:    ldr q1, [x8, :lo12:.LCPI20_0]
506; CHECK-NEXT:    adrp x8, .LCPI20_1
507; CHECK-NEXT:    ldr q2, [x9, :lo12:.LCPI20_2]
508; CHECK-NEXT:    mul v0.4s, v0.4s, v1.4s
509; CHECK-NEXT:    ldr q1, [x8, :lo12:.LCPI20_1]
510; CHECK-NEXT:    adrp x8, .LCPI20_3
511; CHECK-NEXT:    ushl v1.4s, v0.4s, v1.4s
512; CHECK-NEXT:    ushl v0.4s, v0.4s, v2.4s
513; CHECK-NEXT:    movi v2.4s, #1
514; CHECK-NEXT:    orr v0.16b, v0.16b, v1.16b
515; CHECK-NEXT:    ldr q1, [x8, :lo12:.LCPI20_3]
516; CHECK-NEXT:    cmhs v0.4s, v1.4s, v0.4s
517; CHECK-NEXT:    and v0.16b, v0.16b, v2.16b
518; CHECK-NEXT:    ret
519  %urem = urem <4 x i32> %X, <i32 14, i32 4294967295, i32 1, i32 14>
520  %cmp = icmp eq <4 x i32> %urem, <i32 0, i32 0, i32 0, i32 0>
521  %ret = zext <4 x i1> %cmp to <4 x i32>
522  ret <4 x i32> %ret
523}
524
525; One all-ones divisor and one one divisor in odd+even divisor
526define <4 x i32> @test_urem_odd_even_allones_and_one(<4 x i32> %X) nounwind {
527; CHECK-LABEL: test_urem_odd_even_allones_and_one:
528; CHECK:       // %bb.0:
529; CHECK-NEXT:    adrp x8, .LCPI21_0
530; CHECK-NEXT:    adrp x9, .LCPI21_2
531; CHECK-NEXT:    ldr q1, [x8, :lo12:.LCPI21_0]
532; CHECK-NEXT:    adrp x8, .LCPI21_1
533; CHECK-NEXT:    ldr q2, [x9, :lo12:.LCPI21_2]
534; CHECK-NEXT:    mul v0.4s, v0.4s, v1.4s
535; CHECK-NEXT:    ldr q1, [x8, :lo12:.LCPI21_1]
536; CHECK-NEXT:    adrp x8, .LCPI21_3
537; CHECK-NEXT:    ushl v1.4s, v0.4s, v1.4s
538; CHECK-NEXT:    ushl v0.4s, v0.4s, v2.4s
539; CHECK-NEXT:    movi v2.4s, #1
540; CHECK-NEXT:    orr v0.16b, v0.16b, v1.16b
541; CHECK-NEXT:    ldr q1, [x8, :lo12:.LCPI21_3]
542; CHECK-NEXT:    cmhs v0.4s, v1.4s, v0.4s
543; CHECK-NEXT:    and v0.16b, v0.16b, v2.16b
544; CHECK-NEXT:    ret
545  %urem = urem <4 x i32> %X, <i32 5, i32 4294967295, i32 1, i32 100>
546  %cmp = icmp eq <4 x i32> %urem, <i32 0, i32 0, i32 0, i32 0>
547  %ret = zext <4 x i1> %cmp to <4 x i32>
548  ret <4 x i32> %ret
549}
550
551;------------------------------------------------------------------------------;
552
553; One power-of-two divisor divisor and one divisor in odd divisor
554define <4 x i32> @test_urem_odd_poweroftwo_and_one(<4 x i32> %X) nounwind {
555; CHECK-LABEL: test_urem_odd_poweroftwo_and_one:
556; CHECK:       // %bb.0:
557; CHECK-NEXT:    adrp x8, .LCPI22_0
558; CHECK-NEXT:    adrp x9, .LCPI22_2
559; CHECK-NEXT:    ldr q1, [x8, :lo12:.LCPI22_0]
560; CHECK-NEXT:    adrp x8, .LCPI22_1
561; CHECK-NEXT:    ldr q2, [x9, :lo12:.LCPI22_2]
562; CHECK-NEXT:    mul v0.4s, v0.4s, v1.4s
563; CHECK-NEXT:    ldr q1, [x8, :lo12:.LCPI22_1]
564; CHECK-NEXT:    adrp x8, .LCPI22_3
565; CHECK-NEXT:    ushl v1.4s, v0.4s, v1.4s
566; CHECK-NEXT:    ushl v0.4s, v0.4s, v2.4s
567; CHECK-NEXT:    movi v2.4s, #1
568; CHECK-NEXT:    orr v0.16b, v0.16b, v1.16b
569; CHECK-NEXT:    ldr q1, [x8, :lo12:.LCPI22_3]
570; CHECK-NEXT:    cmhs v0.4s, v1.4s, v0.4s
571; CHECK-NEXT:    and v0.16b, v0.16b, v2.16b
572; CHECK-NEXT:    ret
573  %urem = urem <4 x i32> %X, <i32 5, i32 16, i32 1, i32 5>
574  %cmp = icmp eq <4 x i32> %urem, <i32 0, i32 0, i32 0, i32 0>
575  %ret = zext <4 x i1> %cmp to <4 x i32>
576  ret <4 x i32> %ret
577}
578
579; One power-of-two divisor divisor and one divisor in even divisor
580define <4 x i32> @test_urem_even_poweroftwo_and_one(<4 x i32> %X) nounwind {
581; CHECK-LABEL: test_urem_even_poweroftwo_and_one:
582; CHECK:       // %bb.0:
583; CHECK-NEXT:    adrp x8, .LCPI23_0
584; CHECK-NEXT:    adrp x9, .LCPI23_2
585; CHECK-NEXT:    ldr q1, [x8, :lo12:.LCPI23_0]
586; CHECK-NEXT:    adrp x8, .LCPI23_1
587; CHECK-NEXT:    ldr q2, [x9, :lo12:.LCPI23_2]
588; CHECK-NEXT:    mul v0.4s, v0.4s, v1.4s
589; CHECK-NEXT:    ldr q1, [x8, :lo12:.LCPI23_1]
590; CHECK-NEXT:    adrp x8, .LCPI23_3
591; CHECK-NEXT:    ushl v1.4s, v0.4s, v1.4s
592; CHECK-NEXT:    ushl v0.4s, v0.4s, v2.4s
593; CHECK-NEXT:    movi v2.4s, #1
594; CHECK-NEXT:    orr v0.16b, v0.16b, v1.16b
595; CHECK-NEXT:    ldr q1, [x8, :lo12:.LCPI23_3]
596; CHECK-NEXT:    cmhs v0.4s, v1.4s, v0.4s
597; CHECK-NEXT:    and v0.16b, v0.16b, v2.16b
598; CHECK-NEXT:    ret
599  %urem = urem <4 x i32> %X, <i32 14, i32 16, i32 1, i32 14>
600  %cmp = icmp eq <4 x i32> %urem, <i32 0, i32 0, i32 0, i32 0>
601  %ret = zext <4 x i1> %cmp to <4 x i32>
602  ret <4 x i32> %ret
603}
604
605; One power-of-two divisor divisor and one divisor in odd+even divisor
606define <4 x i32> @test_urem_odd_even_poweroftwo_and_one(<4 x i32> %X) nounwind {
607; CHECK-LABEL: test_urem_odd_even_poweroftwo_and_one:
608; CHECK:       // %bb.0:
609; CHECK-NEXT:    adrp x8, .LCPI24_0
610; CHECK-NEXT:    adrp x9, .LCPI24_2
611; CHECK-NEXT:    ldr q1, [x8, :lo12:.LCPI24_0]
612; CHECK-NEXT:    adrp x8, .LCPI24_1
613; CHECK-NEXT:    ldr q2, [x9, :lo12:.LCPI24_2]
614; CHECK-NEXT:    mul v0.4s, v0.4s, v1.4s
615; CHECK-NEXT:    ldr q1, [x8, :lo12:.LCPI24_1]
616; CHECK-NEXT:    adrp x8, .LCPI24_3
617; CHECK-NEXT:    ushl v1.4s, v0.4s, v1.4s
618; CHECK-NEXT:    ushl v0.4s, v0.4s, v2.4s
619; CHECK-NEXT:    movi v2.4s, #1
620; CHECK-NEXT:    orr v0.16b, v0.16b, v1.16b
621; CHECK-NEXT:    ldr q1, [x8, :lo12:.LCPI24_3]
622; CHECK-NEXT:    cmhs v0.4s, v1.4s, v0.4s
623; CHECK-NEXT:    and v0.16b, v0.16b, v2.16b
624; CHECK-NEXT:    ret
625  %urem = urem <4 x i32> %X, <i32 5, i32 16, i32 1, i32 100>
626  %cmp = icmp eq <4 x i32> %urem, <i32 0, i32 0, i32 0, i32 0>
627  %ret = zext <4 x i1> %cmp to <4 x i32>
628  ret <4 x i32> %ret
629}
630
631;------------------------------------------------------------------------------;
632
633define <4 x i32> @test_urem_odd_allones_and_poweroftwo_and_one(<4 x i32> %X) nounwind {
634; CHECK-LABEL: test_urem_odd_allones_and_poweroftwo_and_one:
635; CHECK:       // %bb.0:
636; CHECK-NEXT:    adrp x8, .LCPI25_0
637; CHECK-NEXT:    adrp x9, .LCPI25_2
638; CHECK-NEXT:    ldr q1, [x8, :lo12:.LCPI25_0]
639; CHECK-NEXT:    adrp x8, .LCPI25_1
640; CHECK-NEXT:    ldr q2, [x9, :lo12:.LCPI25_2]
641; CHECK-NEXT:    mul v0.4s, v0.4s, v1.4s
642; CHECK-NEXT:    ldr q1, [x8, :lo12:.LCPI25_1]
643; CHECK-NEXT:    adrp x8, .LCPI25_3
644; CHECK-NEXT:    ushl v1.4s, v0.4s, v1.4s
645; CHECK-NEXT:    ushl v0.4s, v0.4s, v2.4s
646; CHECK-NEXT:    movi v2.4s, #1
647; CHECK-NEXT:    orr v0.16b, v0.16b, v1.16b
648; CHECK-NEXT:    ldr q1, [x8, :lo12:.LCPI25_3]
649; CHECK-NEXT:    cmhs v0.4s, v1.4s, v0.4s
650; CHECK-NEXT:    and v0.16b, v0.16b, v2.16b
651; CHECK-NEXT:    ret
652  %urem = urem <4 x i32> %X, <i32 5, i32 4294967295, i32 16, i32 1>
653  %cmp = icmp eq <4 x i32> %urem, <i32 0, i32 0, i32 0, i32 0>
654  %ret = zext <4 x i1> %cmp to <4 x i32>
655  ret <4 x i32> %ret
656}
657
658define <4 x i32> @test_urem_even_allones_and_poweroftwo_and_one(<4 x i32> %X) nounwind {
659; CHECK-LABEL: test_urem_even_allones_and_poweroftwo_and_one:
660; CHECK:       // %bb.0:
661; CHECK-NEXT:    adrp x8, .LCPI26_0
662; CHECK-NEXT:    adrp x9, .LCPI26_2
663; CHECK-NEXT:    ldr q1, [x8, :lo12:.LCPI26_0]
664; CHECK-NEXT:    adrp x8, .LCPI26_1
665; CHECK-NEXT:    ldr q2, [x9, :lo12:.LCPI26_2]
666; CHECK-NEXT:    mul v0.4s, v0.4s, v1.4s
667; CHECK-NEXT:    ldr q1, [x8, :lo12:.LCPI26_1]
668; CHECK-NEXT:    adrp x8, .LCPI26_3
669; CHECK-NEXT:    ushl v1.4s, v0.4s, v1.4s
670; CHECK-NEXT:    ushl v0.4s, v0.4s, v2.4s
671; CHECK-NEXT:    movi v2.4s, #1
672; CHECK-NEXT:    orr v0.16b, v0.16b, v1.16b
673; CHECK-NEXT:    ldr q1, [x8, :lo12:.LCPI26_3]
674; CHECK-NEXT:    cmhs v0.4s, v1.4s, v0.4s
675; CHECK-NEXT:    and v0.16b, v0.16b, v2.16b
676; CHECK-NEXT:    ret
677  %urem = urem <4 x i32> %X, <i32 14, i32 4294967295, i32 16, i32 1>
678  %cmp = icmp eq <4 x i32> %urem, <i32 0, i32 0, i32 0, i32 0>
679  %ret = zext <4 x i1> %cmp to <4 x i32>
680  ret <4 x i32> %ret
681}
682