1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc -mtriple=aarch64-unknown-linux-gnu < %s | FileCheck %s 3 4define i1 @test_urem_odd(i13 %X) nounwind { 5; CHECK-LABEL: test_urem_odd: 6; CHECK: // %bb.0: 7; CHECK-NEXT: mov w8, #3277 // =0xccd 8; CHECK-NEXT: mul w8, w0, w8 9; CHECK-NEXT: and w8, w8, #0x1fff 10; CHECK-NEXT: cmp w8, #1639 11; CHECK-NEXT: cset w0, lo 12; CHECK-NEXT: ret 13 %urem = urem i13 %X, 5 14 %cmp = icmp eq i13 %urem, 0 15 ret i1 %cmp 16} 17 18define i1 @test_urem_even(i27 %X) nounwind { 19; CHECK-LABEL: test_urem_even: 20; CHECK: // %bb.0: 21; CHECK-NEXT: mov w8, #28087 // =0x6db7 22; CHECK-NEXT: movk w8, #1755, lsl #16 23; CHECK-NEXT: mul w8, w0, w8 24; CHECK-NEXT: lsl w9, w8, #26 25; CHECK-NEXT: bfxil w9, w8, #1, #26 26; CHECK-NEXT: and w8, w9, #0x7ffffff 27; CHECK-NEXT: mov w9, #18725 // =0x4925 28; CHECK-NEXT: movk w9, #146, lsl #16 29; CHECK-NEXT: cmp w8, w9 30; CHECK-NEXT: cset w0, lo 31; CHECK-NEXT: ret 32 %urem = urem i27 %X, 14 33 %cmp = icmp eq i27 %urem, 0 34 ret i1 %cmp 35} 36 37define i1 @test_urem_odd_setne(i4 %X) nounwind { 38; CHECK-LABEL: test_urem_odd_setne: 39; CHECK: // %bb.0: 40; CHECK-NEXT: mov w8, #13 // =0xd 41; CHECK-NEXT: mul w8, w0, w8 42; CHECK-NEXT: and w8, w8, #0xf 43; CHECK-NEXT: cmp w8, #3 44; CHECK-NEXT: cset w0, hi 45; CHECK-NEXT: ret 46 %urem = urem i4 %X, 5 47 %cmp = icmp ne i4 %urem, 0 48 ret i1 %cmp 49} 50 51define i1 @test_urem_negative_odd(i9 %X) nounwind { 52; CHECK-LABEL: test_urem_negative_odd: 53; CHECK: // %bb.0: 54; CHECK-NEXT: mov w8, #307 // =0x133 55; CHECK-NEXT: mul w8, w0, w8 56; CHECK-NEXT: and w8, w8, #0x1ff 57; CHECK-NEXT: cmp w8, #1 58; CHECK-NEXT: cset w0, hi 59; CHECK-NEXT: ret 60 %urem = urem i9 %X, -5 61 %cmp = icmp ne i9 %urem, 0 62 ret i1 %cmp 63} 64 65define <3 x i1> @test_urem_vec(<3 x i11> %X) nounwind { 66; CHECK-LABEL: test_urem_vec: 67; CHECK: // %bb.0: 68; CHECK-NEXT: fmov s0, w0 69; CHECK-NEXT: adrp x8, .LCPI4_0 70; CHECK-NEXT: ldr d1, [x8, :lo12:.LCPI4_0] 71; CHECK-NEXT: adrp x8, .LCPI4_1 72; CHECK-NEXT: mov v0.h[1], w1 73; CHECK-NEXT: mov v0.h[2], w2 74; CHECK-NEXT: sub v0.4h, v0.4h, v1.4h 75; CHECK-NEXT: ldr d1, [x8, :lo12:.LCPI4_1] 76; CHECK-NEXT: adrp x8, .LCPI4_2 77; CHECK-NEXT: ldr d3, [x8, :lo12:.LCPI4_2] 78; CHECK-NEXT: adrp x8, .LCPI4_3 79; CHECK-NEXT: mul v0.4h, v0.4h, v1.4h 80; CHECK-NEXT: movi d1, #0x0000000000ffff 81; CHECK-NEXT: add v2.4h, v0.4h, v0.4h 82; CHECK-NEXT: bic v0.4h, #248, lsl #8 83; CHECK-NEXT: ushl v2.4h, v2.4h, v3.4h 84; CHECK-NEXT: ushl v0.4h, v0.4h, v1.4h 85; CHECK-NEXT: ldr d1, [x8, :lo12:.LCPI4_3] 86; CHECK-NEXT: orr v0.8b, v0.8b, v2.8b 87; CHECK-NEXT: bic v0.4h, #248, lsl #8 88; CHECK-NEXT: cmhi v0.4h, v0.4h, v1.4h 89; CHECK-NEXT: umov w0, v0.h[0] 90; CHECK-NEXT: umov w1, v0.h[1] 91; CHECK-NEXT: umov w2, v0.h[2] 92; CHECK-NEXT: ret 93 %urem = urem <3 x i11> %X, <i11 6, i11 7, i11 -5> 94 %cmp = icmp ne <3 x i11> %urem, <i11 0, i11 1, i11 2> 95 ret <3 x i1> %cmp 96} 97