xref: /llvm-project/llvm/test/CodeGen/AArch64/typepromotion-signed.ll (revision db158c7c830807caeeb0691739c41f1d522029e9) 
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple=aarch64 %s -o - | FileCheck %s
3
4define i16 @test_signed_load(ptr nocapture readonly %ptr) {
5; CHECK-LABEL: test_signed_load:
6; CHECK:       // %bb.0:
7; CHECK-NEXT:    ldrsh w8, [x0]
8; CHECK-NEXT:    tst w8, #0xffff0000
9; CHECK-NEXT:    cset w0, eq
10; CHECK-NEXT:    ret
11  %load = load i16, ptr %ptr, align 2
12  %conv0 = zext i16 %load to i32
13  %conv1 = sext i16 %load to i32
14  %cmp = icmp eq i32 %conv0, %conv1
15  %conv2 = zext i1 %cmp to i16
16  ret i16 %conv2
17}
18
19define i16 @test_ashr(i16 zeroext %arg) local_unnamed_addr #1 {
20; CHECK-LABEL: test_ashr:
21; CHECK:       // %bb.0:
22; CHECK-NEXT:    cmp w0, #2
23; CHECK-NEXT:    cset w0, lo
24; CHECK-NEXT:    ret
25  %cmp = icmp ult i16 %arg, 2
26  %conv = zext i1 %cmp to i16
27  ret i16 %conv
28}
29
30define i16 @test_sdiv(i16 zeroext %arg) local_unnamed_addr #1 {
31; CHECK-LABEL: test_sdiv:
32; CHECK:       // %bb.0:
33; CHECK-NEXT:    add w8, w0, #1
34; CHECK-NEXT:    and w8, w8, #0xffff
35; CHECK-NEXT:    cmp w8, #2
36; CHECK-NEXT:    cset w0, hi
37; CHECK-NEXT:    ret
38  %arg.off = add i16 %arg, 1
39  %1 = icmp ugt i16 %arg.off, 2
40  %conv = zext i1 %1 to i16
41  ret i16 %conv
42}
43
44define i16 @test_srem(i16 zeroext %arg) local_unnamed_addr #1 {
45; CHECK-LABEL: test_srem:
46; CHECK:       // %bb.0:
47; CHECK-NEXT:    tst w0, #0x3
48; CHECK-NEXT:    cset w0, ne
49; CHECK-NEXT:    ret
50  %1 = and i16 %arg, 3
51  %cmp = icmp ne i16 %1, 0
52  %conv = zext i1 %cmp to i16
53  ret i16 %conv
54}
55
56define i32 @test_signext_b(ptr nocapture readonly %ptr, i8 signext %arg) {
57; CHECK-LABEL: test_signext_b:
58; CHECK:       // %bb.0: // %entry
59; CHECK-NEXT:    ldrb w9, [x0]
60; CHECK-NEXT:    mov w8, #20894 // =0x519e
61; CHECK-NEXT:    add w9, w9, w1
62; CHECK-NEXT:    sxtb w9, w9
63; CHECK-NEXT:    cmp w9, #0
64; CHECK-NEXT:    mov w9, #42 // =0x2a
65; CHECK-NEXT:    csel w0, w9, w8, ge
66; CHECK-NEXT:    ret
67entry:
68  %0 = load i8, ptr %ptr, align 1
69  %1 = add nuw nsw i8 %0, %arg
70  %cmp = icmp sgt i8 %1, -1
71  %res = select i1 %cmp, i32 42, i32 20894
72  ret i32 %res
73}
74
75define i32 @test_signext_b_ult_slt(ptr nocapture readonly %ptr, i8 signext %arg) {
76; CHECK-LABEL: test_signext_b_ult_slt:
77; CHECK:       // %bb.0: // %entry
78; CHECK-NEXT:    ldrb w9, [x0]
79; CHECK-NEXT:    mov w8, #57 // =0x39
80; CHECK-NEXT:    add w10, w9, w1, uxtb
81; CHECK-NEXT:    cmp w10, #127
82; CHECK-NEXT:    ccmp w9, #0, #0, ne
83; CHECK-NEXT:    mov w9, #42 // =0x2a
84; CHECK-NEXT:    csel w0, w9, w8, eq
85; CHECK-NEXT:    ret
86entry:
87  %0 = load i8, ptr %ptr, align 1
88  %1 = add nuw nsw i8 %0, %arg
89  %cmp = icmp ne i8 %1, 127
90  %cmp.1 = icmp eq i8 %0, 0
91  %or = and i1 %cmp.1, %cmp
92  %res = select i1 %or, i32 42, i32 57
93  ret i32 %res
94}
95
96define i32 @test_signext_h(ptr nocapture readonly %ptr, i16 signext %arg) {
97; CHECK-LABEL: test_signext_h:
98; CHECK:       // %bb.0: // %entry
99; CHECK-NEXT:    ldrh w9, [x0]
100; CHECK-NEXT:    mov w8, #20894 // =0x519e
101; CHECK-NEXT:    add w9, w9, w1
102; CHECK-NEXT:    sxth w9, w9
103; CHECK-NEXT:    cmp w9, #0
104; CHECK-NEXT:    mov w9, #42 // =0x2a
105; CHECK-NEXT:    csel w0, w9, w8, ge
106; CHECK-NEXT:    ret
107entry:
108  %0 = load i16, ptr %ptr, align 1
109  %1 = add nuw nsw i16 %0, %arg
110  %cmp = icmp sgt i16 %1, -1
111  %res = select i1 %cmp, i32 42, i32 20894
112  ret i32 %res
113}
114