1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc -verify-machineinstrs -o - %s -mtriple=arm64-apple-ios7.0 -aarch64-enable-atomic-cfg-tidy=0 | FileCheck %s 3 4; We've got the usual issues with LLVM reordering blocks here. The 5; tests are correct for the current order, but who knows when that 6; will change. Beware! 7@var32 = global i32 0 8@var64 = global i64 0 9 10define i32 @test_tbz() { 11; CHECK-LABEL: test_tbz: 12; CHECK: ; %bb.0: 13; CHECK-NEXT: Lloh0: 14; CHECK-NEXT: adrp x8, _var32@PAGE 15; CHECK-NEXT: Lloh1: 16; CHECK-NEXT: ldr w8, [x8, _var32@PAGEOFF] 17; CHECK-NEXT: tbz w8, #15, LBB0_5 18; CHECK-NEXT: ; %bb.1: ; %test1 19; CHECK-NEXT: tbz w8, #12, LBB0_5 20; CHECK-NEXT: ; %bb.2: ; %test2 21; CHECK-NEXT: Lloh2: 22; CHECK-NEXT: adrp x8, _var64@PAGE 23; CHECK-NEXT: Lloh3: 24; CHECK-NEXT: ldr x8, [x8, _var64@PAGEOFF] 25; CHECK-NEXT: tbz w8, #15, LBB0_5 26; CHECK-NEXT: ; %bb.3: ; %test3 27; CHECK-NEXT: tbz w8, #12, LBB0_5 28; CHECK-NEXT: ; %bb.4: ; %end2 29; CHECK-NEXT: mov w0, #1 30; CHECK-NEXT: ret 31; CHECK-NEXT: LBB0_5: ; %end1 32; CHECK-NEXT: mov w0, wzr 33; CHECK-NEXT: ret 34; CHECK-NEXT: .loh AdrpLdr Lloh0, Lloh1 35; CHECK-NEXT: .loh AdrpLdr Lloh2, Lloh3 36 37 %val = load i32, ptr @var32 38 %val64 = load i64, ptr @var64 39 40 %tbit0 = and i32 %val, 32768 41 %tst0 = icmp ne i32 %tbit0, 0 42 br i1 %tst0, label %test1, label %end1 43 44test1: 45 %tbit1 = and i32 %val, 4096 46 %tst1 = icmp ne i32 %tbit1, 0 47 br i1 %tst1, label %test2, label %end1 48 49test2: 50 %tbit2 = and i64 %val64, 32768 51 %tst2 = icmp ne i64 %tbit2, 0 52 br i1 %tst2, label %test3, label %end1 53 54test3: 55 %tbit3 = and i64 %val64, 4096 56 %tst3 = icmp ne i64 %tbit3, 0 57 br i1 %tst3, label %end2, label %end1 58 59end2: 60 ret i32 1 61 62end1: 63 ret i32 0 64} 65