1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2 2; RUN: llc -mtriple=aarch64--linux-gnu -mattr=+sve2p1,+bf16 < %s | FileCheck %s 3 4define <vscale x 16 x i8> @test_tblq_i8 (<vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm) { 5; CHECK-LABEL: test_tblq_i8: 6; CHECK: // %bb.0: 7; CHECK-NEXT: tblq z0.b, { z0.b }, z1.b 8; CHECK-NEXT: ret 9 %res = call <vscale x 16 x i8> @llvm.aarch64.sve.tblq.nxv16i8(<vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm) 10 ret <vscale x 16 x i8> %res 11} 12 13define <vscale x 8 x i16> @test_tblq_i16 (<vscale x 8 x i16> %zn, <vscale x 8 x i16> %zm) { 14; CHECK-LABEL: test_tblq_i16: 15; CHECK: // %bb.0: 16; CHECK-NEXT: tblq z0.h, { z0.h }, z1.h 17; CHECK-NEXT: ret 18 %res = call <vscale x 8 x i16> @llvm.aarch64.sve.tblq.nxv8i16(<vscale x 8 x i16> %zn, <vscale x 8 x i16> %zm) 19 ret <vscale x 8 x i16> %res 20} 21 22define <vscale x 4 x i32> @test_tblq_i32 (<vscale x 4 x i32> %zn, <vscale x 4 x i32> %zm) { 23; CHECK-LABEL: test_tblq_i32: 24; CHECK: // %bb.0: 25; CHECK-NEXT: tblq z0.s, { z0.s }, z1.s 26; CHECK-NEXT: ret 27 %res = call <vscale x 4 x i32> @llvm.aarch64.sve.tblq.nxv4i32(<vscale x 4 x i32> %zn, <vscale x 4 x i32> %zm) 28 ret <vscale x 4 x i32> %res 29} 30 31define <vscale x 2 x i64> @test_tblq_i64 (<vscale x 2 x i64> %zn, <vscale x 2 x i64> %zm) { 32; CHECK-LABEL: test_tblq_i64: 33; CHECK: // %bb.0: 34; CHECK-NEXT: tblq z0.d, { z0.d }, z1.d 35; CHECK-NEXT: ret 36 %res = call <vscale x 2 x i64> @llvm.aarch64.sve.tblq.nxv2i64(<vscale x 2 x i64> %zn, <vscale x 2 x i64> %zm) 37 ret <vscale x 2 x i64> %res 38} 39 40define <vscale x 8 x half> @test_tblq_f16(<vscale x 8 x half> %zn, <vscale x 8 x i16> %zm) { 41; CHECK-LABEL: test_tblq_f16: 42; CHECK: // %bb.0: 43; CHECK-NEXT: tblq z0.h, { z0.h }, z1.h 44; CHECK-NEXT: ret 45 %res = call <vscale x 8 x half> @llvm.aarch64.sve.tblq.nxv8f16(<vscale x 8 x half> %zn, <vscale x 8 x i16> %zm) 46 ret <vscale x 8 x half> %res 47} 48 49define <vscale x 4 x float> @test_tblq_f32(<vscale x 4 x float> %zn, <vscale x 4 x i32> %zm) { 50; CHECK-LABEL: test_tblq_f32: 51; CHECK: // %bb.0: 52; CHECK-NEXT: tblq z0.s, { z0.s }, z1.s 53; CHECK-NEXT: ret 54 %res = call <vscale x 4 x float> @llvm.aarch64.sve.tblq.nxv4f32(<vscale x 4 x float> %zn, <vscale x 4 x i32> %zm) 55 ret <vscale x 4 x float> %res 56} 57 58define <vscale x 2 x double> @test_tblq_f64(<vscale x 2 x double> %zn, <vscale x 2 x i64> %zm) { 59; CHECK-LABEL: test_tblq_f64: 60; CHECK: // %bb.0: 61; CHECK-NEXT: tblq z0.d, { z0.d }, z1.d 62; CHECK-NEXT: ret 63 %res = call <vscale x 2 x double> @llvm.aarch64.sve.tblq.nxv2f64(<vscale x 2 x double> %zn, <vscale x 2 x i64> %zm) 64 ret <vscale x 2 x double> %res 65} 66 67define <vscale x 8 x bfloat> @test_tblq_bf16(<vscale x 8 x bfloat> %zn, <vscale x 8 x i16> %zm) { 68; CHECK-LABEL: test_tblq_bf16: 69; CHECK: // %bb.0: 70; CHECK-NEXT: tblq z0.h, { z0.h }, z1.h 71; CHECK-NEXT: ret 72 %res = call <vscale x 8 x bfloat> @llvm.aarch64.sve.tblq.nxv8bf16(<vscale x 8 x bfloat> %zn, <vscale x 8 x i16> %zm) 73 ret <vscale x 8 x bfloat> %res 74} 75 76declare <vscale x 16 x i8> @llvm.aarch64.sve.tblq.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i8>) 77declare <vscale x 8 x i16> @llvm.aarch64.sve.tblq.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i16>) 78declare <vscale x 4 x i32> @llvm.aarch64.sve.tblq.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>) 79declare <vscale x 2 x i64> @llvm.aarch64.sve.tblq.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>) 80declare <vscale x 8 x half> @llvm.aarch64.sve.tblq.nxv8f16(<vscale x 8 x half>, <vscale x 8 x i16>) 81declare <vscale x 4 x float> @llvm.aarch64.sve.tblq.nxv4f32(<vscale x 4 x float>, <vscale x 4 x i32>) 82declare <vscale x 2 x double> @llvm.aarch64.sve.tblq.nxv2f64(<vscale x 2 x double>, <vscale x 2 x i64>) 83declare <vscale x 8 x bfloat> @llvm.aarch64.sve.tblq.nxv8bf16(<vscale x 8 x bfloat>, <vscale x 8 x i16>) 84