xref: /llvm-project/llvm/test/CodeGen/AArch64/sve2p1-intrinsics-scatter-stores-128bit-index.ll (revision 28f62d72f4d56de0db0ed20c9b8c309ec5e8e193) 
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 3
2; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve2p1,+bf16 < %s | FileCheck %s
3
4declare void @llvm.aarch64.sve.st1q.scatter.scalar.offset.nxv2i64.nxv2i64(<vscale x 2 x i64>, <vscale x 1 x i1>, <vscale x 2 x i64>, i64)
5declare void @llvm.aarch64.sve.st1q.scatter.scalar.offset.nxv4i32.nxv2i64(<vscale x 4 x i32>, <vscale x 1 x i1>, <vscale x 2 x i64>, i64)
6declare void @llvm.aarch64.sve.st1q.scatter.scalar.offset.nxv8i16.nxv2i64(<vscale x 8 x i16>, <vscale x 1 x i1>, <vscale x 2 x i64>, i64)
7declare void @llvm.aarch64.sve.st1q.scatter.scalar.offset.nxv16i8.nxv2i64(<vscale x 16 x i8>, <vscale x 1 x i1>, <vscale x 2 x i64>, i64)
8declare void @llvm.aarch64.sve.st1q.scatter.scalar.offset.nxv2f64.nxv2i64(<vscale x 2 x double>, <vscale x 1 x i1>, <vscale x 2 x i64>, i64)
9declare void @llvm.aarch64.sve.st1q.scatter.scalar.offset.nxv4f32.nxv2i64(<vscale x 4 x float>, <vscale x 1 x i1>, <vscale x 2 x i64>, i64)
10declare void @llvm.aarch64.sve.st1q.scatter.scalar.offset.nxv8f16.nxv2i64(<vscale x 8 x half>, <vscale x 1 x i1>, <vscale x 2 x i64>, i64)
11declare void @llvm.aarch64.sve.st1q.scatter.scalar.offset.nxv8bf16.nxv2i64(<vscale x 8 x bfloat>, <vscale x 1 x i1>, <vscale x 2 x i64>, i64)
12declare void @llvm.aarch64.sve.st1q.scatter.index.nxv8i16(<vscale x 8 x i16>, <vscale x 1 x i1>, ptr, <vscale x 2 x i64>)
13declare void @llvm.aarch64.sve.st1q.scatter.index.nxv4i32(<vscale x 4 x i32>, <vscale x 1 x i1>, ptr, <vscale x 2 x i64>)
14declare void @llvm.aarch64.sve.st1q.scatter.index.nxv2i64(<vscale x 2 x i64>, <vscale x 1 x i1>, ptr, <vscale x 2 x i64>)
15declare void @llvm.aarch64.sve.st1q.scatter.index.nxv8bf16(<vscale x 8 x bfloat>, <vscale x 1 x i1>, ptr, <vscale x 2 x i64>)
16declare void @llvm.aarch64.sve.st1q.scatter.index.nxv8f16(<vscale x 8 x half>, <vscale x 1 x i1>, ptr, <vscale x 2 x i64>)
17declare void @llvm.aarch64.sve.st1q.scatter.index.nxv4f32(<vscale x 4 x float>, <vscale x 1 x i1>, ptr, <vscale x 2 x i64>)
18declare void @llvm.aarch64.sve.st1q.scatter.index.nxv2f64(<vscale x 2 x double>, <vscale x 1 x i1>, ptr, <vscale x 2 x i64>)
19
20define void @test_svst1q_scatter_u64index_s16(<vscale x 1 x i1> %pg, ptr %base, <vscale x 2 x i64> %idx, <vscale x 8 x i16> %data) {
21; CHECK-LABEL: test_svst1q_scatter_u64index_s16:
22; CHECK:       // %bb.0: // %entry
23; CHECK-NEXT:    lsl z0.d, z0.d, #1
24; CHECK-NEXT:    st1q { z1.q }, p0, [z0.d, x0]
25; CHECK-NEXT:    ret
26entry:
27  tail call void @llvm.aarch64.sve.st1q.scatter.index.nxv8i16(<vscale x 8 x i16> %data, <vscale x 1 x i1> %pg, ptr %base, <vscale x 2 x i64> %idx)
28  ret void
29}
30
31define void @test_svst1q_scatter_u64index_u16(<vscale x 1 x i1> %pg, ptr %base, <vscale x 2 x i64> %idx, <vscale x 8 x i16> %data) {
32; CHECK-LABEL: test_svst1q_scatter_u64index_u16:
33; CHECK:       // %bb.0: // %entry
34; CHECK-NEXT:    lsl z0.d, z0.d, #1
35; CHECK-NEXT:    st1q { z1.q }, p0, [z0.d, x0]
36; CHECK-NEXT:    ret
37entry:
38  tail call void @llvm.aarch64.sve.st1q.scatter.index.nxv8i16(<vscale x 8 x i16> %data, <vscale x 1 x i1> %pg, ptr %base, <vscale x 2 x i64> %idx)
39  ret void
40}
41
42define void @test_svst1q_scatter_u64index_s32(<vscale x 1 x i1> %pg, ptr %base, <vscale x 2 x i64> %idx, <vscale x 4 x i32> %data) {
43; CHECK-LABEL: test_svst1q_scatter_u64index_s32:
44; CHECK:       // %bb.0: // %entry
45; CHECK-NEXT:    lsl z0.d, z0.d, #2
46; CHECK-NEXT:    st1q { z1.q }, p0, [z0.d, x0]
47; CHECK-NEXT:    ret
48entry:
49  tail call void @llvm.aarch64.sve.st1q.scatter.index.nxv4i32(<vscale x 4 x i32> %data, <vscale x 1 x i1> %pg, ptr %base, <vscale x 2 x i64> %idx)
50  ret void
51}
52
53define void @test_svst1q_scatter_u64index_u32(<vscale x 1 x i1> %pg, ptr %base, <vscale x 2 x i64> %idx, <vscale x 4 x i32> %data) {
54; CHECK-LABEL: test_svst1q_scatter_u64index_u32:
55; CHECK:       // %bb.0: // %entry
56; CHECK-NEXT:    lsl z0.d, z0.d, #2
57; CHECK-NEXT:    st1q { z1.q }, p0, [z0.d, x0]
58; CHECK-NEXT:    ret
59entry:
60  tail call void @llvm.aarch64.sve.st1q.scatter.index.nxv4i32(<vscale x 4 x i32> %data, <vscale x 1 x i1> %pg, ptr %base, <vscale x 2 x i64> %idx)
61  ret void
62}
63
64define void @test_svst1q_scatter_u64index_s64(<vscale x 1 x i1> %pg, ptr %base, <vscale x 2 x i64> %idx, <vscale x 2 x i64> %data) {
65; CHECK-LABEL: test_svst1q_scatter_u64index_s64:
66; CHECK:       // %bb.0: // %entry
67; CHECK-NEXT:    lsl z0.d, z0.d, #3
68; CHECK-NEXT:    st1q { z1.q }, p0, [z0.d, x0]
69; CHECK-NEXT:    ret
70entry:
71  tail call void @llvm.aarch64.sve.st1q.scatter.index.nxv2i64(<vscale x 2 x i64> %data, <vscale x 1 x i1> %pg, ptr %base, <vscale x 2 x i64> %idx)
72  ret void
73}
74
75define void @test_svst1q_scatter_u64index_u64(<vscale x 1 x i1> %pg, ptr %base, <vscale x 2 x i64> %idx, <vscale x 2 x i64> %data) {
76; CHECK-LABEL: test_svst1q_scatter_u64index_u64:
77; CHECK:       // %bb.0: // %entry
78; CHECK-NEXT:    lsl z0.d, z0.d, #3
79; CHECK-NEXT:    st1q { z1.q }, p0, [z0.d, x0]
80; CHECK-NEXT:    ret
81entry:
82  tail call void @llvm.aarch64.sve.st1q.scatter.index.nxv2i64(<vscale x 2 x i64> %data, <vscale x 1 x i1> %pg, ptr %base, <vscale x 2 x i64> %idx)
83  ret void
84}
85
86define void @test_svst1q_scatter_u64index_bf16(<vscale x 1 x i1> %pg, ptr %base, <vscale x 2 x i64> %idx, <vscale x 8 x bfloat> %data) {
87; CHECK-LABEL: test_svst1q_scatter_u64index_bf16:
88; CHECK:       // %bb.0: // %entry
89; CHECK-NEXT:    lsl z0.d, z0.d, #1
90; CHECK-NEXT:    st1q { z1.q }, p0, [z0.d, x0]
91; CHECK-NEXT:    ret
92entry:
93  tail call void @llvm.aarch64.sve.st1q.scatter.index.nxv8bf16(<vscale x 8 x bfloat> %data, <vscale x 1 x i1> %pg, ptr %base, <vscale x 2 x i64> %idx)
94  ret void
95}
96
97define void @test_svst1q_scatter_u64index_f16(<vscale x 1 x i1> %pg, ptr %base, <vscale x 2 x i64> %idx, <vscale x 8 x half> %data) {
98; CHECK-LABEL: test_svst1q_scatter_u64index_f16:
99; CHECK:       // %bb.0: // %entry
100; CHECK-NEXT:    lsl z0.d, z0.d, #1
101; CHECK-NEXT:    st1q { z1.q }, p0, [z0.d, x0]
102; CHECK-NEXT:    ret
103entry:
104  tail call void @llvm.aarch64.sve.st1q.scatter.index.nxv8f16(<vscale x 8 x half> %data, <vscale x 1 x i1> %pg, ptr %base, <vscale x 2 x i64> %idx)
105  ret void
106}
107
108define void @test_svst1q_scatter_u64index_f32(<vscale x 1 x i1> %pg, ptr %base, <vscale x 2 x i64> %idx, <vscale x 4 x float> %data) {
109; CHECK-LABEL: test_svst1q_scatter_u64index_f32:
110; CHECK:       // %bb.0: // %entry
111; CHECK-NEXT:    lsl z0.d, z0.d, #2
112; CHECK-NEXT:    st1q { z1.q }, p0, [z0.d, x0]
113; CHECK-NEXT:    ret
114entry:
115  tail call void @llvm.aarch64.sve.st1q.scatter.index.nxv4f32(<vscale x 4 x float> %data, <vscale x 1 x i1> %pg, ptr %base, <vscale x 2 x i64> %idx)
116  ret void
117}
118
119define void @test_svst1q_scatter_u64index_f64(<vscale x 1 x i1> %pg, ptr %base, <vscale x 2 x i64> %idx, <vscale x 2 x double> %data) {
120; CHECK-LABEL: test_svst1q_scatter_u64index_f64:
121; CHECK:       // %bb.0: // %entry
122; CHECK-NEXT:    lsl z0.d, z0.d, #3
123; CHECK-NEXT:    st1q { z1.q }, p0, [z0.d, x0]
124; CHECK-NEXT:    ret
125entry:
126  tail call void @llvm.aarch64.sve.st1q.scatter.index.nxv2f64(<vscale x 2 x double> %data, <vscale x 1 x i1> %pg, ptr %base, <vscale x 2 x i64> %idx)
127  ret void
128}
129
130define void @test_svst1q_scatter_u64base_index_s16(<vscale x 1 x i1> %pg, <vscale x 2 x i64> %base, i64 %idx, <vscale x 8 x i16> %data) {
131; CHECK-LABEL: test_svst1q_scatter_u64base_index_s16:
132; CHECK:       // %bb.0: // %entry
133; CHECK-NEXT:    lsl x8, x0, #1
134; CHECK-NEXT:    st1q { z1.q }, p0, [z0.d, x8]
135; CHECK-NEXT:    ret
136entry:
137  %0 = shl i64 %idx, 1
138  tail call void @llvm.aarch64.sve.st1q.scatter.scalar.offset.nxv8i16.nxv2i64(<vscale x 8 x i16> %data, <vscale x 1 x i1> %pg, <vscale x 2 x i64> %base, i64 %0)
139  ret void
140}
141
142define void @test_svst1q_scatter_u64base_index_u16(<vscale x 1 x i1> %pg, <vscale x 2 x i64> %base, i64 %idx, <vscale x 8 x i16> %data) {
143; CHECK-LABEL: test_svst1q_scatter_u64base_index_u16:
144; CHECK:       // %bb.0: // %entry
145; CHECK-NEXT:    lsl x8, x0, #1
146; CHECK-NEXT:    st1q { z1.q }, p0, [z0.d, x8]
147; CHECK-NEXT:    ret
148entry:
149  %0 = shl i64 %idx, 1
150  tail call void @llvm.aarch64.sve.st1q.scatter.scalar.offset.nxv8i16.nxv2i64(<vscale x 8 x i16> %data, <vscale x 1 x i1> %pg, <vscale x 2 x i64> %base, i64 %0)
151  ret void
152}
153
154define void @test_svst1q_scatter_u64base_index_s32(<vscale x 1 x i1> %pg, <vscale x 2 x i64> %base, i64 %idx, <vscale x 4 x i32> %data) {
155; CHECK-LABEL: test_svst1q_scatter_u64base_index_s32:
156; CHECK:       // %bb.0: // %entry
157; CHECK-NEXT:    lsl x8, x0, #2
158; CHECK-NEXT:    st1q { z1.q }, p0, [z0.d, x8]
159; CHECK-NEXT:    ret
160entry:
161  %0 = shl i64 %idx, 2
162  tail call void @llvm.aarch64.sve.st1q.scatter.scalar.offset.nxv4i32.nxv2i64(<vscale x 4 x i32> %data, <vscale x 1 x i1> %pg, <vscale x 2 x i64> %base, i64 %0)
163  ret void
164}
165
166define void @test_svst1q_scatter_u64base_index_u32(<vscale x 1 x i1> %pg, <vscale x 2 x i64> %base, i64 %idx, <vscale x 4 x i32> %data) {
167; CHECK-LABEL: test_svst1q_scatter_u64base_index_u32:
168; CHECK:       // %bb.0: // %entry
169; CHECK-NEXT:    lsl x8, x0, #2
170; CHECK-NEXT:    st1q { z1.q }, p0, [z0.d, x8]
171; CHECK-NEXT:    ret
172entry:
173  %0 = shl i64 %idx, 2
174  tail call void @llvm.aarch64.sve.st1q.scatter.scalar.offset.nxv4i32.nxv2i64(<vscale x 4 x i32> %data, <vscale x 1 x i1> %pg, <vscale x 2 x i64> %base, i64 %0)
175  ret void
176}
177
178define void @test_svst1q_scatter_u64base_index_s64(<vscale x 1 x i1> %pg, <vscale x 2 x i64> %base, i64 %idx, <vscale x 2 x i64> %data) {
179; CHECK-LABEL: test_svst1q_scatter_u64base_index_s64:
180; CHECK:       // %bb.0: // %entry
181; CHECK-NEXT:    lsl x8, x0, #3
182; CHECK-NEXT:    st1q { z1.q }, p0, [z0.d, x8]
183; CHECK-NEXT:    ret
184entry:
185  %0 = shl i64 %idx, 3
186  tail call void @llvm.aarch64.sve.st1q.scatter.scalar.offset.nxv2i64.nxv2i64(<vscale x 2 x i64> %data, <vscale x 1 x i1> %pg, <vscale x 2 x i64> %base, i64 %0)
187  ret void
188}
189
190define void @test_svst1q_scatter_u64base_index_u64(<vscale x 1 x i1> %pg, <vscale x 2 x i64> %base, i64 %idx, <vscale x 2 x i64> %data) {
191; CHECK-LABEL: test_svst1q_scatter_u64base_index_u64:
192; CHECK:       // %bb.0: // %entry
193; CHECK-NEXT:    lsl x8, x0, #3
194; CHECK-NEXT:    st1q { z1.q }, p0, [z0.d, x8]
195; CHECK-NEXT:    ret
196entry:
197  %0 = shl i64 %idx, 3
198  tail call void @llvm.aarch64.sve.st1q.scatter.scalar.offset.nxv2i64.nxv2i64(<vscale x 2 x i64> %data, <vscale x 1 x i1> %pg, <vscale x 2 x i64> %base, i64 %0)
199  ret void
200}
201
202define void @test_svst1q_scatter_u64base_index_bf16(<vscale x 1 x i1> %pg, <vscale x 2 x i64> %base, i64 %idx, <vscale x 8 x bfloat> %data) {
203; CHECK-LABEL: test_svst1q_scatter_u64base_index_bf16:
204; CHECK:       // %bb.0: // %entry
205; CHECK-NEXT:    lsl x8, x0, #1
206; CHECK-NEXT:    st1q { z1.q }, p0, [z0.d, x8]
207; CHECK-NEXT:    ret
208entry:
209  %0 = shl i64 %idx, 1
210  tail call void @llvm.aarch64.sve.st1q.scatter.scalar.offset.nxv8bf16.nxv2i64(<vscale x 8 x bfloat> %data, <vscale x 1 x i1> %pg, <vscale x 2 x i64> %base, i64 %0)
211  ret void
212}
213
214define void @test_svst1q_scatter_u64base_index_f16(<vscale x 1 x i1> %pg, <vscale x 2 x i64> %base, i64 %idx, <vscale x 8 x half> %data) {
215; CHECK-LABEL: test_svst1q_scatter_u64base_index_f16:
216; CHECK:       // %bb.0: // %entry
217; CHECK-NEXT:    lsl x8, x0, #1
218; CHECK-NEXT:    st1q { z1.q }, p0, [z0.d, x8]
219; CHECK-NEXT:    ret
220entry:
221  %0 = shl i64 %idx, 1
222  tail call void @llvm.aarch64.sve.st1q.scatter.scalar.offset.nxv8f16.nxv2i64(<vscale x 8 x half> %data, <vscale x 1 x i1> %pg, <vscale x 2 x i64> %base, i64 %0)
223  ret void
224}
225
226define void @test_svst1q_scatter_u64base_index_f32(<vscale x 1 x i1> %pg, <vscale x 2 x i64> %base, i64 %idx, <vscale x 4 x float> %data) {
227; CHECK-LABEL: test_svst1q_scatter_u64base_index_f32:
228; CHECK:       // %bb.0: // %entry
229; CHECK-NEXT:    lsl x8, x0, #2
230; CHECK-NEXT:    st1q { z1.q }, p0, [z0.d, x8]
231; CHECK-NEXT:    ret
232entry:
233  %0 = shl i64 %idx, 2
234  tail call void @llvm.aarch64.sve.st1q.scatter.scalar.offset.nxv4f32.nxv2i64(<vscale x 4 x float> %data, <vscale x 1 x i1> %pg, <vscale x 2 x i64> %base, i64 %0)
235  ret void
236}
237
238define void @test_svst1q_scatter_u64base_index_f64(<vscale x 1 x i1> %pg, <vscale x 2 x i64> %base, i64 %idx, <vscale x 2 x double> %data) {
239; CHECK-LABEL: test_svst1q_scatter_u64base_index_f64:
240; CHECK:       // %bb.0: // %entry
241; CHECK-NEXT:    lsl x8, x0, #3
242; CHECK-NEXT:    st1q { z1.q }, p0, [z0.d, x8]
243; CHECK-NEXT:    ret
244entry:
245  %0 = shl i64 %idx, 3
246  tail call void @llvm.aarch64.sve.st1q.scatter.scalar.offset.nxv2f64.nxv2i64(<vscale x 2 x double> %data, <vscale x 1 x i1> %pg, <vscale x 2 x i64> %base, i64 %0)
247  ret void
248}
249