xref: /llvm-project/llvm/test/CodeGen/AArch64/sve2p1-intrinsics-qrshr.ll (revision 034ad11acff75511cb229c61b050f59138dbbed9) 
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve2p1 -verify-machineinstrs < %s | FileCheck %s
3
4;
5; S/UQRSHRN x2
6;
7
8define <vscale x 8 x i16> @multi_vector_sat_shift_narrow_interleave_x2_s16(<vscale x 4 x i32> %unused, <vscale x 4 x i32> %zn1, <vscale x 4 x i32> %zn2) {
9; CHECK-LABEL: multi_vector_sat_shift_narrow_interleave_x2_s16:
10; CHECK:       // %bb.0:
11; CHECK-NEXT:    mov z3.d, z2.d
12; CHECK-NEXT:    mov z2.d, z1.d
13; CHECK-NEXT:    sqrshrn z0.h, { z2.s, z3.s }, #16
14; CHECK-NEXT:    ret
15  %res = call <vscale x 8 x i16> @llvm.aarch64.sve.sqrshrn.x2.nxv8i16(<vscale x 4 x i32> %zn1, <vscale x 4 x i32> %zn2, i32 16)
16  ret <vscale x 8 x i16> %res
17}
18
19define <vscale x 8 x i16> @multi_vector_sat_shift_narrow_interleave_x2_u16(<vscale x 4 x i32> %unused, <vscale x 4 x i32> %zn1, <vscale x 4 x i32> %zn2) {
20; CHECK-LABEL: multi_vector_sat_shift_narrow_interleave_x2_u16:
21; CHECK:       // %bb.0:
22; CHECK-NEXT:    mov z3.d, z2.d
23; CHECK-NEXT:    mov z2.d, z1.d
24; CHECK-NEXT:    uqrshrn z0.h, { z2.s, z3.s }, #16
25; CHECK-NEXT:    ret
26  %res = call <vscale x 8 x i16> @llvm.aarch64.sve.uqrshrn.x2.nxv8i16(<vscale x 4 x i32> %zn1, <vscale x 4 x i32> %zn2, i32 16)
27  ret <vscale x 8 x i16> %res
28}
29
30;
31; SQRSHRUN x2
32;
33
34define <vscale x 8 x i16> @multi_vector_sat_shift_unsigned_narrow_interleave_x2_s16(<vscale x 4 x i32> %unused, <vscale x 4 x i32> %zn1, <vscale x 4 x i32> %zn2) {
35; CHECK-LABEL: multi_vector_sat_shift_unsigned_narrow_interleave_x2_s16:
36; CHECK:       // %bb.0:
37; CHECK-NEXT:    mov z3.d, z2.d
38; CHECK-NEXT:    mov z2.d, z1.d
39; CHECK-NEXT:    sqrshrun z0.h, { z2.s, z3.s }, #16
40; CHECK-NEXT:    ret
41  %res = call <vscale x 8 x i16> @llvm.aarch64.sve.sqrshrun.x2.nxv8i16(<vscale x 4 x i32> %zn1, <vscale x 4 x i32> %zn2, i32 16)
42  ret <vscale x 8 x i16> %res
43}
44
45declare <vscale x 8 x i16> @llvm.aarch64.sve.sqrshrn.x2.nxv8i16(<vscale x 4 x i32>, <vscale x 4 x i32>, i32)
46declare <vscale x 8 x i16> @llvm.aarch64.sve.uqrshrn.x2.nxv8i16(<vscale x 4 x i32>, <vscale x 4 x i32>, i32)
47
48declare <vscale x 8 x i16> @llvm.aarch64.sve.sqrshrun.x2.nxv8i16(<vscale x 4 x i32>, <vscale x 4 x i32>, i32)
49