xref: /llvm-project/llvm/test/CodeGen/AArch64/sve2p1-intrinsics-dots.ll (revision 62baf21daa377c4ec1a641b26931063c1117d262) 
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve2p1 < %s | FileCheck %s
3; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sme2 -force-streaming < %s | FileCheck %s
4
5define <vscale x 4 x i32> @sdot_x2(<vscale x 4 x i32> %zda, <vscale x 8 x i16> %zn, <vscale x 8 x i16> %zm) {
6; CHECK-LABEL: sdot_x2:
7; CHECK:       // %bb.0:
8; CHECK-NEXT:    sdot z0.s, z1.h, z2.h
9; CHECK-NEXT:    ret
10  %out = call <vscale x 4 x i32> @llvm.aarch64.sve.sdot.x2.nxv4i32(<vscale x 4 x i32> %zda, <vscale x 8 x i16> %zn, <vscale x 8 x i16> %zm)
11  ret <vscale x 4 x i32> %out
12}
13
14define <vscale x 4 x i32> @udot_x2(<vscale x 4 x i32> %zda, <vscale x 8 x i16> %zn, <vscale x 8 x i16> %zm) {
15; CHECK-LABEL: udot_x2:
16; CHECK:       // %bb.0:
17; CHECK-NEXT:    udot z0.s, z1.h, z2.h
18; CHECK-NEXT:    ret
19  %out = call <vscale x 4 x i32> @llvm.aarch64.sve.udot.x2.nxv4i32(<vscale x 4 x i32> %zda, <vscale x 8 x i16> %zn, <vscale x 8 x i16> %zm)
20  ret <vscale x 4 x i32> %out
21}
22
23define <vscale x 4 x float> @fdot_x2(<vscale x 4 x float> %zda, <vscale x 8 x half> %zn, <vscale x 8 x half> %zm) {
24; CHECK-LABEL: fdot_x2:
25; CHECK:       // %bb.0:
26; CHECK-NEXT:    fdot z0.s, z1.h, z2.h
27; CHECK-NEXT:    ret
28  %out = call <vscale x 4 x float> @llvm.aarch64.sve.fdot.x2.nxv4f32(<vscale x 4 x float> %zda, <vscale x 8 x half> %zn, <vscale x 8 x half> %zm)
29  ret <vscale x 4 x float> %out
30}
31
32define <vscale x 4 x i32> @sdot_lane_x2(<vscale x 4 x i32> %zda, <vscale x 8 x i16> %zn, <vscale x 8 x i16> %zm) {
33; CHECK-LABEL: sdot_lane_x2:
34; CHECK:       // %bb.0:
35; CHECK-NEXT:    sdot z0.s, z1.h, z2.h[3]
36; CHECK-NEXT:    ret
37  %out = call <vscale x 4 x i32> @llvm.aarch64.sve.sdot.lane.x2.nxv4i32(<vscale x 4 x i32> %zda, <vscale x 8 x i16> %zn, <vscale x 8 x i16> %zm, i32 3)
38  ret <vscale x 4 x i32> %out
39}
40
41define <vscale x 4 x i32> @udot_lane_x2(<vscale x 4 x i32> %zda, <vscale x 8 x i16> %zn, <vscale x 8 x i16> %zm) {
42; CHECK-LABEL: udot_lane_x2:
43; CHECK:       // %bb.0:
44; CHECK-NEXT:    udot z0.s, z1.h, z2.h[3]
45; CHECK-NEXT:    ret
46  %out = call <vscale x 4 x i32> @llvm.aarch64.sve.udot.lane.x2.nxv4i32(<vscale x 4 x i32> %zda, <vscale x 8 x i16> %zn, <vscale x 8 x i16> %zm, i32 3)
47  ret <vscale x 4 x i32> %out
48}
49
50define <vscale x 4 x float> @fdot_lane_x2(<vscale x 4 x float> %zda, <vscale x 8 x half> %zn, <vscale x 8 x half> %zm) {
51; CHECK-LABEL: fdot_lane_x2:
52; CHECK:       // %bb.0:
53; CHECK-NEXT:    fdot z0.s, z1.h, z2.h[3]
54; CHECK-NEXT:    ret
55  %out = call <vscale x 4 x float> @llvm.aarch64.sve.fdot.lane.x2.nxv4f32(<vscale x 4 x float> %zda, <vscale x 8 x half> %zn, <vscale x 8 x half> %zm, i32 3)
56  ret <vscale x 4 x float> %out
57}
58
59
60declare <vscale x 4 x i32> @llvm.aarch64.sve.sdot.x2.nxv4i32(<vscale x 4 x i32> %zda, <vscale x 8 x i16> %zn, <vscale x 8 x i16> %zm)
61declare <vscale x 4 x i32> @llvm.aarch64.sve.udot.x2.nxv4i32(<vscale x 4 x i32> %zda, <vscale x 8 x i16> %zn, <vscale x 8 x i16> %zm)
62declare <vscale x 4 x float> @llvm.aarch64.sve.fdot.x2.nxv4f32(<vscale x 4 x float> %zda, <vscale x 8 x half> %zn, <vscale x 8 x half> %zm)
63declare <vscale x 4 x i32> @llvm.aarch64.sve.sdot.lane.x2.nxv4i32(<vscale x 4 x i32> %zda, <vscale x 8 x i16> %zn, <vscale x 8 x i16> %zm, i32)
64declare <vscale x 4 x i32> @llvm.aarch64.sve.udot.lane.x2.nxv4i32(<vscale x 4 x i32> %zda, <vscale x 8 x i16> %zn, <vscale x 8 x i16> %zm, i32)
65declare <vscale x 4 x float> @llvm.aarch64.sve.fdot.lane.x2.nxv4f32(<vscale x 4 x float> %zda, <vscale x 8 x half> %zn, <vscale x 8 x half> %zm, i32)
66