xref: /llvm-project/llvm/test/CodeGen/AArch64/sve2p1-intrinsics-bfmlsl.ll (revision 55f067f3bafac284ff0c8e259af01b1202de94d1) 
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve2p1 -mattr=+b16b16 -verify-machineinstrs < %s | FileCheck %s
3
4define <vscale x 4 x float> @bfmlslb_f32(<vscale x 4 x float> %zda, <vscale x 8 x bfloat> %zn, <vscale x 8 x bfloat> %zm) {
5; CHECK-LABEL: bfmlslb_f32:
6; CHECK:       // %bb.0:
7; CHECK-NEXT:    bfmlslb z0.s, z1.h, z2.h
8; CHECK-NEXT:    ret
9  %out = call <vscale x 4 x float> @llvm.aarch64.sve.bfmlslb(<vscale x 4 x float> %zda, <vscale x 8 x bfloat> %zn, <vscale x 8 x bfloat> %zm)
10  ret <vscale x 4 x float> %out
11}
12
13define <vscale x 4 x float> @bfmlslt_f32(<vscale x 4 x float> %zda, <vscale x 8 x bfloat> %zn, <vscale x 8 x bfloat> %zm) {
14; CHECK-LABEL: bfmlslt_f32:
15; CHECK:       // %bb.0:
16; CHECK-NEXT:    bfmlslt z0.s, z1.h, z2.h
17; CHECK-NEXT:    ret
18  %out = call <vscale x 4 x float> @llvm.aarch64.sve.bfmlslt(<vscale x 4 x float> %zda, <vscale x 8 x bfloat> %zn, <vscale x 8 x bfloat> %zm)
19  ret <vscale x 4 x float> %out
20}
21
22define <vscale x 4 x float> @bfmlslb_lane_f32(<vscale x 4 x float> %zda, <vscale x 8 x bfloat> %zn, <vscale x 8 x bfloat> %zm) {
23; CHECK-LABEL: bfmlslb_lane_f32:
24; CHECK:       // %bb.0:
25; CHECK-NEXT:    bfmlslb z0.s, z1.h, z2.h[7]
26; CHECK-NEXT:    ret
27  %out = call <vscale x 4 x float> @llvm.aarch64.sve.bfmlslb.lane(<vscale x 4 x float> %zda, <vscale x 8 x bfloat> %zn, <vscale x 8 x bfloat> %zm, i32 7)
28  ret <vscale x 4 x float> %out
29}
30
31define <vscale x 4 x float> @bfmlslt_lane_f32(<vscale x 4 x float> %zda, <vscale x 8 x bfloat> %zn, <vscale x 8 x bfloat> %zm) {
32; CHECK-LABEL: bfmlslt_lane_f32:
33; CHECK:       // %bb.0:
34; CHECK-NEXT:    bfmlslt z0.s, z1.h, z2.h[7]
35; CHECK-NEXT:    ret
36  %out = call <vscale x 4 x float> @llvm.aarch64.sve.bfmlslt.lane(<vscale x 4 x float> %zda, <vscale x 8 x bfloat> %zn, <vscale x 8 x bfloat> %zm, i32 7)
37  ret <vscale x 4 x float> %out
38}
39
40declare <vscale x 4 x float> @llvm.aarch64.sve.bfmlslb(<vscale x 4 x float>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>)
41declare <vscale x 4 x float> @llvm.aarch64.sve.bfmlslt(<vscale x 4 x float>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>)
42declare <vscale x 4 x float> @llvm.aarch64.sve.bfmlslb.lane(<vscale x 4 x float>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i32)
43declare <vscale x 4 x float> @llvm.aarch64.sve.bfmlslt.lane(<vscale x 4 x float>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i32)
44