1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4 2; RUN: llc -mtriple=aarch64 -mattr=+sve < %s -o - | FileCheck --check-prefixes=CHECK,SVE %s 3; RUN: llc -mtriple=aarch64 -mattr=+sve2 < %s -o - | FileCheck --check-prefixes=CHECK,SVE2 %s 4 5define <vscale x 16 x i8> @testLeftGood16x8(<vscale x 16 x i8> %src1, <vscale x 16 x i8> %src2) { 6; SVE-LABEL: testLeftGood16x8: 7; SVE: // %bb.0: 8; SVE-NEXT: and z0.b, z0.b, #0x7 9; SVE-NEXT: lsl z1.b, z1.b, #3 10; SVE-NEXT: orr z0.d, z0.d, z1.d 11; SVE-NEXT: ret 12; 13; SVE2-LABEL: testLeftGood16x8: 14; SVE2: // %bb.0: 15; SVE2-NEXT: sli z0.b, z1.b, #3 16; SVE2-NEXT: ret 17 %and.i = and <vscale x 16 x i8> %src1, splat(i8 7) 18 %vshl_n = shl <vscale x 16 x i8> %src2, splat(i8 3) 19 %result = or <vscale x 16 x i8> %and.i, %vshl_n 20 ret <vscale x 16 x i8> %result 21} 22 23define <vscale x 16 x i8> @testLeftBad16x8(<vscale x 16 x i8> %src1, <vscale x 16 x i8> %src2) { 24; CHECK-LABEL: testLeftBad16x8: 25; CHECK: // %bb.0: 26; CHECK-NEXT: mov z2.b, #-91 // =0xffffffffffffffa5 27; CHECK-NEXT: lsl z1.b, z1.b, #1 28; CHECK-NEXT: and z0.d, z0.d, z2.d 29; CHECK-NEXT: orr z0.d, z0.d, z1.d 30; CHECK-NEXT: ret 31 %and.i = and <vscale x 16 x i8> %src1, splat(i8 165) 32 %vshl_n = shl <vscale x 16 x i8> %src2, splat(i8 1) 33 %result = or <vscale x 16 x i8> %and.i, %vshl_n 34 ret <vscale x 16 x i8> %result 35} 36 37define <vscale x 16 x i8> @testRightGood16x8(<vscale x 16 x i8> %src1, <vscale x 16 x i8> %src2) { 38; SVE-LABEL: testRightGood16x8: 39; SVE: // %bb.0: 40; SVE-NEXT: and z0.b, z0.b, #0xe0 41; SVE-NEXT: lsr z1.b, z1.b, #3 42; SVE-NEXT: orr z0.d, z0.d, z1.d 43; SVE-NEXT: ret 44; 45; SVE2-LABEL: testRightGood16x8: 46; SVE2: // %bb.0: 47; SVE2-NEXT: sri z0.b, z1.b, #3 48; SVE2-NEXT: ret 49 %and.i = and <vscale x 16 x i8> %src1, splat(i8 224) 50 %vshl_n = lshr <vscale x 16 x i8> %src2, splat(i8 3) 51 %result = or <vscale x 16 x i8> %and.i, %vshl_n 52 ret <vscale x 16 x i8> %result 53} 54 55define <vscale x 16 x i8> @testRightBad16x8(<vscale x 16 x i8> %src1, <vscale x 16 x i8> %src2) { 56; CHECK-LABEL: testRightBad16x8: 57; CHECK: // %bb.0: 58; CHECK-NEXT: mov z2.b, #-91 // =0xffffffffffffffa5 59; CHECK-NEXT: lsr z1.b, z1.b, #1 60; CHECK-NEXT: and z0.d, z0.d, z2.d 61; CHECK-NEXT: orr z0.d, z0.d, z1.d 62; CHECK-NEXT: ret 63 %and.i = and <vscale x 16 x i8> %src1, splat(i8 165) 64 %vshl_n = lshr <vscale x 16 x i8> %src2, splat(i8 1) 65 %result = or <vscale x 16 x i8> %and.i, %vshl_n 66 ret <vscale x 16 x i8> %result 67} 68 69define <vscale x 8 x i16> @testLeftGood8x16(<vscale x 8 x i16> %src1, <vscale x 8 x i16> %src2) { 70; SVE-LABEL: testLeftGood8x16: 71; SVE: // %bb.0: 72; SVE-NEXT: and z0.h, z0.h, #0x3fff 73; SVE-NEXT: lsl z1.h, z1.h, #14 74; SVE-NEXT: orr z0.d, z0.d, z1.d 75; SVE-NEXT: ret 76; 77; SVE2-LABEL: testLeftGood8x16: 78; SVE2: // %bb.0: 79; SVE2-NEXT: sli z0.h, z1.h, #14 80; SVE2-NEXT: ret 81 %and.i = and <vscale x 8 x i16> %src1, splat(i16 16383) 82 %vshl_n = shl <vscale x 8 x i16> %src2, splat(i16 14) 83 %result = or <vscale x 8 x i16> %and.i, %vshl_n 84 ret <vscale x 8 x i16> %result 85} 86 87define <vscale x 8 x i16> @testLeftBad8x16(<vscale x 8 x i16> %src1, <vscale x 8 x i16> %src2) { 88; CHECK-LABEL: testLeftBad8x16: 89; CHECK: // %bb.0: 90; CHECK-NEXT: mov w8, #16500 // =0x4074 91; CHECK-NEXT: lsl z1.h, z1.h, #14 92; CHECK-NEXT: mov z2.h, w8 93; CHECK-NEXT: and z0.d, z0.d, z2.d 94; CHECK-NEXT: orr z0.d, z0.d, z1.d 95; CHECK-NEXT: ret 96 %and.i = and <vscale x 8 x i16> %src1, splat(i16 16500) 97 %vshl_n = shl <vscale x 8 x i16> %src2, splat(i16 14) 98 %result = or <vscale x 8 x i16> %and.i, %vshl_n 99 ret <vscale x 8 x i16> %result 100} 101 102define <vscale x 8 x i16> @testRightGood8x16(<vscale x 8 x i16> %src1, <vscale x 8 x i16> %src2) { 103; SVE-LABEL: testRightGood8x16: 104; SVE: // %bb.0: 105; SVE-NEXT: and z0.h, z0.h, #0xfffc 106; SVE-NEXT: lsr z1.h, z1.h, #14 107; SVE-NEXT: orr z0.d, z0.d, z1.d 108; SVE-NEXT: ret 109; 110; SVE2-LABEL: testRightGood8x16: 111; SVE2: // %bb.0: 112; SVE2-NEXT: sri z0.h, z1.h, #14 113; SVE2-NEXT: ret 114 %and.i = and <vscale x 8 x i16> %src1, splat(i16 65532) 115 %vshl_n = lshr <vscale x 8 x i16> %src2, splat(i16 14) 116 %result = or <vscale x 8 x i16> %and.i, %vshl_n 117 ret <vscale x 8 x i16> %result 118} 119 120define <vscale x 8 x i16> @testRightBad8x16(<vscale x 8 x i16> %src1, <vscale x 8 x i16> %src2) { 121; CHECK-LABEL: testRightBad8x16: 122; CHECK: // %bb.0: 123; CHECK-NEXT: mov w8, #16500 // =0x4074 124; CHECK-NEXT: lsr z1.h, z1.h, #14 125; CHECK-NEXT: mov z2.h, w8 126; CHECK-NEXT: and z0.d, z0.d, z2.d 127; CHECK-NEXT: orr z0.d, z0.d, z1.d 128; CHECK-NEXT: ret 129 %and.i = and <vscale x 8 x i16> %src1, splat(i16 16500) 130 %vshl_n = lshr <vscale x 8 x i16> %src2, splat(i16 14) 131 %result = or <vscale x 8 x i16> %and.i, %vshl_n 132 ret <vscale x 8 x i16> %result 133} 134 135define <vscale x 4 x i32> @testLeftGood4x32(<vscale x 4 x i32> %src1, <vscale x 4 x i32> %src2) { 136; SVE-LABEL: testLeftGood4x32: 137; SVE: // %bb.0: 138; SVE-NEXT: and z0.s, z0.s, #0x3fffff 139; SVE-NEXT: lsl z1.s, z1.s, #22 140; SVE-NEXT: orr z0.d, z0.d, z1.d 141; SVE-NEXT: ret 142; 143; SVE2-LABEL: testLeftGood4x32: 144; SVE2: // %bb.0: 145; SVE2-NEXT: sli z0.s, z1.s, #22 146; SVE2-NEXT: ret 147 %and.i = and <vscale x 4 x i32> %src1, splat(i32 4194303) 148 %vshl_n = shl <vscale x 4 x i32> %src2, splat(i32 22) 149 %result = or <vscale x 4 x i32> %and.i, %vshl_n 150 ret <vscale x 4 x i32> %result 151} 152 153define <vscale x 4 x i32> @testLeftBad4x32(<vscale x 4 x i32> %src1, <vscale x 4 x i32> %src2) { 154; CHECK-LABEL: testLeftBad4x32: 155; CHECK: // %bb.0: 156; CHECK-NEXT: and z0.s, z0.s, #0x3ffffc 157; CHECK-NEXT: lsl z1.s, z1.s, #22 158; CHECK-NEXT: orr z0.d, z0.d, z1.d 159; CHECK-NEXT: ret 160 %and.i = and <vscale x 4 x i32> %src1, splat(i32 4194300) 161 %vshl_n = shl <vscale x 4 x i32> %src2, splat(i32 22) 162 %result = or <vscale x 4 x i32> %and.i, %vshl_n 163 ret <vscale x 4 x i32> %result 164} 165 166define <vscale x 4 x i32> @testRightGood4x32(<vscale x 4 x i32> %src1, <vscale x 4 x i32> %src2) { 167; SVE-LABEL: testRightGood4x32: 168; SVE: // %bb.0: 169; SVE-NEXT: and z0.s, z0.s, #0xfffffc00 170; SVE-NEXT: lsr z1.s, z1.s, #22 171; SVE-NEXT: orr z0.d, z0.d, z1.d 172; SVE-NEXT: ret 173; 174; SVE2-LABEL: testRightGood4x32: 175; SVE2: // %bb.0: 176; SVE2-NEXT: sri z0.s, z1.s, #22 177; SVE2-NEXT: ret 178 %and.i = and <vscale x 4 x i32> %src1, splat(i32 4294966272) 179 %vshl_n = lshr <vscale x 4 x i32> %src2, splat(i32 22) 180 %result = or <vscale x 4 x i32> %and.i, %vshl_n 181 ret <vscale x 4 x i32> %result 182} 183 184define <vscale x 4 x i32> @testRightBad4x32(<vscale x 4 x i32> %src1, <vscale x 4 x i32> %src2) { 185; CHECK-LABEL: testRightBad4x32: 186; CHECK: // %bb.0: 187; CHECK-NEXT: and z0.s, z0.s, #0x3ffffc 188; CHECK-NEXT: lsr z1.s, z1.s, #22 189; CHECK-NEXT: orr z0.d, z0.d, z1.d 190; CHECK-NEXT: ret 191 %and.i = and <vscale x 4 x i32> %src1, splat(i32 4194300) 192 %vshl_n = lshr <vscale x 4 x i32> %src2, splat(i32 22) 193 %result = or <vscale x 4 x i32> %and.i, %vshl_n 194 ret <vscale x 4 x i32> %result 195} 196 197define <vscale x 2 x i64> @testLeftGood2x64(<vscale x 2 x i64> %src1, <vscale x 2 x i64> %src2) { 198; SVE-LABEL: testLeftGood2x64: 199; SVE: // %bb.0: 200; SVE-NEXT: and z0.d, z0.d, #0xffffffffffff 201; SVE-NEXT: lsl z1.d, z1.d, #48 202; SVE-NEXT: orr z0.d, z0.d, z1.d 203; SVE-NEXT: ret 204; 205; SVE2-LABEL: testLeftGood2x64: 206; SVE2: // %bb.0: 207; SVE2-NEXT: sli z0.d, z1.d, #48 208; SVE2-NEXT: ret 209 %and.i = and <vscale x 2 x i64> %src1, splat(i64 281474976710655) 210 %vshl_n = shl <vscale x 2 x i64> %src2, splat(i64 48) 211 %result = or <vscale x 2 x i64> %and.i, %vshl_n 212 ret <vscale x 2 x i64> %result 213} 214 215define <vscale x 2 x i64> @testLeftBad2x64(<vscale x 2 x i64> %src1, <vscale x 2 x i64> %src2) { 216; CHECK-LABEL: testLeftBad2x64: 217; CHECK: // %bb.0: 218; CHECK-NEXT: mov x8, #10 // =0xa 219; CHECK-NEXT: lsl z1.d, z1.d, #48 220; CHECK-NEXT: movk x8, #1, lsl #48 221; CHECK-NEXT: mov z2.d, x8 222; CHECK-NEXT: and z0.d, z0.d, z2.d 223; CHECK-NEXT: orr z0.d, z0.d, z1.d 224; CHECK-NEXT: ret 225 %and.i = and <vscale x 2 x i64> %src1, splat(i64 281474976710666) 226 %vshl_n = shl <vscale x 2 x i64> %src2, splat(i64 48) 227 %result = or <vscale x 2 x i64> %and.i, %vshl_n 228 ret <vscale x 2 x i64> %result 229} 230 231define <vscale x 2 x i64> @testRightGood2x64(<vscale x 2 x i64> %src1, <vscale x 2 x i64> %src2) { 232; SVE-LABEL: testRightGood2x64: 233; SVE: // %bb.0: 234; SVE-NEXT: and z0.d, z0.d, #0xffffffffffff0000 235; SVE-NEXT: lsr z1.d, z1.d, #48 236; SVE-NEXT: orr z0.d, z0.d, z1.d 237; SVE-NEXT: ret 238; 239; SVE2-LABEL: testRightGood2x64: 240; SVE2: // %bb.0: 241; SVE2-NEXT: sri z0.d, z1.d, #48 242; SVE2-NEXT: ret 243 %and.i = and <vscale x 2 x i64> %src1, splat(i64 18446744073709486080) 244 %vshl_n = lshr <vscale x 2 x i64> %src2, splat(i64 48) 245 %result = or <vscale x 2 x i64> %and.i, %vshl_n 246 ret <vscale x 2 x i64> %result 247} 248 249define <vscale x 2 x i64> @testRightBad2x64(<vscale x 2 x i64> %src1, <vscale x 2 x i64> %src2) { 250; CHECK-LABEL: testRightBad2x64: 251; CHECK: // %bb.0: 252; CHECK-NEXT: mov x8, #10 // =0xa 253; CHECK-NEXT: lsr z1.d, z1.d, #48 254; CHECK-NEXT: movk x8, #1, lsl #48 255; CHECK-NEXT: mov z2.d, x8 256; CHECK-NEXT: and z0.d, z0.d, z2.d 257; CHECK-NEXT: orr z0.d, z0.d, z1.d 258; CHECK-NEXT: ret 259 %and.i = and <vscale x 2 x i64> %src1, splat(i64 281474976710666) 260 %vshl_n = lshr <vscale x 2 x i64> %src2, splat(i64 48) 261 %result = or <vscale x 2 x i64> %and.i, %vshl_n 262 ret <vscale x 2 x i64> %result 263} 264