xref: /llvm-project/llvm/test/CodeGen/AArch64/sve2-rsra.ll (revision 424b2ae9ab3af0dc2d70438a38898a19e3177026) 
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc < %s | FileCheck %s
3
4target triple = "aarch64-unknown-linux-gnu"
5
6; URSRA
7
8define <vscale x 16 x i8> @ursra_i8(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b) #0 {
9; CHECK-LABEL: ursra_i8:
10; CHECK:       // %bb.0:
11; CHECK-NEXT:    ursra z0.b, z1.b, #1
12; CHECK-NEXT:    ret
13  %pg = call <vscale x 16 x i1> @llvm.aarch64.sve.ptrue.nxv16i1(i32 31)
14  %shift = call <vscale x 16 x i8> @llvm.aarch64.sve.urshr.nxv16i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %b, i32 1)
15  %add = add <vscale x 16 x i8> %a, %shift
16  ret <vscale x 16 x i8> %add
17}
18
19define <vscale x 8 x i16> @ursra_i16(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b) #0 {
20; CHECK-LABEL: ursra_i16:
21; CHECK:       // %bb.0:
22; CHECK-NEXT:    ursra z0.h, z1.h, #2
23; CHECK-NEXT:    ret
24  %pg = call <vscale x 8 x i1> @llvm.aarch64.sve.ptrue.nxv8i1(i32 31)
25  %shift = call <vscale x 8 x i16> @llvm.aarch64.sve.urshr.nxv8i16(<vscale x 8 x i1> %pg, <vscale x 8 x i16> %b, i32 2)
26  %add = add <vscale x 8 x i16> %a, %shift
27  ret <vscale x 8 x i16> %add
28}
29
30define <vscale x 4 x i32> @ursra_i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) #0 {
31; CHECK-LABEL: ursra_i32:
32; CHECK:       // %bb.0:
33; CHECK-NEXT:    ursra z0.s, z1.s, #3
34; CHECK-NEXT:    ret
35  %pg = call <vscale x 4 x i1> @llvm.aarch64.sve.ptrue.nxv4i1(i32 31)
36  %shift = call <vscale x 4 x i32> @llvm.aarch64.sve.urshr.nxv4i32(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %b, i32 3)
37  %add = add <vscale x 4 x i32> %a, %shift
38  ret <vscale x 4 x i32> %add
39}
40
41define <vscale x 2 x i64> @ursra_i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b) #0 {
42; CHECK-LABEL: ursra_i64:
43; CHECK:       // %bb.0:
44; CHECK-NEXT:    ursra z0.d, z1.d, #4
45; CHECK-NEXT:    ret
46  %pg = call <vscale x 2 x i1> @llvm.aarch64.sve.ptrue.nxv2i1(i32 31)
47  %shift = call <vscale x 2 x i64> @llvm.aarch64.sve.urshr.nxv2i64(<vscale x 2 x i1> %pg, <vscale x 2 x i64> %b, i32 4)
48  %add = add <vscale x 2 x i64> %a, %shift
49  ret <vscale x 2 x i64> %add
50}
51
52; SRSRA
53
54define <vscale x 16 x i8> @srsra_i8(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b) #0 {
55; CHECK-LABEL: srsra_i8:
56; CHECK:       // %bb.0:
57; CHECK-NEXT:    srsra z0.b, z1.b, #1
58; CHECK-NEXT:    ret
59  %pg = call <vscale x 16 x i1> @llvm.aarch64.sve.ptrue.nxv16i1(i32 31)
60  %shift = call <vscale x 16 x i8> @llvm.aarch64.sve.srshr.nxv16i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %b, i32 1)
61  %add = add <vscale x 16 x i8> %a, %shift
62  ret <vscale x 16 x i8> %add
63}
64
65define <vscale x 8 x i16> @srsra_i16(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b) #0 {
66; CHECK-LABEL: srsra_i16:
67; CHECK:       // %bb.0:
68; CHECK-NEXT:    srsra z0.h, z1.h, #2
69; CHECK-NEXT:    ret
70  %pg = call <vscale x 8 x i1> @llvm.aarch64.sve.ptrue.nxv8i1(i32 31)
71  %shift = call <vscale x 8 x i16> @llvm.aarch64.sve.srshr.nxv8i16(<vscale x 8 x i1> %pg, <vscale x 8 x i16> %b, i32 2)
72  %add = add <vscale x 8 x i16> %a, %shift
73  ret <vscale x 8 x i16> %add
74}
75
76define <vscale x 4 x i32> @srsra_i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) #0 {
77; CHECK-LABEL: srsra_i32:
78; CHECK:       // %bb.0:
79; CHECK-NEXT:    srsra z0.s, z1.s, #3
80; CHECK-NEXT:    ret
81  %pg = call <vscale x 4 x i1> @llvm.aarch64.sve.ptrue.nxv4i1(i32 31)
82  %shift = call <vscale x 4 x i32> @llvm.aarch64.sve.srshr.nxv4i32(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %b, i32 3)
83  %add = add <vscale x 4 x i32> %a, %shift
84  ret <vscale x 4 x i32> %add
85}
86
87define <vscale x 2 x i64> @srsra_i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b) #0 {
88; CHECK-LABEL: srsra_i64:
89; CHECK:       // %bb.0:
90; CHECK-NEXT:    srsra z0.d, z1.d, #4
91; CHECK-NEXT:    ret
92  %pg = call <vscale x 2 x i1> @llvm.aarch64.sve.ptrue.nxv2i1(i32 31)
93  %shift = call <vscale x 2 x i64> @llvm.aarch64.sve.srshr.nxv2i64(<vscale x 2 x i1> %pg, <vscale x 2 x i64> %b, i32 4)
94  %add = add <vscale x 2 x i64> %a, %shift
95  ret <vscale x 2 x i64> %add
96}
97
98
99declare <vscale x 16 x i1> @llvm.aarch64.sve.ptrue.nxv16i1(i32 immarg)
100declare <vscale x 8 x i1> @llvm.aarch64.sve.ptrue.nxv8i1(i32 immarg)
101declare <vscale x 4 x i1> @llvm.aarch64.sve.ptrue.nxv4i1(i32 immarg)
102declare <vscale x 2 x i1> @llvm.aarch64.sve.ptrue.nxv2i1(i32 immarg)
103
104declare <vscale x 16 x i8> @llvm.aarch64.sve.urshr.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>, i32)
105declare <vscale x 8 x i16> @llvm.aarch64.sve.urshr.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>, i32)
106declare <vscale x 4 x i32> @llvm.aarch64.sve.urshr.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, i32)
107declare <vscale x 2 x i64> @llvm.aarch64.sve.urshr.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>, i32)
108
109declare <vscale x 16 x i8> @llvm.aarch64.sve.srshr.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>, i32)
110declare <vscale x 8 x i16> @llvm.aarch64.sve.srshr.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>, i32)
111declare <vscale x 4 x i32> @llvm.aarch64.sve.srshr.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, i32)
112declare <vscale x 2 x i64> @llvm.aarch64.sve.srshr.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>, i32)
113
114attributes #0 = { "target-features"="+sve,+sve2" }
115