xref: /llvm-project/llvm/test/CodeGen/AArch64/sve2-intrinsics-widening-complex-int-arith.ll (revision 62baf21daa377c4ec1a641b26931063c1117d262) 
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve2 < %s | FileCheck %s
3; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sme -force-streaming < %s | FileCheck %s
4
5;
6; SADDLBT
7;
8
9define <vscale x 8 x i16> @saddlbt_b(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b) {
10; CHECK-LABEL: saddlbt_b:
11; CHECK:       // %bb.0:
12; CHECK-NEXT:    saddlbt z0.h, z0.b, z1.b
13; CHECK-NEXT:    ret
14  %out = call <vscale x 8 x i16> @llvm.aarch64.sve.saddlbt.nxv8i16(<vscale x 16 x i8> %a,
15                                                              <vscale x 16 x i8> %b)
16  ret <vscale x 8 x i16> %out
17}
18
19define <vscale x 4 x i32> @saddlbt_h(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b) {
20; CHECK-LABEL: saddlbt_h:
21; CHECK:       // %bb.0:
22; CHECK-NEXT:    saddlbt z0.s, z0.h, z1.h
23; CHECK-NEXT:    ret
24  %out = call <vscale x 4 x i32> @llvm.aarch64.sve.saddlbt.nxv4i32(<vscale x 8 x i16> %a,
25                                                              <vscale x 8 x i16> %b)
26  ret <vscale x 4 x i32> %out
27}
28
29define <vscale x 2 x i64> @saddlbt_s(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) {
30; CHECK-LABEL: saddlbt_s:
31; CHECK:       // %bb.0:
32; CHECK-NEXT:    saddlbt z0.d, z0.s, z1.s
33; CHECK-NEXT:    ret
34  %out = call <vscale x 2 x i64> @llvm.aarch64.sve.saddlbt.nxv2i64(<vscale x 4 x i32> %a,
35                                                              <vscale x 4 x i32> %b)
36  ret <vscale x 2 x i64> %out
37}
38
39;
40; SSUBLBT
41;
42
43define <vscale x 8 x i16> @ssublbt_b(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b) {
44; CHECK-LABEL: ssublbt_b:
45; CHECK:       // %bb.0:
46; CHECK-NEXT:    ssublbt z0.h, z0.b, z1.b
47; CHECK-NEXT:    ret
48  %out = call <vscale x 8 x i16> @llvm.aarch64.sve.ssublbt.nxv8i16(<vscale x 16 x i8> %a,
49                                                              <vscale x 16 x i8> %b)
50  ret <vscale x 8 x i16> %out
51}
52
53define <vscale x 4 x i32> @ssublbt_h(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b) {
54; CHECK-LABEL: ssublbt_h:
55; CHECK:       // %bb.0:
56; CHECK-NEXT:    ssublbt z0.s, z0.h, z1.h
57; CHECK-NEXT:    ret
58  %out = call <vscale x 4 x i32> @llvm.aarch64.sve.ssublbt.nxv4i32(<vscale x 8 x i16> %a,
59                                                              <vscale x 8 x i16> %b)
60  ret <vscale x 4 x i32> %out
61}
62
63define <vscale x 2 x i64> @ssublbt_s(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) {
64; CHECK-LABEL: ssublbt_s:
65; CHECK:       // %bb.0:
66; CHECK-NEXT:    ssublbt z0.d, z0.s, z1.s
67; CHECK-NEXT:    ret
68  %out = call <vscale x 2 x i64> @llvm.aarch64.sve.ssublbt.nxv2i64(<vscale x 4 x i32> %a,
69                                                              <vscale x 4 x i32> %b)
70  ret <vscale x 2 x i64> %out
71}
72
73;
74; SSUBLTB
75;
76
77define <vscale x 8 x i16> @ssubltb_b(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b) {
78; CHECK-LABEL: ssubltb_b:
79; CHECK:       // %bb.0:
80; CHECK-NEXT:    ssubltb z0.h, z0.b, z1.b
81; CHECK-NEXT:    ret
82  %out = call <vscale x 8 x i16> @llvm.aarch64.sve.ssubltb.nxv8i16(<vscale x 16 x i8> %a,
83                                                              <vscale x 16 x i8> %b)
84  ret <vscale x 8 x i16> %out
85}
86
87define <vscale x 4 x i32> @ssubltb_h(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b) {
88; CHECK-LABEL: ssubltb_h:
89; CHECK:       // %bb.0:
90; CHECK-NEXT:    ssubltb z0.s, z0.h, z1.h
91; CHECK-NEXT:    ret
92  %out = call <vscale x 4 x i32> @llvm.aarch64.sve.ssubltb.nxv4i32(<vscale x 8 x i16> %a,
93                                                              <vscale x 8 x i16> %b)
94  ret <vscale x 4 x i32> %out
95}
96
97define <vscale x 2 x i64> @ssubltb_s(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) {
98; CHECK-LABEL: ssubltb_s:
99; CHECK:       // %bb.0:
100; CHECK-NEXT:    ssubltb z0.d, z0.s, z1.s
101; CHECK-NEXT:    ret
102  %out = call <vscale x 2 x i64> @llvm.aarch64.sve.ssubltb.nxv2i64(<vscale x 4 x i32> %a,
103                                                              <vscale x 4 x i32> %b)
104  ret <vscale x 2 x i64> %out
105}
106
107declare <vscale x 8 x i16> @llvm.aarch64.sve.saddlbt.nxv8i16(<vscale x 16 x i8>, <vscale x 16 x i8>)
108declare <vscale x 4 x i32> @llvm.aarch64.sve.saddlbt.nxv4i32(<vscale x 8 x i16>, <vscale x 8 x i16>)
109declare <vscale x 2 x i64> @llvm.aarch64.sve.saddlbt.nxv2i64(<vscale x 4 x i32>, <vscale x 4 x i32>)
110
111declare <vscale x 8 x i16> @llvm.aarch64.sve.ssublbt.nxv8i16(<vscale x 16 x i8>, <vscale x 16 x i8>)
112declare <vscale x 4 x i32> @llvm.aarch64.sve.ssublbt.nxv4i32(<vscale x 8 x i16>, <vscale x 8 x i16>)
113declare <vscale x 2 x i64> @llvm.aarch64.sve.ssublbt.nxv2i64(<vscale x 4 x i32>, <vscale x 4 x i32>)
114
115declare <vscale x 8 x i16> @llvm.aarch64.sve.ssubltb.nxv8i16(<vscale x 16 x i8>, <vscale x 16 x i8>)
116declare <vscale x 4 x i32> @llvm.aarch64.sve.ssubltb.nxv4i32(<vscale x 8 x i16>, <vscale x 8 x i16>)
117declare <vscale x 2 x i64> @llvm.aarch64.sve.ssubltb.nxv2i64(<vscale x 4 x i32>, <vscale x 4 x i32>)
118