xref: /llvm-project/llvm/test/CodeGen/AArch64/sve2-intrinsics-while.ll (revision 62baf21daa377c4ec1a641b26931063c1117d262) 
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve2 < %s | FileCheck %s
3; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sme -force-streaming < %s | FileCheck %s
4
5;
6; WHILEGE
7;
8
9define <vscale x 16 x i1> @whilege_b_ww(i32 %a, i32 %b) {
10; CHECK-LABEL: whilege_b_ww:
11; CHECK:       // %bb.0:
12; CHECK-NEXT:    whilege p0.b, w0, w1
13; CHECK-NEXT:    ret
14  %out = call <vscale x 16 x i1> @llvm.aarch64.sve.whilege.nxv16i1.i32(i32 %a, i32 %b)
15  ret <vscale x 16 x i1> %out
16}
17
18define <vscale x 16 x i1> @whilege_b_xx(i64 %a, i64 %b) {
19; CHECK-LABEL: whilege_b_xx:
20; CHECK:       // %bb.0:
21; CHECK-NEXT:    whilege p0.b, x0, x1
22; CHECK-NEXT:    ret
23  %out = call <vscale x 16 x i1> @llvm.aarch64.sve.whilege.nxv16i1.i64(i64 %a, i64 %b)
24  ret <vscale x 16 x i1> %out
25}
26
27define <vscale x 8 x i1> @whilege_h_ww(i32 %a, i32 %b) {
28; CHECK-LABEL: whilege_h_ww:
29; CHECK:       // %bb.0:
30; CHECK-NEXT:    whilege p0.h, w0, w1
31; CHECK-NEXT:    ret
32  %out = call <vscale x 8 x i1> @llvm.aarch64.sve.whilege.nxv8i1.i32(i32 %a, i32 %b)
33  ret <vscale x 8 x i1> %out
34}
35
36define <vscale x 8 x i1> @whilege_h_xx(i64 %a, i64 %b) {
37; CHECK-LABEL: whilege_h_xx:
38; CHECK:       // %bb.0:
39; CHECK-NEXT:    whilege p0.h, x0, x1
40; CHECK-NEXT:    ret
41  %out = call <vscale x 8 x i1> @llvm.aarch64.sve.whilege.nxv8i1.i64(i64 %a, i64 %b)
42  ret <vscale x 8 x i1> %out
43}
44
45define <vscale x 4 x i1> @whilege_s_ww(i32 %a, i32 %b) {
46; CHECK-LABEL: whilege_s_ww:
47; CHECK:       // %bb.0:
48; CHECK-NEXT:    whilege p0.s, w0, w1
49; CHECK-NEXT:    ret
50  %out = call <vscale x 4 x i1> @llvm.aarch64.sve.whilege.nxv4i1.i32(i32 %a, i32 %b)
51  ret <vscale x 4 x i1> %out
52}
53
54define <vscale x 4 x i1> @whilege_s_xx(i64 %a, i64 %b) {
55; CHECK-LABEL: whilege_s_xx:
56; CHECK:       // %bb.0:
57; CHECK-NEXT:    whilege p0.s, x0, x1
58; CHECK-NEXT:    ret
59  %out = call <vscale x 4 x i1> @llvm.aarch64.sve.whilege.nxv4i1.i64(i64 %a, i64 %b)
60  ret <vscale x 4 x i1> %out
61}
62
63define <vscale x 2 x i1> @whilege_d_ww(i32 %a, i32 %b) {
64; CHECK-LABEL: whilege_d_ww:
65; CHECK:       // %bb.0:
66; CHECK-NEXT:    whilege p0.d, w0, w1
67; CHECK-NEXT:    ret
68  %out = call <vscale x 2 x i1> @llvm.aarch64.sve.whilege.nxv2i1.i32(i32 %a, i32 %b)
69  ret <vscale x 2 x i1> %out
70}
71
72define <vscale x 2 x i1> @whilege_d_xx(i64 %a, i64 %b) {
73; CHECK-LABEL: whilege_d_xx:
74; CHECK:       // %bb.0:
75; CHECK-NEXT:    whilege p0.d, x0, x1
76; CHECK-NEXT:    ret
77  %out = call <vscale x 2 x i1> @llvm.aarch64.sve.whilege.nxv2i1.i64(i64 %a, i64 %b)
78  ret <vscale x 2 x i1> %out
79}
80
81; Ensure we don't convert constant decrementing while instructions to ptrue.
82define <vscale x 16 x i1> @whilege_b_ii() {
83; CHECK-LABEL: whilege_b_ii:
84; CHECK:       // %bb.0: // %entry
85; CHECK-NEXT:    mov w8, #-2 // =0xfffffffe
86; CHECK-NEXT:    mov w9, #3 // =0x3
87; CHECK-NEXT:    whilege p0.b, w9, w8
88; CHECK-NEXT:    ret
89entry:
90  %out = call <vscale x 16 x i1> @llvm.aarch64.sve.whilege.nxv16i1.i32(i32 3, i32 -2)
91  ret <vscale x 16 x i1> %out
92}
93
94;
95; WHILEHS
96;
97
98define <vscale x 16 x i1> @whilehs_b_ww(i32 %a, i32 %b) {
99; CHECK-LABEL: whilehs_b_ww:
100; CHECK:       // %bb.0:
101; CHECK-NEXT:    whilehs p0.b, w0, w1
102; CHECK-NEXT:    ret
103  %out = call <vscale x 16 x i1> @llvm.aarch64.sve.whilehs.nxv16i1.i32(i32 %a, i32 %b)
104  ret <vscale x 16 x i1> %out
105}
106
107define <vscale x 16 x i1> @whilehs_b_xx(i64 %a, i64 %b) {
108; CHECK-LABEL: whilehs_b_xx:
109; CHECK:       // %bb.0:
110; CHECK-NEXT:    whilehs p0.b, x0, x1
111; CHECK-NEXT:    ret
112  %out = call <vscale x 16 x i1> @llvm.aarch64.sve.whilehs.nxv16i1.i64(i64 %a, i64 %b)
113  ret <vscale x 16 x i1> %out
114}
115
116define <vscale x 8 x i1> @whilehs_h_ww(i32 %a, i32 %b) {
117; CHECK-LABEL: whilehs_h_ww:
118; CHECK:       // %bb.0:
119; CHECK-NEXT:    whilehs p0.h, w0, w1
120; CHECK-NEXT:    ret
121  %out = call <vscale x 8 x i1> @llvm.aarch64.sve.whilehs.nxv8i1.i32(i32 %a, i32 %b)
122  ret <vscale x 8 x i1> %out
123}
124
125define <vscale x 8 x i1> @whilehs_h_xx(i64 %a, i64 %b) {
126; CHECK-LABEL: whilehs_h_xx:
127; CHECK:       // %bb.0:
128; CHECK-NEXT:    whilehs p0.h, x0, x1
129; CHECK-NEXT:    ret
130  %out = call <vscale x 8 x i1> @llvm.aarch64.sve.whilehs.nxv8i1.i64(i64 %a, i64 %b)
131  ret <vscale x 8 x i1> %out
132}
133
134define <vscale x 4 x i1> @whilehs_s_ww(i32 %a, i32 %b) {
135; CHECK-LABEL: whilehs_s_ww:
136; CHECK:       // %bb.0:
137; CHECK-NEXT:    whilehs p0.s, w0, w1
138; CHECK-NEXT:    ret
139  %out = call <vscale x 4 x i1> @llvm.aarch64.sve.whilehs.nxv4i1.i32(i32 %a, i32 %b)
140  ret <vscale x 4 x i1> %out
141}
142
143define <vscale x 4 x i1> @whilehs_s_xx(i64 %a, i64 %b) {
144; CHECK-LABEL: whilehs_s_xx:
145; CHECK:       // %bb.0:
146; CHECK-NEXT:    whilehs p0.s, x0, x1
147; CHECK-NEXT:    ret
148  %out = call <vscale x 4 x i1> @llvm.aarch64.sve.whilehs.nxv4i1.i64(i64 %a, i64 %b)
149  ret <vscale x 4 x i1> %out
150}
151
152define <vscale x 2 x i1> @whilehs_d_ww(i32 %a, i32 %b) {
153; CHECK-LABEL: whilehs_d_ww:
154; CHECK:       // %bb.0:
155; CHECK-NEXT:    whilehs p0.d, w0, w1
156; CHECK-NEXT:    ret
157  %out = call <vscale x 2 x i1> @llvm.aarch64.sve.whilehs.nxv2i1.i32(i32 %a, i32 %b)
158  ret <vscale x 2 x i1> %out
159}
160
161define <vscale x 2 x i1> @whilehs_d_xx(i64 %a, i64 %b) {
162; CHECK-LABEL: whilehs_d_xx:
163; CHECK:       // %bb.0:
164; CHECK-NEXT:    whilehs p0.d, x0, x1
165; CHECK-NEXT:    ret
166  %out = call <vscale x 2 x i1> @llvm.aarch64.sve.whilehs.nxv2i1.i64(i64 %a, i64 %b)
167  ret <vscale x 2 x i1> %out
168}
169
170; Ensure we don't convert constant decrementing while instructions to ptrue.
171define <vscale x 16 x i1> @whilehs_b_ii() {
172; CHECK-LABEL: whilehs_b_ii:
173; CHECK:       // %bb.0: // %entry
174; CHECK-NEXT:    mov w8, #2 // =0x2
175; CHECK-NEXT:    mov w9, #8 // =0x8
176; CHECK-NEXT:    whilehs p0.b, x9, x8
177; CHECK-NEXT:    ret
178entry:
179  %out = call <vscale x 16 x i1> @llvm.aarch64.sve.whilehs.nxv16i1.i64(i64 8, i64 2)
180  ret <vscale x 16 x i1> %out
181}
182
183;
184; WHILEGT
185;
186
187define <vscale x 16 x i1> @whilegt_b_ww(i32 %a, i32 %b) {
188; CHECK-LABEL: whilegt_b_ww:
189; CHECK:       // %bb.0:
190; CHECK-NEXT:    whilegt p0.b, w0, w1
191; CHECK-NEXT:    ret
192  %out = call <vscale x 16 x i1> @llvm.aarch64.sve.whilegt.nxv16i1.i32(i32 %a, i32 %b)
193  ret <vscale x 16 x i1> %out
194}
195
196define <vscale x 16 x i1> @whilegt_b_xx(i64 %a, i64 %b) {
197; CHECK-LABEL: whilegt_b_xx:
198; CHECK:       // %bb.0:
199; CHECK-NEXT:    whilegt p0.b, x0, x1
200; CHECK-NEXT:    ret
201  %out = call <vscale x 16 x i1> @llvm.aarch64.sve.whilegt.nxv16i1.i64(i64 %a, i64 %b)
202  ret <vscale x 16 x i1> %out
203}
204
205define <vscale x 8 x i1> @whilegt_h_ww(i32 %a, i32 %b) {
206; CHECK-LABEL: whilegt_h_ww:
207; CHECK:       // %bb.0:
208; CHECK-NEXT:    whilegt p0.h, w0, w1
209; CHECK-NEXT:    ret
210  %out = call <vscale x 8 x i1> @llvm.aarch64.sve.whilegt.nxv8i1.i32(i32 %a, i32 %b)
211  ret <vscale x 8 x i1> %out
212}
213
214define <vscale x 8 x i1> @whilegt_h_xx(i64 %a, i64 %b) {
215; CHECK-LABEL: whilegt_h_xx:
216; CHECK:       // %bb.0:
217; CHECK-NEXT:    whilegt p0.h, x0, x1
218; CHECK-NEXT:    ret
219  %out = call <vscale x 8 x i1> @llvm.aarch64.sve.whilegt.nxv8i1.i64(i64 %a, i64 %b)
220  ret <vscale x 8 x i1> %out
221}
222
223define <vscale x 4 x i1> @whilegt_s_ww(i32 %a, i32 %b) {
224; CHECK-LABEL: whilegt_s_ww:
225; CHECK:       // %bb.0:
226; CHECK-NEXT:    whilegt p0.s, w0, w1
227; CHECK-NEXT:    ret
228  %out = call <vscale x 4 x i1> @llvm.aarch64.sve.whilegt.nxv4i1.i32(i32 %a, i32 %b)
229  ret <vscale x 4 x i1> %out
230}
231
232define <vscale x 4 x i1> @whilegt_s_xx(i64 %a, i64 %b) {
233; CHECK-LABEL: whilegt_s_xx:
234; CHECK:       // %bb.0:
235; CHECK-NEXT:    whilegt p0.s, x0, x1
236; CHECK-NEXT:    ret
237  %out = call <vscale x 4 x i1> @llvm.aarch64.sve.whilegt.nxv4i1.i64(i64 %a, i64 %b)
238  ret <vscale x 4 x i1> %out
239}
240
241define <vscale x 2 x i1> @whilegt_d_ww(i32 %a, i32 %b) {
242; CHECK-LABEL: whilegt_d_ww:
243; CHECK:       // %bb.0:
244; CHECK-NEXT:    whilegt p0.d, w0, w1
245; CHECK-NEXT:    ret
246  %out = call <vscale x 2 x i1> @llvm.aarch64.sve.whilegt.nxv2i1.i32(i32 %a, i32 %b)
247  ret <vscale x 2 x i1> %out
248}
249
250define <vscale x 2 x i1> @whilegt_d_xx(i64 %a, i64 %b) {
251; CHECK-LABEL: whilegt_d_xx:
252; CHECK:       // %bb.0:
253; CHECK-NEXT:    whilegt p0.d, x0, x1
254; CHECK-NEXT:    ret
255  %out = call <vscale x 2 x i1> @llvm.aarch64.sve.whilegt.nxv2i1.i64(i64 %a, i64 %b)
256  ret <vscale x 2 x i1> %out
257}
258
259; Ensure we don't convert constant decrementing while instructions to ptrue.
260define <vscale x 16 x i1> @whilegt_b_ii() {
261; CHECK-LABEL: whilegt_b_ii:
262; CHECK:       // %bb.0: // %entry
263; CHECK-NEXT:    mov w8, #-2 // =0xfffffffe
264; CHECK-NEXT:    mov w9, #3 // =0x3
265; CHECK-NEXT:    whilegt p0.b, w9, w8
266; CHECK-NEXT:    ret
267entry:
268  %out = call <vscale x 16 x i1> @llvm.aarch64.sve.whilegt.nxv16i1.i32(i32 3, i32 -2)
269  ret <vscale x 16 x i1> %out
270}
271
272;
273; WHILEHI
274;
275
276define <vscale x 16 x i1> @whilehi_b_ww(i32 %a, i32 %b) {
277; CHECK-LABEL: whilehi_b_ww:
278; CHECK:       // %bb.0:
279; CHECK-NEXT:    whilehi p0.b, w0, w1
280; CHECK-NEXT:    ret
281  %out = call <vscale x 16 x i1> @llvm.aarch64.sve.whilehi.nxv16i1.i32(i32 %a, i32 %b)
282  ret <vscale x 16 x i1> %out
283}
284
285define <vscale x 16 x i1> @whilehi_b_xx(i64 %a, i64 %b) {
286; CHECK-LABEL: whilehi_b_xx:
287; CHECK:       // %bb.0:
288; CHECK-NEXT:    whilehi p0.b, x0, x1
289; CHECK-NEXT:    ret
290  %out = call <vscale x 16 x i1> @llvm.aarch64.sve.whilehi.nxv16i1.i64(i64 %a, i64 %b)
291  ret <vscale x 16 x i1> %out
292}
293
294define <vscale x 8 x i1> @whilehi_h_ww(i32 %a, i32 %b) {
295; CHECK-LABEL: whilehi_h_ww:
296; CHECK:       // %bb.0:
297; CHECK-NEXT:    whilehi p0.h, w0, w1
298; CHECK-NEXT:    ret
299  %out = call <vscale x 8 x i1> @llvm.aarch64.sve.whilehi.nxv8i1.i32(i32 %a, i32 %b)
300  ret <vscale x 8 x i1> %out
301}
302
303define <vscale x 8 x i1> @whilehi_h_xx(i64 %a, i64 %b) {
304; CHECK-LABEL: whilehi_h_xx:
305; CHECK:       // %bb.0:
306; CHECK-NEXT:    whilehi p0.h, x0, x1
307; CHECK-NEXT:    ret
308  %out = call <vscale x 8 x i1> @llvm.aarch64.sve.whilehi.nxv8i1.i64(i64 %a, i64 %b)
309  ret <vscale x 8 x i1> %out
310}
311
312define <vscale x 4 x i1> @whilehi_s_ww(i32 %a, i32 %b) {
313; CHECK-LABEL: whilehi_s_ww:
314; CHECK:       // %bb.0:
315; CHECK-NEXT:    whilehi p0.s, w0, w1
316; CHECK-NEXT:    ret
317  %out = call <vscale x 4 x i1> @llvm.aarch64.sve.whilehi.nxv4i1.i32(i32 %a, i32 %b)
318  ret <vscale x 4 x i1> %out
319}
320
321define <vscale x 4 x i1> @whilehi_s_xx(i64 %a, i64 %b) {
322; CHECK-LABEL: whilehi_s_xx:
323; CHECK:       // %bb.0:
324; CHECK-NEXT:    whilehi p0.s, x0, x1
325; CHECK-NEXT:    ret
326  %out = call <vscale x 4 x i1> @llvm.aarch64.sve.whilehi.nxv4i1.i64(i64 %a, i64 %b)
327  ret <vscale x 4 x i1> %out
328}
329
330define <vscale x 2 x i1> @whilehi_d_ww(i32 %a, i32 %b) {
331; CHECK-LABEL: whilehi_d_ww:
332; CHECK:       // %bb.0:
333; CHECK-NEXT:    whilehi p0.d, w0, w1
334; CHECK-NEXT:    ret
335  %out = call <vscale x 2 x i1> @llvm.aarch64.sve.whilehi.nxv2i1.i32(i32 %a, i32 %b)
336  ret <vscale x 2 x i1> %out
337}
338
339define <vscale x 2 x i1> @whilehi_d_xx(i64 %a, i64 %b) {
340; CHECK-LABEL: whilehi_d_xx:
341; CHECK:       // %bb.0:
342; CHECK-NEXT:    whilehi p0.d, x0, x1
343; CHECK-NEXT:    ret
344  %out = call <vscale x 2 x i1> @llvm.aarch64.sve.whilehi.nxv2i1.i64(i64 %a, i64 %b)
345  ret <vscale x 2 x i1> %out
346}
347
348; Ensure we don't convert constant decrementing while instructions to ptrue.
349define <vscale x 16 x i1> @whilehi_b_ii() {
350; CHECK-LABEL: whilehi_b_ii:
351; CHECK:       // %bb.0: // %entry
352; CHECK-NEXT:    mov w8, #2 // =0x2
353; CHECK-NEXT:    mov w9, #8 // =0x8
354; CHECK-NEXT:    whilehi p0.b, x9, x8
355; CHECK-NEXT:    ret
356entry:
357  %out = call <vscale x 16 x i1> @llvm.aarch64.sve.whilehi.nxv16i1.i64(i64 8, i64 2)
358  ret <vscale x 16 x i1> %out
359}
360
361declare <vscale x 16 x i1> @llvm.aarch64.sve.whilege.nxv16i1.i32(i32, i32)
362declare <vscale x 16 x i1> @llvm.aarch64.sve.whilege.nxv16i1.i64(i64, i64)
363declare <vscale x 8 x i1> @llvm.aarch64.sve.whilege.nxv8i1.i32(i32, i32)
364declare <vscale x 8 x i1> @llvm.aarch64.sve.whilege.nxv8i1.i64(i64, i64)
365declare <vscale x 4 x i1> @llvm.aarch64.sve.whilege.nxv4i1.i32(i32, i32)
366declare <vscale x 4 x i1> @llvm.aarch64.sve.whilege.nxv4i1.i64(i64, i64)
367declare <vscale x 2 x i1> @llvm.aarch64.sve.whilege.nxv2i1.i32(i32, i32)
368declare <vscale x 2 x i1> @llvm.aarch64.sve.whilege.nxv2i1.i64(i64, i64)
369
370declare <vscale x 16 x i1> @llvm.aarch64.sve.whilehs.nxv16i1.i32(i32, i32)
371declare <vscale x 16 x i1> @llvm.aarch64.sve.whilehs.nxv16i1.i64(i64, i64)
372declare <vscale x 8 x i1> @llvm.aarch64.sve.whilehs.nxv8i1.i32(i32, i32)
373declare <vscale x 8 x i1> @llvm.aarch64.sve.whilehs.nxv8i1.i64(i64, i64)
374declare <vscale x 4 x i1> @llvm.aarch64.sve.whilehs.nxv4i1.i32(i32, i32)
375declare <vscale x 4 x i1> @llvm.aarch64.sve.whilehs.nxv4i1.i64(i64, i64)
376declare <vscale x 2 x i1> @llvm.aarch64.sve.whilehs.nxv2i1.i32(i32, i32)
377declare <vscale x 2 x i1> @llvm.aarch64.sve.whilehs.nxv2i1.i64(i64, i64)
378
379declare <vscale x 16 x i1> @llvm.aarch64.sve.whilegt.nxv16i1.i32(i32, i32)
380declare <vscale x 16 x i1> @llvm.aarch64.sve.whilegt.nxv16i1.i64(i64, i64)
381declare <vscale x 8 x i1> @llvm.aarch64.sve.whilegt.nxv8i1.i32(i32, i32)
382declare <vscale x 8 x i1> @llvm.aarch64.sve.whilegt.nxv8i1.i64(i64, i64)
383declare <vscale x 4 x i1> @llvm.aarch64.sve.whilegt.nxv4i1.i32(i32, i32)
384declare <vscale x 4 x i1> @llvm.aarch64.sve.whilegt.nxv4i1.i64(i64, i64)
385declare <vscale x 2 x i1> @llvm.aarch64.sve.whilegt.nxv2i1.i32(i32, i32)
386declare <vscale x 2 x i1> @llvm.aarch64.sve.whilegt.nxv2i1.i64(i64, i64)
387
388declare <vscale x 16 x i1> @llvm.aarch64.sve.whilehi.nxv16i1.i32(i32, i32)
389declare <vscale x 16 x i1> @llvm.aarch64.sve.whilehi.nxv16i1.i64(i64, i64)
390declare <vscale x 8 x i1> @llvm.aarch64.sve.whilehi.nxv8i1.i32(i32, i32)
391declare <vscale x 8 x i1> @llvm.aarch64.sve.whilehi.nxv8i1.i64(i64, i64)
392declare <vscale x 4 x i1> @llvm.aarch64.sve.whilehi.nxv4i1.i32(i32, i32)
393declare <vscale x 4 x i1> @llvm.aarch64.sve.whilehi.nxv4i1.i64(i64, i64)
394declare <vscale x 2 x i1> @llvm.aarch64.sve.whilehi.nxv2i1.i32(i32, i32)
395declare <vscale x 2 x i1> @llvm.aarch64.sve.whilehi.nxv2i1.i64(i64, i64)
396