xref: /llvm-project/llvm/test/CodeGen/AArch64/sve2-intrinsics-vec-hist-count.ll (revision fadea4413ecbfffa4d28ad8298e0628165b543f1) 
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve2 < %s | FileCheck %s
3
4;
5; HISTCNT
6;
7
8define <vscale x 4 x i32> @histcnt_i32(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %a, <vscale x 4 x i32> %b) {
9; CHECK-LABEL: histcnt_i32:
10; CHECK:       // %bb.0:
11; CHECK-NEXT:    histcnt z0.s, p0/z, z0.s, z1.s
12; CHECK-NEXT:    ret
13  %out = call <vscale x 4 x i32> @llvm.aarch64.sve.histcnt.nxv4i32(<vscale x 4 x i1> %pg,
14                                                                   <vscale x 4 x i32> %a,
15                                                                   <vscale x 4 x i32> %b)
16  ret <vscale x 4 x i32> %out
17}
18
19define <vscale x 2 x i64> @histcnt_i64(<vscale x 2 x i1> %pg, <vscale x 2 x i64> %a, <vscale x 2 x i64> %b) {
20; CHECK-LABEL: histcnt_i64:
21; CHECK:       // %bb.0:
22; CHECK-NEXT:    histcnt z0.d, p0/z, z0.d, z1.d
23; CHECK-NEXT:    ret
24  %out = call <vscale x 2 x i64> @llvm.aarch64.sve.histcnt.nxv2i64(<vscale x 2 x i1> %pg,
25                                                                   <vscale x 2 x i64> %a,
26                                                                   <vscale x 2 x i64> %b)
27  ret <vscale x 2 x i64> %out
28}
29
30;
31; HISTSEG
32;
33
34define <vscale x 16 x i8> @histseg(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b) {
35; CHECK-LABEL: histseg:
36; CHECK:       // %bb.0:
37; CHECK-NEXT:    histseg z0.b, z0.b, z1.b
38; CHECK-NEXT:    ret
39  %out = call <vscale x 16 x i8> @llvm.aarch64.sve.histseg.nxv16i8(<vscale x 16 x i8> %a,
40                                                                   <vscale x 16 x i8> %b)
41  ret <vscale x 16 x i8> %out
42}
43
44declare <vscale x 4 x i32> @llvm.aarch64.sve.histcnt.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>)
45declare <vscale x 2 x i64> @llvm.aarch64.sve.histcnt.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>, <vscale x 2 x i64>)
46declare <vscale x 16 x i8> @llvm.aarch64.sve.histseg.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i8>)
47