xref: /llvm-project/llvm/test/CodeGen/AArch64/sve2-intrinsics-unary-narrowing.ll (revision 62baf21daa377c4ec1a641b26931063c1117d262) 
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve2 < %s | FileCheck %s
3; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sme -force-streaming < %s | FileCheck %s
4
5;
6; SQXTNB
7;
8
9define <vscale x 16 x i8> @sqxtnb_h(<vscale x 8 x i16> %a) {
10; CHECK-LABEL: sqxtnb_h:
11; CHECK:       // %bb.0:
12; CHECK-NEXT:    sqxtnb z0.b, z0.h
13; CHECK-NEXT:    ret
14  %out = call <vscale x 16 x i8> @llvm.aarch64.sve.sqxtnb.nxv8i16(<vscale x 8 x i16> %a)
15  ret <vscale x 16 x i8> %out
16}
17
18define <vscale x 8 x i16> @sqxtnb_s(<vscale x 4 x i32> %a) {
19; CHECK-LABEL: sqxtnb_s:
20; CHECK:       // %bb.0:
21; CHECK-NEXT:    sqxtnb z0.h, z0.s
22; CHECK-NEXT:    ret
23  %out = call <vscale x 8 x i16> @llvm.aarch64.sve.sqxtnb.nxv4i32(<vscale x 4 x i32> %a)
24  ret <vscale x 8 x i16> %out
25}
26
27define <vscale x 4 x i32> @sqxtnb_d(<vscale x 2 x i64> %a) {
28; CHECK-LABEL: sqxtnb_d:
29; CHECK:       // %bb.0:
30; CHECK-NEXT:    sqxtnb z0.s, z0.d
31; CHECK-NEXT:    ret
32  %out = call <vscale x 4 x i32> @llvm.aarch64.sve.sqxtnb.nxv2i64(<vscale x 2 x i64> %a)
33  ret <vscale x 4 x i32> %out
34}
35
36;
37; UQXTNB
38;
39
40define <vscale x 16 x i8> @uqxtnb_h(<vscale x 8 x i16> %a) {
41; CHECK-LABEL: uqxtnb_h:
42; CHECK:       // %bb.0:
43; CHECK-NEXT:    uqxtnb z0.b, z0.h
44; CHECK-NEXT:    ret
45  %out = call <vscale x 16 x i8> @llvm.aarch64.sve.uqxtnb.nxv8i16(<vscale x 8 x i16> %a)
46  ret <vscale x 16 x i8> %out
47}
48
49define <vscale x 8 x i16> @uqxtnb_s(<vscale x 4 x i32> %a) {
50; CHECK-LABEL: uqxtnb_s:
51; CHECK:       // %bb.0:
52; CHECK-NEXT:    uqxtnb z0.h, z0.s
53; CHECK-NEXT:    ret
54  %out = call <vscale x 8 x i16> @llvm.aarch64.sve.uqxtnb.nxv4i32(<vscale x 4 x i32> %a)
55  ret <vscale x 8 x i16> %out
56}
57
58define <vscale x 4 x i32> @uqxtnb_d(<vscale x 2 x i64> %a) {
59; CHECK-LABEL: uqxtnb_d:
60; CHECK:       // %bb.0:
61; CHECK-NEXT:    uqxtnb z0.s, z0.d
62; CHECK-NEXT:    ret
63  %out = call <vscale x 4 x i32> @llvm.aarch64.sve.uqxtnb.nxv2i64(<vscale x 2 x i64> %a)
64  ret <vscale x 4 x i32> %out
65}
66
67;
68; SQXTUNB
69;
70
71define <vscale x 16 x i8> @sqxtunb_h(<vscale x 8 x i16> %a) {
72; CHECK-LABEL: sqxtunb_h:
73; CHECK:       // %bb.0:
74; CHECK-NEXT:    sqxtunb z0.b, z0.h
75; CHECK-NEXT:    ret
76  %out = call <vscale x 16 x i8> @llvm.aarch64.sve.sqxtunb.nxv8i16(<vscale x 8 x i16> %a)
77  ret <vscale x 16 x i8> %out
78}
79
80define <vscale x 8 x i16> @sqxtunb_s(<vscale x 4 x i32> %a) {
81; CHECK-LABEL: sqxtunb_s:
82; CHECK:       // %bb.0:
83; CHECK-NEXT:    sqxtunb z0.h, z0.s
84; CHECK-NEXT:    ret
85  %out = call <vscale x 8 x i16> @llvm.aarch64.sve.sqxtunb.nxv4i32(<vscale x 4 x i32> %a)
86  ret <vscale x 8 x i16> %out
87}
88
89define <vscale x 4 x i32> @sqxtunb_d(<vscale x 2 x i64> %a) {
90; CHECK-LABEL: sqxtunb_d:
91; CHECK:       // %bb.0:
92; CHECK-NEXT:    sqxtunb z0.s, z0.d
93; CHECK-NEXT:    ret
94  %out = call <vscale x 4 x i32> @llvm.aarch64.sve.sqxtunb.nxv2i64(<vscale x 2 x i64> %a)
95  ret <vscale x 4 x i32> %out
96}
97
98;
99; SQXTNT
100;
101
102define <vscale x 16 x i8> @sqxtnt_h(<vscale x 16 x i8> %a, <vscale x 8 x i16> %b) {
103; CHECK-LABEL: sqxtnt_h:
104; CHECK:       // %bb.0:
105; CHECK-NEXT:    sqxtnt z0.b, z1.h
106; CHECK-NEXT:    ret
107  %out = call <vscale x 16 x i8> @llvm.aarch64.sve.sqxtnt.nxv8i16(<vscale x 16 x i8> %a,
108                                                                  <vscale x 8 x i16> %b)
109  ret <vscale x 16 x i8> %out
110}
111
112define <vscale x 8 x i16> @sqxtnt_s(<vscale x 8 x i16> %a, <vscale x 4 x i32> %b) {
113; CHECK-LABEL: sqxtnt_s:
114; CHECK:       // %bb.0:
115; CHECK-NEXT:    sqxtnt z0.h, z1.s
116; CHECK-NEXT:    ret
117  %out = call <vscale x 8 x i16> @llvm.aarch64.sve.sqxtnt.nxv4i32(<vscale x 8 x i16> %a,
118                                                                  <vscale x 4 x i32> %b)
119  ret <vscale x 8 x i16> %out
120}
121
122define <vscale x 4 x i32> @sqxtnt_d(<vscale x 4 x i32> %a, <vscale x 2 x i64> %b) {
123; CHECK-LABEL: sqxtnt_d:
124; CHECK:       // %bb.0:
125; CHECK-NEXT:    sqxtnt z0.s, z1.d
126; CHECK-NEXT:    ret
127  %out = call <vscale x 4 x i32> @llvm.aarch64.sve.sqxtnt.nxv2i64(<vscale x 4 x i32> %a,
128                                                                  <vscale x 2 x i64> %b)
129  ret <vscale x 4 x i32> %out
130}
131
132;
133; UQXTNT
134;
135
136define <vscale x 16 x i8> @uqxtnt_h(<vscale x 16 x i8> %a, <vscale x 8 x i16> %b) {
137; CHECK-LABEL: uqxtnt_h:
138; CHECK:       // %bb.0:
139; CHECK-NEXT:    uqxtnt z0.b, z1.h
140; CHECK-NEXT:    ret
141  %out = call <vscale x 16 x i8> @llvm.aarch64.sve.uqxtnt.nxv8i16(<vscale x 16 x i8> %a,
142                                                                  <vscale x 8 x i16> %b)
143  ret <vscale x 16 x i8> %out
144}
145
146define <vscale x 8 x i16> @uqxtnt_s(<vscale x 8 x i16> %a, <vscale x 4 x i32> %b) {
147; CHECK-LABEL: uqxtnt_s:
148; CHECK:       // %bb.0:
149; CHECK-NEXT:    uqxtnt z0.h, z1.s
150; CHECK-NEXT:    ret
151  %out = call <vscale x 8 x i16> @llvm.aarch64.sve.uqxtnt.nxv4i32(<vscale x 8 x i16> %a,
152                                                                  <vscale x 4 x i32> %b)
153  ret <vscale x 8 x i16> %out
154}
155
156define <vscale x 4 x i32> @uqxtnt_d(<vscale x 4 x i32> %a, <vscale x 2 x i64> %b) {
157; CHECK-LABEL: uqxtnt_d:
158; CHECK:       // %bb.0:
159; CHECK-NEXT:    uqxtnt z0.s, z1.d
160; CHECK-NEXT:    ret
161  %out = call <vscale x 4 x i32> @llvm.aarch64.sve.uqxtnt.nxv2i64(<vscale x 4 x i32> %a,
162                                                                  <vscale x 2 x i64> %b)
163  ret <vscale x 4 x i32> %out
164}
165
166;
167; SQXTUNT
168;
169
170define <vscale x 16 x i8> @sqxtunt_h(<vscale x 16 x i8> %a, <vscale x 8 x i16> %b) {
171; CHECK-LABEL: sqxtunt_h:
172; CHECK:       // %bb.0:
173; CHECK-NEXT:    sqxtunt z0.b, z1.h
174; CHECK-NEXT:    ret
175  %out = call <vscale x 16 x i8> @llvm.aarch64.sve.sqxtunt.nxv8i16(<vscale x 16 x i8> %a,
176                                                                   <vscale x 8 x i16> %b)
177  ret <vscale x 16 x i8> %out
178}
179
180define <vscale x 8 x i16> @sqxtunt_s(<vscale x 8 x i16> %a, <vscale x 4 x i32> %b) {
181; CHECK-LABEL: sqxtunt_s:
182; CHECK:       // %bb.0:
183; CHECK-NEXT:    sqxtunt z0.h, z1.s
184; CHECK-NEXT:    ret
185  %out = call <vscale x 8 x i16> @llvm.aarch64.sve.sqxtunt.nxv4i32(<vscale x 8 x i16> %a,
186                                                                   <vscale x 4 x i32> %b)
187  ret <vscale x 8 x i16> %out
188}
189
190define <vscale x 4 x i32> @sqxtunt_d(<vscale x 4 x i32> %a, <vscale x 2 x i64> %b) {
191; CHECK-LABEL: sqxtunt_d:
192; CHECK:       // %bb.0:
193; CHECK-NEXT:    sqxtunt z0.s, z1.d
194; CHECK-NEXT:    ret
195  %out = call <vscale x 4 x i32> @llvm.aarch64.sve.sqxtunt.nxv2i64(<vscale x 4 x i32> %a,
196                                                                   <vscale x 2 x i64> %b)
197  ret <vscale x 4 x i32> %out
198}
199
200declare <vscale x 16 x i8> @llvm.aarch64.sve.sqxtnb.nxv8i16(<vscale x 8 x i16>)
201declare <vscale x 8 x i16> @llvm.aarch64.sve.sqxtnb.nxv4i32(<vscale x 4 x i32>)
202declare <vscale x 4 x i32> @llvm.aarch64.sve.sqxtnb.nxv2i64(<vscale x 2 x i64>)
203
204declare <vscale x 16 x i8> @llvm.aarch64.sve.uqxtnb.nxv8i16(<vscale x 8 x i16>)
205declare <vscale x 8 x i16> @llvm.aarch64.sve.uqxtnb.nxv4i32(<vscale x 4 x i32>)
206declare <vscale x 4 x i32> @llvm.aarch64.sve.uqxtnb.nxv2i64(<vscale x 2 x i64>)
207
208declare <vscale x 16 x i8> @llvm.aarch64.sve.sqxtunb.nxv8i16(<vscale x 8 x i16>)
209declare <vscale x 8 x i16> @llvm.aarch64.sve.sqxtunb.nxv4i32(<vscale x 4 x i32>)
210declare <vscale x 4 x i32> @llvm.aarch64.sve.sqxtunb.nxv2i64(<vscale x 2 x i64>)
211
212declare <vscale x 16 x i8> @llvm.aarch64.sve.sqxtnt.nxv8i16(<vscale x 16 x i8>, <vscale x 8 x i16>)
213declare <vscale x 8 x i16> @llvm.aarch64.sve.sqxtnt.nxv4i32(<vscale x 8 x i16>, <vscale x 4 x i32>)
214declare <vscale x 4 x i32> @llvm.aarch64.sve.sqxtnt.nxv2i64(<vscale x 4 x i32>, <vscale x 2 x i64>)
215
216declare <vscale x 16 x i8> @llvm.aarch64.sve.uqxtnt.nxv8i16(<vscale x 16 x i8>, <vscale x 8 x i16>)
217declare <vscale x 8 x i16> @llvm.aarch64.sve.uqxtnt.nxv4i32(<vscale x 8 x i16>, <vscale x 4 x i32>)
218declare <vscale x 4 x i32> @llvm.aarch64.sve.uqxtnt.nxv2i64(<vscale x 4 x i32>, <vscale x 2 x i64>)
219
220declare <vscale x 16 x i8> @llvm.aarch64.sve.sqxtunt.nxv8i16(<vscale x 16 x i8>, <vscale x 8 x i16>)
221declare <vscale x 8 x i16> @llvm.aarch64.sve.sqxtunt.nxv4i32(<vscale x 8 x i16>, <vscale x 4 x i32>)
222declare <vscale x 4 x i32> @llvm.aarch64.sve.sqxtunt.nxv2i64(<vscale x 4 x i32>, <vscale x 2 x i64>)
223