xref: /llvm-project/llvm/test/CodeGen/AArch64/sve2-intrinsics-int-mul-lane.ll (revision 62baf21daa377c4ec1a641b26931063c1117d262) 
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve2 < %s | FileCheck %s
3; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sme -force-streaming < %s | FileCheck %s
4
5;
6; MUL
7;
8
9define <vscale x 2 x i64> @mul_lane_d(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b) {
10; CHECK-LABEL: mul_lane_d:
11; CHECK:       // %bb.0:
12; CHECK-NEXT:    mul z0.d, z0.d, z1.d[1]
13; CHECK-NEXT:    ret
14  %out = call <vscale x 2 x i64> @llvm.aarch64.sve.mul.lane.nxv2i64(<vscale x 2 x i64> %a,
15                                                                    <vscale x 2 x i64> %b,
16                                                                    i32 1)
17  ret <vscale x 2 x i64> %out
18}
19
20define <vscale x 4 x i32> @mul_lane_s(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) {
21; CHECK-LABEL: mul_lane_s:
22; CHECK:       // %bb.0:
23; CHECK-NEXT:    mul z0.s, z0.s, z1.s[1]
24; CHECK-NEXT:    ret
25  %out = call <vscale x 4 x i32> @llvm.aarch64.sve.mul.lane.nxv4i32(<vscale x 4 x i32> %a,
26                                                                    <vscale x 4 x i32> %b,
27                                                                    i32 1)
28  ret <vscale x 4 x i32> %out
29}
30
31define <vscale x 8 x i16> @mul_lane_h(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b) {
32; CHECK-LABEL: mul_lane_h:
33; CHECK:       // %bb.0:
34; CHECK-NEXT:    mul z0.h, z0.h, z1.h[1]
35; CHECK-NEXT:    ret
36  %out = call <vscale x 8 x i16> @llvm.aarch64.sve.mul.lane.nxv8i16(<vscale x 8 x i16> %a,
37                                                                    <vscale x 8 x i16> %b,
38                                                                    i32 1)
39  ret <vscale x 8 x i16> %out
40}
41
42;
43; MLA
44;
45
46define <vscale x 2 x i64> @mla_lane_d(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b, <vscale x 2 x i64> %c) {
47; CHECK-LABEL: mla_lane_d:
48; CHECK:       // %bb.0:
49; CHECK-NEXT:    mla z0.d, z1.d, z2.d[1]
50; CHECK-NEXT:    ret
51  %out = call <vscale x 2 x i64> @llvm.aarch64.sve.mla.lane.nxv2i64(<vscale x 2 x i64> %a,
52                                                                    <vscale x 2 x i64> %b,
53                                                                    <vscale x 2 x i64> %c,
54                                                                    i32 1)
55  ret <vscale x 2 x i64> %out
56}
57
58define <vscale x 4 x i32> @mla_lane_s(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b, <vscale x 4 x i32> %c) {
59; CHECK-LABEL: mla_lane_s:
60; CHECK:       // %bb.0:
61; CHECK-NEXT:    mla z0.s, z1.s, z2.s[1]
62; CHECK-NEXT:    ret
63  %out = call <vscale x 4 x i32> @llvm.aarch64.sve.mla.lane.nxv4i32(<vscale x 4 x i32> %a,
64                                                                    <vscale x 4 x i32> %b,
65                                                                    <vscale x 4 x i32> %c,
66                                                                    i32 1)
67  ret <vscale x 4 x i32> %out
68}
69
70define <vscale x 8 x i16> @mla_lane_h(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b, <vscale x 8 x i16> %c) {
71; CHECK-LABEL: mla_lane_h:
72; CHECK:       // %bb.0:
73; CHECK-NEXT:    mla z0.h, z1.h, z2.h[1]
74; CHECK-NEXT:    ret
75  %out = call <vscale x 8 x i16> @llvm.aarch64.sve.mla.lane.nxv8i16(<vscale x 8 x i16> %a,
76                                                                    <vscale x 8 x i16> %b,
77                                                                    <vscale x 8 x i16> %c,
78                                                                    i32 1)
79  ret <vscale x 8 x i16> %out
80}
81
82;
83; MLS
84;
85
86define <vscale x 2 x i64> @mls_lane_d(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b, <vscale x 2 x i64> %c) {
87; CHECK-LABEL: mls_lane_d:
88; CHECK:       // %bb.0:
89; CHECK-NEXT:    mls z0.d, z1.d, z2.d[1]
90; CHECK-NEXT:    ret
91  %out = call <vscale x 2 x i64> @llvm.aarch64.sve.mls.lane.nxv2i64(<vscale x 2 x i64> %a,
92                                                                    <vscale x 2 x i64> %b,
93                                                                    <vscale x 2 x i64> %c,
94                                                                    i32 1)
95  ret <vscale x 2 x i64> %out
96}
97
98define <vscale x 4 x i32> @mls_lane_s(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b, <vscale x 4 x i32> %c) {
99; CHECK-LABEL: mls_lane_s:
100; CHECK:       // %bb.0:
101; CHECK-NEXT:    mls z0.s, z1.s, z2.s[1]
102; CHECK-NEXT:    ret
103  %out = call <vscale x 4 x i32> @llvm.aarch64.sve.mls.lane.nxv4i32(<vscale x 4 x i32> %a,
104                                                                    <vscale x 4 x i32> %b,
105                                                                    <vscale x 4 x i32> %c,
106                                                                    i32 1)
107  ret <vscale x 4 x i32> %out
108}
109
110define <vscale x 8 x i16> @mls_lane_h(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b, <vscale x 8 x i16> %c) {
111; CHECK-LABEL: mls_lane_h:
112; CHECK:       // %bb.0:
113; CHECK-NEXT:    mls z0.h, z1.h, z2.h[1]
114; CHECK-NEXT:    ret
115  %out = call <vscale x 8 x i16> @llvm.aarch64.sve.mls.lane.nxv8i16(<vscale x 8 x i16> %a,
116                                                                    <vscale x 8 x i16> %b,
117                                                                    <vscale x 8 x i16> %c,
118                                                                    i32 1)
119  ret <vscale x 8 x i16> %out
120}
121
122declare <vscale x 8 x i16> @llvm.aarch64.sve.mul.lane.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i16>, i32)
123declare <vscale x 4 x i32> @llvm.aarch64.sve.mul.lane.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>, i32)
124declare <vscale x 2 x i64> @llvm.aarch64.sve.mul.lane.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>, i32)
125declare <vscale x 8 x i16> @llvm.aarch64.sve.mla.lane.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, i32)
126declare <vscale x 4 x i32> @llvm.aarch64.sve.mla.lane.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, i32)
127declare <vscale x 2 x i64> @llvm.aarch64.sve.mla.lane.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, i32)
128declare <vscale x 8 x i16> @llvm.aarch64.sve.mls.lane.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, i32)
129declare <vscale x 4 x i32> @llvm.aarch64.sve.mls.lane.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, i32)
130declare <vscale x 2 x i64> @llvm.aarch64.sve.mls.lane.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, i32)
131