xref: /llvm-project/llvm/test/CodeGen/AArch64/sve2-intrinsics-fp-int-binary-logarithm.ll (revision 62baf21daa377c4ec1a641b26931063c1117d262) 
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve2 < %s | FileCheck %s
3; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sme -force-streaming < %s | FileCheck %s
4
5;
6; FLOGB
7;
8
9define <vscale x 8 x i16> @flogb_f16(<vscale x 8 x i16> %a, <vscale x 8 x i1> %pg, <vscale x 8 x half> %b) {
10; CHECK-LABEL: flogb_f16:
11; CHECK:       // %bb.0:
12; CHECK-NEXT:    flogb z0.h, p0/m, z1.h
13; CHECK-NEXT:    ret
14  %out = call <vscale x 8 x i16> @llvm.aarch64.sve.flogb.nxv8f16(<vscale x 8 x i16> %a,
15                                                                 <vscale x 8 x i1> %pg,
16                                                                 <vscale x 8 x half> %b)
17  ret <vscale x 8 x i16> %out
18}
19
20define <vscale x 4 x i32> @flogb_f32(<vscale x 4 x i32> %a, <vscale x 4 x i1> %pg, <vscale x 4 x float> %b) {
21; CHECK-LABEL: flogb_f32:
22; CHECK:       // %bb.0:
23; CHECK-NEXT:    flogb z0.s, p0/m, z1.s
24; CHECK-NEXT:    ret
25  %out = call <vscale x 4 x i32> @llvm.aarch64.sve.flogb.nxv4f32(<vscale x 4 x i32> %a,
26                                                                 <vscale x 4 x i1> %pg,
27                                                                 <vscale x 4 x float> %b)
28  ret <vscale x 4 x i32> %out
29}
30
31define <vscale x 2 x i64> @flogb_f64(<vscale x 2 x i64> %a, <vscale x 2 x i1> %pg, <vscale x 2 x double> %b) {
32; CHECK-LABEL: flogb_f64:
33; CHECK:       // %bb.0:
34; CHECK-NEXT:    flogb z0.d, p0/m, z1.d
35; CHECK-NEXT:    ret
36  %out = call <vscale x 2 x i64> @llvm.aarch64.sve.flogb.nxv2f64(<vscale x 2 x i64> %a,
37                                                                 <vscale x 2 x i1> %pg,
38                                                                 <vscale x 2 x double> %b)
39  ret <vscale x 2 x i64> %out
40}
41
42declare <vscale x 8 x i16> @llvm.aarch64.sve.flogb.nxv8f16(<vscale x 8 x i16>, <vscale x 8 x i1>, <vscale x 8 x half>)
43declare <vscale x 4 x i32> @llvm.aarch64.sve.flogb.nxv4f32(<vscale x 4 x i32>, <vscale x 4 x i1>, <vscale x 4 x float>)
44declare <vscale x 2 x i64> @llvm.aarch64.sve.flogb.nxv2f64(<vscale x 2 x i64>, <vscale x 2 x i1>, <vscale x 2 x double>)
45