xref: /llvm-project/llvm/test/CodeGen/AArch64/sve2-intrinsics-fp-int-binary-logarithm-zeroing.ll (revision 39af4659f24026fd3c667ce50a9e798485e1ae98)
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve2 -mattr=+use-experimental-zeroing-pseudos < %s | FileCheck %s
3
4;
5; FLOGB
6;
7
8; NOTE: The %unused paramter ensures z0 is free, leading to a simpler test.
9define <vscale x 8 x i16> @flogb_f16(<vscale x 8 x i16> %unused, <vscale x 8 x i1> %pg, <vscale x 8 x half> %a) {
10; CHECK-LABEL: flogb_f16:
11; CHECK:       // %bb.0:
12; CHECK-NEXT:    movprfx z0.h, p0/z, z1.h
13; CHECK-NEXT:    flogb z0.h, p0/m, z1.h
14; CHECK-NEXT:    ret
15  %out = call <vscale x 8 x i16> @llvm.aarch64.sve.flogb.nxv8f16(<vscale x 8 x i16> zeroinitializer,
16                                                                 <vscale x 8 x i1> %pg,
17                                                                 <vscale x 8 x half> %a)
18  ret <vscale x 8 x i16> %out
19}
20
21define <vscale x 4 x i32> @flogb_f32(<vscale x 4 x i32> %unused, <vscale x 4 x i1> %pg, <vscale x 4 x float> %a) {
22; CHECK-LABEL: flogb_f32:
23; CHECK:       // %bb.0:
24; CHECK-NEXT:    movprfx z0.s, p0/z, z1.s
25; CHECK-NEXT:    flogb z0.s, p0/m, z1.s
26; CHECK-NEXT:    ret
27  %out = call <vscale x 4 x i32> @llvm.aarch64.sve.flogb.nxv4f32(<vscale x 4 x i32> zeroinitializer,
28                                                                 <vscale x 4 x i1> %pg,
29                                                                 <vscale x 4 x float> %a)
30  ret <vscale x 4 x i32> %out
31}
32
33define <vscale x 2 x i64> @flogb_f64(<vscale x 2 x i64> %unused, <vscale x 2 x i1> %pg, <vscale x 2 x double> %a) {
34; CHECK-LABEL: flogb_f64:
35; CHECK:       // %bb.0:
36; CHECK-NEXT:    movprfx z0.d, p0/z, z1.d
37; CHECK-NEXT:    flogb z0.d, p0/m, z1.d
38; CHECK-NEXT:    ret
39  %out = call <vscale x 2 x i64> @llvm.aarch64.sve.flogb.nxv2f64(<vscale x 2 x i64> zeroinitializer,
40                                                                 <vscale x 2 x i1> %pg,
41                                                                 <vscale x 2 x double> %a)
42  ret <vscale x 2 x i64> %out
43}
44
45declare <vscale x 8 x i16> @llvm.aarch64.sve.flogb.nxv8f16(<vscale x 8 x i16>, <vscale x 8 x i1>, <vscale x 8 x half>)
46declare <vscale x 4 x i32> @llvm.aarch64.sve.flogb.nxv4f32(<vscale x 4 x i32>, <vscale x 4 x i1>, <vscale x 4 x float>)
47declare <vscale x 2 x i64> @llvm.aarch64.sve.flogb.nxv2f64(<vscale x 2 x i64>, <vscale x 2 x i1>, <vscale x 2 x double>)
48