xref: /llvm-project/llvm/test/CodeGen/AArch64/sve2-intrinsics-bit-permutation.ll (revision fadea4413ecbfffa4d28ad8298e0628165b543f1) 
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve2,+sve2-bitperm < %s | FileCheck %s
3
4;
5; BDEP
6;
7
8define <vscale x 16 x i8> @bdep_nxv16i8(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b) {
9; CHECK-LABEL: bdep_nxv16i8:
10; CHECK:       // %bb.0:
11; CHECK-NEXT:    bdep z0.b, z0.b, z1.b
12; CHECK-NEXT:    ret
13  %out = call <vscale x 16 x i8> @llvm.aarch64.sve.bdep.x.nx16i8(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b)
14  ret <vscale x 16 x i8> %out
15}
16
17define <vscale x 8 x i16> @bdep_nxv8i16(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b) {
18; CHECK-LABEL: bdep_nxv8i16:
19; CHECK:       // %bb.0:
20; CHECK-NEXT:    bdep z0.h, z0.h, z1.h
21; CHECK-NEXT:    ret
22  %out = call <vscale x 8 x i16> @llvm.aarch64.sve.bdep.x.nx8i16(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b)
23  ret <vscale x 8 x i16> %out
24}
25
26define <vscale x 4 x i32> @bdep_nxv4i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) {
27; CHECK-LABEL: bdep_nxv4i32:
28; CHECK:       // %bb.0:
29; CHECK-NEXT:    bdep z0.s, z0.s, z1.s
30; CHECK-NEXT:    ret
31  %out = call <vscale x 4 x i32> @llvm.aarch64.sve.bdep.x.nx4i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b)
32  ret <vscale x 4 x i32> %out
33}
34
35define <vscale x 2 x i64> @bdep_nxv2i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b) {
36; CHECK-LABEL: bdep_nxv2i64:
37; CHECK:       // %bb.0:
38; CHECK-NEXT:    bdep z0.d, z0.d, z1.d
39; CHECK-NEXT:    ret
40  %out = call <vscale x 2 x i64> @llvm.aarch64.sve.bdep.x.nx2i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b)
41  ret <vscale x 2 x i64> %out
42}
43
44;
45; BEXT
46;
47
48define <vscale x 16 x i8> @bext_nxv16i8(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b) {
49; CHECK-LABEL: bext_nxv16i8:
50; CHECK:       // %bb.0:
51; CHECK-NEXT:    bext z0.b, z0.b, z1.b
52; CHECK-NEXT:    ret
53  %out = call <vscale x 16 x i8> @llvm.aarch64.sve.bext.x.nx16i8(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b)
54  ret <vscale x 16 x i8> %out
55}
56
57define <vscale x 8 x i16> @bext_nxv8i16(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b) {
58; CHECK-LABEL: bext_nxv8i16:
59; CHECK:       // %bb.0:
60; CHECK-NEXT:    bext z0.h, z0.h, z1.h
61; CHECK-NEXT:    ret
62  %out = call <vscale x 8 x i16> @llvm.aarch64.sve.bext.x.nx8i16(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b)
63  ret <vscale x 8 x i16> %out
64}
65
66define <vscale x 4 x i32> @bext_nxv4i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) {
67; CHECK-LABEL: bext_nxv4i32:
68; CHECK:       // %bb.0:
69; CHECK-NEXT:    bext z0.s, z0.s, z1.s
70; CHECK-NEXT:    ret
71  %out = call <vscale x 4 x i32> @llvm.aarch64.sve.bext.x.nx4i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b)
72  ret <vscale x 4 x i32> %out
73}
74
75define <vscale x 2 x i64> @bext_nxv2i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b) {
76; CHECK-LABEL: bext_nxv2i64:
77; CHECK:       // %bb.0:
78; CHECK-NEXT:    bext z0.d, z0.d, z1.d
79; CHECK-NEXT:    ret
80  %out = call <vscale x 2 x i64> @llvm.aarch64.sve.bext.x.nx2i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b)
81  ret <vscale x 2 x i64> %out
82}
83
84;
85; BGRP
86;
87
88define <vscale x 16 x i8> @bgrp_nxv16i8(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b) {
89; CHECK-LABEL: bgrp_nxv16i8:
90; CHECK:       // %bb.0:
91; CHECK-NEXT:    bgrp z0.b, z0.b, z1.b
92; CHECK-NEXT:    ret
93  %out = call <vscale x 16 x i8> @llvm.aarch64.sve.bgrp.x.nx16i8(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b)
94  ret <vscale x 16 x i8> %out
95}
96
97define <vscale x 8 x i16> @bgrp_nxv8i16(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b) {
98; CHECK-LABEL: bgrp_nxv8i16:
99; CHECK:       // %bb.0:
100; CHECK-NEXT:    bgrp z0.h, z0.h, z1.h
101; CHECK-NEXT:    ret
102  %out = call <vscale x 8 x i16> @llvm.aarch64.sve.bgrp.x.nx8i16(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b)
103  ret <vscale x 8 x i16> %out
104}
105
106define <vscale x 4 x i32> @bgrp_nxv4i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) {
107; CHECK-LABEL: bgrp_nxv4i32:
108; CHECK:       // %bb.0:
109; CHECK-NEXT:    bgrp z0.s, z0.s, z1.s
110; CHECK-NEXT:    ret
111  %out = call <vscale x 4 x i32> @llvm.aarch64.sve.bgrp.x.nx4i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b)
112  ret <vscale x 4 x i32> %out
113}
114
115define <vscale x 2 x i64> @bgrp_nxv2i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b) {
116; CHECK-LABEL: bgrp_nxv2i64:
117; CHECK:       // %bb.0:
118; CHECK-NEXT:    bgrp z0.d, z0.d, z1.d
119; CHECK-NEXT:    ret
120  %out = call <vscale x 2 x i64> @llvm.aarch64.sve.bgrp.x.nx2i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b)
121  ret <vscale x 2 x i64> %out
122}
123
124declare <vscale x 16 x i8> @llvm.aarch64.sve.bdep.x.nx16i8(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b)
125declare <vscale x 8 x i16> @llvm.aarch64.sve.bdep.x.nx8i16(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b)
126declare <vscale x 4 x i32> @llvm.aarch64.sve.bdep.x.nx4i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b)
127declare <vscale x 2 x i64> @llvm.aarch64.sve.bdep.x.nx2i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b)
128
129declare <vscale x 16 x i8> @llvm.aarch64.sve.bext.x.nx16i8(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b)
130declare <vscale x 8 x i16> @llvm.aarch64.sve.bext.x.nx8i16(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b)
131declare <vscale x 4 x i32> @llvm.aarch64.sve.bext.x.nx4i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b)
132declare <vscale x 2 x i64> @llvm.aarch64.sve.bext.x.nx2i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b)
133
134declare <vscale x 16 x i8> @llvm.aarch64.sve.bgrp.x.nx16i8(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b)
135declare <vscale x 8 x i16> @llvm.aarch64.sve.bgrp.x.nx8i16(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b)
136declare <vscale x 4 x i32> @llvm.aarch64.sve.bgrp.x.nx4i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b)
137declare <vscale x 2 x i64> @llvm.aarch64.sve.bgrp.x.nx2i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b)
138