xref: /llvm-project/llvm/test/CodeGen/AArch64/sve2-intrinsics-binary-narrowing-shr.ll (revision 62baf21daa377c4ec1a641b26931063c1117d262) 
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve2 < %s | FileCheck %s
3; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sme -force-streaming < %s | FileCheck %s
4
5;
6; SHRNB
7;
8
9define <vscale x 16 x i8> @shrnb_h(<vscale x 8 x i16> %a) {
10; CHECK-LABEL: shrnb_h:
11; CHECK:       // %bb.0:
12; CHECK-NEXT:    shrnb z0.b, z0.h, #8
13; CHECK-NEXT:    ret
14  %out = call <vscale x 16 x i8> @llvm.aarch64.sve.shrnb.nxv8i16(<vscale x 8 x i16> %a,
15                                                                 i32 8)
16  ret <vscale x 16 x i8> %out
17}
18
19define <vscale x 8 x i16> @shrnb_s(<vscale x 4 x i32> %a) {
20; CHECK-LABEL: shrnb_s:
21; CHECK:       // %bb.0:
22; CHECK-NEXT:    shrnb z0.h, z0.s, #16
23; CHECK-NEXT:    ret
24  %out = call <vscale x 8 x i16> @llvm.aarch64.sve.shrnb.nxv4i32(<vscale x 4 x i32> %a,
25                                                                 i32 16)
26  ret <vscale x 8 x i16> %out
27}
28
29define <vscale x 4 x i32> @shrnb_d(<vscale x 2 x i64> %a) {
30; CHECK-LABEL: shrnb_d:
31; CHECK:       // %bb.0:
32; CHECK-NEXT:    shrnb z0.s, z0.d, #32
33; CHECK-NEXT:    ret
34  %out = call <vscale x 4 x i32> @llvm.aarch64.sve.shrnb.nxv2i64(<vscale x 2 x i64> %a,
35                                                                 i32 32)
36  ret <vscale x 4 x i32> %out
37}
38
39;
40; RSHRNB
41;
42
43define <vscale x 16 x i8> @rshrnb_h(<vscale x 8 x i16> %a) {
44; CHECK-LABEL: rshrnb_h:
45; CHECK:       // %bb.0:
46; CHECK-NEXT:    rshrnb z0.b, z0.h, #2
47; CHECK-NEXT:    ret
48  %out = call <vscale x 16 x i8> @llvm.aarch64.sve.rshrnb.nxv8i16(<vscale x 8 x i16> %a,
49                                                                  i32 2)
50  ret <vscale x 16 x i8> %out
51}
52
53define <vscale x 8 x i16> @rshrnb_s(<vscale x 4 x i32> %a) {
54; CHECK-LABEL: rshrnb_s:
55; CHECK:       // %bb.0:
56; CHECK-NEXT:    rshrnb z0.h, z0.s, #2
57; CHECK-NEXT:    ret
58  %out = call <vscale x 8 x i16> @llvm.aarch64.sve.rshrnb.nxv4i32(<vscale x 4 x i32> %a,
59                                                                  i32 2)
60  ret <vscale x 8 x i16> %out
61}
62
63define <vscale x 4 x i32> @rshrnb_d(<vscale x 2 x i64> %a) {
64; CHECK-LABEL: rshrnb_d:
65; CHECK:       // %bb.0:
66; CHECK-NEXT:    rshrnb z0.s, z0.d, #2
67; CHECK-NEXT:    ret
68  %out = call <vscale x 4 x i32> @llvm.aarch64.sve.rshrnb.nxv2i64(<vscale x 2 x i64> %a,
69                                                                  i32 2)
70  ret <vscale x 4 x i32> %out
71}
72
73;
74; UQSHRNB
75;
76
77define <vscale x 16 x i8> @uqshrnb_h(<vscale x 8 x i16> %a) {
78; CHECK-LABEL: uqshrnb_h:
79; CHECK:       // %bb.0:
80; CHECK-NEXT:    uqshrnb z0.b, z0.h, #1
81; CHECK-NEXT:    ret
82  %out = call <vscale x 16 x i8> @llvm.aarch64.sve.uqshrnb.nxv8i16(<vscale x 8 x i16> %a,
83                                                                   i32 1)
84  ret <vscale x 16 x i8> %out
85}
86
87define <vscale x 8 x i16> @uqshrnb_s(<vscale x 4 x i32> %a) {
88; CHECK-LABEL: uqshrnb_s:
89; CHECK:       // %bb.0:
90; CHECK-NEXT:    uqshrnb z0.h, z0.s, #1
91; CHECK-NEXT:    ret
92  %out = call <vscale x 8 x i16> @llvm.aarch64.sve.uqshrnb.nxv4i32(<vscale x 4 x i32> %a,
93                                                                   i32 1)
94  ret <vscale x 8 x i16> %out
95}
96
97define <vscale x 4 x i32> @uqshrnb_d(<vscale x 2 x i64> %a) {
98; CHECK-LABEL: uqshrnb_d:
99; CHECK:       // %bb.0:
100; CHECK-NEXT:    uqshrnb z0.s, z0.d, #1
101; CHECK-NEXT:    ret
102  %out = call <vscale x 4 x i32> @llvm.aarch64.sve.uqshrnb.nxv2i64(<vscale x 2 x i64> %a,
103                                                                   i32 1)
104  ret <vscale x 4 x i32> %out
105}
106
107;
108; SQSHRNB
109;
110
111define <vscale x 16 x i8> @sqshrnb_h(<vscale x 8 x i16> %a) {
112; CHECK-LABEL: sqshrnb_h:
113; CHECK:       // %bb.0:
114; CHECK-NEXT:    sqshrnb z0.b, z0.h, #1
115; CHECK-NEXT:    ret
116  %out = call <vscale x 16 x i8> @llvm.aarch64.sve.sqshrnb.nxv8i16(<vscale x 8 x i16> %a,
117                                                                   i32 1)
118  ret <vscale x 16 x i8> %out
119}
120
121define <vscale x 8 x i16> @sqshrnb_s(<vscale x 4 x i32> %a) {
122; CHECK-LABEL: sqshrnb_s:
123; CHECK:       // %bb.0:
124; CHECK-NEXT:    sqshrnb z0.h, z0.s, #1
125; CHECK-NEXT:    ret
126  %out = call <vscale x 8 x i16> @llvm.aarch64.sve.sqshrnb.nxv4i32(<vscale x 4 x i32> %a,
127                                                                   i32 1)
128  ret <vscale x 8 x i16> %out
129}
130
131define <vscale x 4 x i32> @sqshrnb_d(<vscale x 2 x i64> %a) {
132; CHECK-LABEL: sqshrnb_d:
133; CHECK:       // %bb.0:
134; CHECK-NEXT:    sqshrnb z0.s, z0.d, #1
135; CHECK-NEXT:    ret
136  %out = call <vscale x 4 x i32> @llvm.aarch64.sve.sqshrnb.nxv2i64(<vscale x 2 x i64> %a,
137                                                                   i32 1)
138  ret <vscale x 4 x i32> %out
139}
140
141;
142; SQSHRUNB
143;
144
145define <vscale x 16 x i8> @sqshrunb_h(<vscale x 8 x i16> %a) {
146; CHECK-LABEL: sqshrunb_h:
147; CHECK:       // %bb.0:
148; CHECK-NEXT:    sqshrunb z0.b, z0.h, #7
149; CHECK-NEXT:    ret
150  %out = call <vscale x 16 x i8> @llvm.aarch64.sve.sqshrunb.nxv8i16(<vscale x 8 x i16> %a,
151                                                                    i32 7)
152  ret <vscale x 16 x i8> %out
153}
154
155define <vscale x 8 x i16> @sqshrunb_s(<vscale x 4 x i32> %a) {
156; CHECK-LABEL: sqshrunb_s:
157; CHECK:       // %bb.0:
158; CHECK-NEXT:    sqshrunb z0.h, z0.s, #15
159; CHECK-NEXT:    ret
160  %out = call <vscale x 8 x i16> @llvm.aarch64.sve.sqshrunb.nxv4i32(<vscale x 4 x i32> %a,
161                                                                    i32 15)
162  ret <vscale x 8 x i16> %out
163}
164
165define <vscale x 4 x i32> @sqshrunb_d(<vscale x 2 x i64> %a) {
166; CHECK-LABEL: sqshrunb_d:
167; CHECK:       // %bb.0:
168; CHECK-NEXT:    sqshrunb z0.s, z0.d, #31
169; CHECK-NEXT:    ret
170  %out = call <vscale x 4 x i32> @llvm.aarch64.sve.sqshrunb.nxv2i64(<vscale x 2 x i64> %a,
171                                                                    i32 31)
172  ret <vscale x 4 x i32> %out
173}
174
175;
176; UQRSHRNB
177;
178
179define <vscale x 16 x i8> @uqrshrnb_h(<vscale x 8 x i16> %a) {
180; CHECK-LABEL: uqrshrnb_h:
181; CHECK:       // %bb.0:
182; CHECK-NEXT:    uqrshrnb z0.b, z0.h, #2
183; CHECK-NEXT:    ret
184  %out = call <vscale x 16 x i8> @llvm.aarch64.sve.uqrshrnb.nxv8i16(<vscale x 8 x i16> %a,
185                                                                    i32 2)
186  ret <vscale x 16 x i8> %out
187}
188
189define <vscale x 8 x i16> @uqrshrnb_s(<vscale x 4 x i32> %a) {
190; CHECK-LABEL: uqrshrnb_s:
191; CHECK:       // %bb.0:
192; CHECK-NEXT:    uqrshrnb z0.h, z0.s, #2
193; CHECK-NEXT:    ret
194  %out = call <vscale x 8 x i16> @llvm.aarch64.sve.uqrshrnb.nxv4i32(<vscale x 4 x i32> %a,
195                                                                    i32 2)
196  ret <vscale x 8 x i16> %out
197}
198
199define <vscale x 4 x i32> @uqrshrnb_d(<vscale x 2 x i64> %a) {
200; CHECK-LABEL: uqrshrnb_d:
201; CHECK:       // %bb.0:
202; CHECK-NEXT:    uqrshrnb z0.s, z0.d, #2
203; CHECK-NEXT:    ret
204  %out = call <vscale x 4 x i32> @llvm.aarch64.sve.uqrshrnb.nxv2i64(<vscale x 2 x i64> %a,
205                                                                    i32 2)
206  ret <vscale x 4 x i32> %out
207}
208
209;
210; SQRSHRNB
211;
212
213define <vscale x 16 x i8> @sqrshrnb_h(<vscale x 8 x i16> %a) {
214; CHECK-LABEL: sqrshrnb_h:
215; CHECK:       // %bb.0:
216; CHECK-NEXT:    sqrshrnb z0.b, z0.h, #2
217; CHECK-NEXT:    ret
218  %out = call <vscale x 16 x i8> @llvm.aarch64.sve.sqrshrnb.nxv8i16(<vscale x 8 x i16> %a,
219                                                                    i32 2)
220  ret <vscale x 16 x i8> %out
221}
222
223define <vscale x 8 x i16> @sqrshrnb_s(<vscale x 4 x i32> %a) {
224; CHECK-LABEL: sqrshrnb_s:
225; CHECK:       // %bb.0:
226; CHECK-NEXT:    sqrshrnb z0.h, z0.s, #2
227; CHECK-NEXT:    ret
228  %out = call <vscale x 8 x i16> @llvm.aarch64.sve.sqrshrnb.nxv4i32(<vscale x 4 x i32> %a,
229                                                                    i32 2)
230  ret <vscale x 8 x i16> %out
231}
232
233define <vscale x 4 x i32> @sqrshrnb_d(<vscale x 2 x i64> %a) {
234; CHECK-LABEL: sqrshrnb_d:
235; CHECK:       // %bb.0:
236; CHECK-NEXT:    sqrshrnb z0.s, z0.d, #2
237; CHECK-NEXT:    ret
238  %out = call <vscale x 4 x i32> @llvm.aarch64.sve.sqrshrnb.nxv2i64(<vscale x 2 x i64> %a,
239                                                                    i32 2)
240  ret <vscale x 4 x i32> %out
241}
242
243;
244; SQRSHRUNB
245;
246
247define <vscale x 16 x i8> @sqrshrunb_h(<vscale x 8 x i16> %a) {
248; CHECK-LABEL: sqrshrunb_h:
249; CHECK:       // %bb.0:
250; CHECK-NEXT:    sqrshrunb z0.b, z0.h, #6
251; CHECK-NEXT:    ret
252  %out = call <vscale x 16 x i8> @llvm.aarch64.sve.sqrshrunb.nxv8i16(<vscale x 8 x i16> %a,
253                                                                     i32 6)
254  ret <vscale x 16 x i8> %out
255}
256
257define <vscale x 8 x i16> @sqrshrunb_s(<vscale x 4 x i32> %a) {
258; CHECK-LABEL: sqrshrunb_s:
259; CHECK:       // %bb.0:
260; CHECK-NEXT:    sqrshrunb z0.h, z0.s, #14
261; CHECK-NEXT:    ret
262  %out = call <vscale x 8 x i16> @llvm.aarch64.sve.sqrshrunb.nxv4i32(<vscale x 4 x i32> %a,
263                                                                     i32 14)
264  ret <vscale x 8 x i16> %out
265}
266
267define <vscale x 4 x i32> @sqrshrunb_d(<vscale x 2 x i64> %a) {
268; CHECK-LABEL: sqrshrunb_d:
269; CHECK:       // %bb.0:
270; CHECK-NEXT:    sqrshrunb z0.s, z0.d, #30
271; CHECK-NEXT:    ret
272  %out = call <vscale x 4 x i32> @llvm.aarch64.sve.sqrshrunb.nxv2i64(<vscale x 2 x i64> %a,
273                                                                     i32 30)
274  ret <vscale x 4 x i32> %out
275}
276
277;
278; SHRNT
279;
280
281define <vscale x 16 x i8> @shrnt_h(<vscale x 16 x i8> %a, <vscale x 8 x i16> %b) {
282; CHECK-LABEL: shrnt_h:
283; CHECK:       // %bb.0:
284; CHECK-NEXT:    shrnt z0.b, z1.h, #3
285; CHECK-NEXT:    ret
286  %out = call <vscale x 16 x i8> @llvm.aarch64.sve.shrnt.nxv8i16(<vscale x 16 x i8> %a,
287                                                                 <vscale x 8 x i16> %b,
288                                                                 i32 3)
289  ret <vscale x 16 x i8> %out
290}
291
292define <vscale x 8 x i16> @shrnt_s(<vscale x 8 x i16> %a, <vscale x 4 x i32> %b) {
293; CHECK-LABEL: shrnt_s:
294; CHECK:       // %bb.0:
295; CHECK-NEXT:    shrnt z0.h, z1.s, #3
296; CHECK-NEXT:    ret
297  %out = call <vscale x 8 x i16> @llvm.aarch64.sve.shrnt.nxv4i32(<vscale x 8 x i16> %a,
298                                                                 <vscale x 4 x i32> %b,
299                                                                 i32 3)
300  ret <vscale x 8 x i16> %out
301}
302
303define <vscale x 4 x i32> @shrnt_d(<vscale x 4 x i32> %a, <vscale x 2 x i64> %b) {
304; CHECK-LABEL: shrnt_d:
305; CHECK:       // %bb.0:
306; CHECK-NEXT:    shrnt z0.s, z1.d, #3
307; CHECK-NEXT:    ret
308  %out = call <vscale x 4 x i32> @llvm.aarch64.sve.shrnt.nxv2i64(<vscale x 4 x i32> %a,
309                                                                 <vscale x 2 x i64> %b,
310                                                                 i32 3)
311  ret <vscale x 4 x i32> %out
312}
313
314;
315; RSHRNT
316;
317
318define <vscale x 16 x i8> @rshrnt_h(<vscale x 16 x i8> %a, <vscale x 8 x i16> %b) {
319; CHECK-LABEL: rshrnt_h:
320; CHECK:       // %bb.0:
321; CHECK-NEXT:    rshrnt z0.b, z1.h, #1
322; CHECK-NEXT:    ret
323  %out = call <vscale x 16 x i8> @llvm.aarch64.sve.rshrnt.nxv8i16(<vscale x 16 x i8> %a,
324                                                                  <vscale x 8 x i16> %b,
325                                                                  i32 1)
326  ret <vscale x 16 x i8> %out
327}
328
329define <vscale x 8 x i16> @rshrnt_s(<vscale x 8 x i16> %a, <vscale x 4 x i32> %b) {
330; CHECK-LABEL: rshrnt_s:
331; CHECK:       // %bb.0:
332; CHECK-NEXT:    rshrnt z0.h, z1.s, #5
333; CHECK-NEXT:    ret
334  %out = call <vscale x 8 x i16> @llvm.aarch64.sve.rshrnt.nxv4i32(<vscale x 8 x i16> %a,
335                                                                  <vscale x 4 x i32> %b,
336                                                                  i32 5)
337  ret <vscale x 8 x i16> %out
338}
339
340define <vscale x 4 x i32> @rshrnt_d(<vscale x 4 x i32> %a, <vscale x 2 x i64> %b) {
341; CHECK-LABEL: rshrnt_d:
342; CHECK:       // %bb.0:
343; CHECK-NEXT:    rshrnt z0.s, z1.d, #5
344; CHECK-NEXT:    ret
345  %out = call <vscale x 4 x i32> @llvm.aarch64.sve.rshrnt.nxv2i64(<vscale x 4 x i32> %a,
346                                                                  <vscale x 2 x i64> %b,
347                                                                  i32 5)
348  ret <vscale x 4 x i32> %out
349}
350
351;
352; UQSHRNT
353;
354
355define <vscale x 16 x i8> @uqshrnt_h(<vscale x 16 x i8> %a, <vscale x 8 x i16> %b) {
356; CHECK-LABEL: uqshrnt_h:
357; CHECK:       // %bb.0:
358; CHECK-NEXT:    uqshrnt z0.b, z1.h, #5
359; CHECK-NEXT:    ret
360  %out = call <vscale x 16 x i8> @llvm.aarch64.sve.uqshrnt.nxv8i16(<vscale x 16 x i8> %a,
361                                                                   <vscale x 8 x i16> %b,
362                                                                   i32 5)
363  ret <vscale x 16 x i8> %out
364}
365
366define <vscale x 8 x i16> @uqshrnt_s(<vscale x 8 x i16> %a, <vscale x 4 x i32> %b) {
367; CHECK-LABEL: uqshrnt_s:
368; CHECK:       // %bb.0:
369; CHECK-NEXT:    uqshrnt z0.h, z1.s, #13
370; CHECK-NEXT:    ret
371  %out = call <vscale x 8 x i16> @llvm.aarch64.sve.uqshrnt.nxv4i32(<vscale x 8 x i16> %a,
372                                                                   <vscale x 4 x i32> %b,
373                                                                   i32 13)
374  ret <vscale x 8 x i16> %out
375}
376
377define <vscale x 4 x i32> @uqshrnt_d(<vscale x 4 x i32> %a, <vscale x 2 x i64> %b) {
378; CHECK-LABEL: uqshrnt_d:
379; CHECK:       // %bb.0:
380; CHECK-NEXT:    uqshrnt z0.s, z1.d, #29
381; CHECK-NEXT:    ret
382  %out = call <vscale x 4 x i32> @llvm.aarch64.sve.uqshrnt.nxv2i64(<vscale x 4 x i32> %a,
383                                                                   <vscale x 2 x i64> %b,
384                                                                   i32 29)
385  ret <vscale x 4 x i32> %out
386}
387
388;
389; SQSHRNT
390;
391
392define <vscale x 16 x i8> @sqshrnt_h(<vscale x 16 x i8> %a, <vscale x 8 x i16> %b) {
393; CHECK-LABEL: sqshrnt_h:
394; CHECK:       // %bb.0:
395; CHECK-NEXT:    sqshrnt z0.b, z1.h, #5
396; CHECK-NEXT:    ret
397  %out = call <vscale x 16 x i8> @llvm.aarch64.sve.sqshrnt.nxv8i16(<vscale x 16 x i8> %a,
398                                                                   <vscale x 8 x i16> %b,
399                                                                   i32 5)
400  ret <vscale x 16 x i8> %out
401}
402
403define <vscale x 8 x i16> @sqshrnt_s(<vscale x 8 x i16> %a, <vscale x 4 x i32> %b) {
404; CHECK-LABEL: sqshrnt_s:
405; CHECK:       // %bb.0:
406; CHECK-NEXT:    sqshrnt z0.h, z1.s, #13
407; CHECK-NEXT:    ret
408  %out = call <vscale x 8 x i16> @llvm.aarch64.sve.sqshrnt.nxv4i32(<vscale x 8 x i16> %a,
409                                                                   <vscale x 4 x i32> %b,
410                                                                   i32 13)
411  ret <vscale x 8 x i16> %out
412}
413
414define <vscale x 4 x i32> @sqshrnt_d(<vscale x 4 x i32> %a, <vscale x 2 x i64> %b) {
415; CHECK-LABEL: sqshrnt_d:
416; CHECK:       // %bb.0:
417; CHECK-NEXT:    sqshrnt z0.s, z1.d, #29
418; CHECK-NEXT:    ret
419  %out = call <vscale x 4 x i32> @llvm.aarch64.sve.sqshrnt.nxv2i64(<vscale x 4 x i32> %a,
420                                                                   <vscale x 2 x i64> %b,
421                                                                   i32 29)
422  ret <vscale x 4 x i32> %out
423}
424
425;
426; SQSHRUNT
427;
428
429define <vscale x 16 x i8> @sqshrunt_h(<vscale x 16 x i8> %a, <vscale x 8 x i16> %b) {
430; CHECK-LABEL: sqshrunt_h:
431; CHECK:       // %bb.0:
432; CHECK-NEXT:    sqshrunt z0.b, z1.h, #4
433; CHECK-NEXT:    ret
434  %out = call <vscale x 16 x i8> @llvm.aarch64.sve.sqshrunt.nxv8i16(<vscale x 16 x i8> %a,
435                                                                    <vscale x 8 x i16> %b,
436                                                                    i32 4)
437  ret <vscale x 16 x i8> %out
438}
439
440define <vscale x 8 x i16> @sqshrunt_s(<vscale x 8 x i16> %a, <vscale x 4 x i32> %b) {
441; CHECK-LABEL: sqshrunt_s:
442; CHECK:       // %bb.0:
443; CHECK-NEXT:    sqshrunt z0.h, z1.s, #4
444; CHECK-NEXT:    ret
445  %out = call <vscale x 8 x i16> @llvm.aarch64.sve.sqshrunt.nxv4i32(<vscale x 8 x i16> %a,
446                                                                    <vscale x 4 x i32> %b,
447                                                                    i32 4)
448  ret <vscale x 8 x i16> %out
449}
450
451define <vscale x 4 x i32> @sqshrunt_d(<vscale x 4 x i32> %a, <vscale x 2 x i64> %b) {
452; CHECK-LABEL: sqshrunt_d:
453; CHECK:       // %bb.0:
454; CHECK-NEXT:    sqshrunt z0.s, z1.d, #4
455; CHECK-NEXT:    ret
456  %out = call <vscale x 4 x i32> @llvm.aarch64.sve.sqshrunt.nxv2i64(<vscale x 4 x i32> %a,
457                                                                    <vscale x 2 x i64> %b,
458                                                                    i32 4)
459  ret <vscale x 4 x i32> %out
460}
461
462;
463; UQRSHRNT
464;
465
466define <vscale x 16 x i8> @uqrshrnt_h(<vscale x 16 x i8> %a, <vscale x 8 x i16> %b) {
467; CHECK-LABEL: uqrshrnt_h:
468; CHECK:       // %bb.0:
469; CHECK-NEXT:    uqrshrnt z0.b, z1.h, #8
470; CHECK-NEXT:    ret
471  %out = call <vscale x 16 x i8> @llvm.aarch64.sve.uqrshrnt.nxv8i16(<vscale x 16 x i8> %a,
472                                                                    <vscale x 8 x i16> %b,
473                                                                    i32 8)
474  ret <vscale x 16 x i8> %out
475}
476
477define <vscale x 8 x i16> @uqrshrnt_s(<vscale x 8 x i16> %a, <vscale x 4 x i32> %b) {
478; CHECK-LABEL: uqrshrnt_s:
479; CHECK:       // %bb.0:
480; CHECK-NEXT:    uqrshrnt z0.h, z1.s, #12
481; CHECK-NEXT:    ret
482  %out = call <vscale x 8 x i16> @llvm.aarch64.sve.uqrshrnt.nxv4i32(<vscale x 8 x i16> %a,
483                                                                    <vscale x 4 x i32> %b,
484                                                                    i32 12)
485  ret <vscale x 8 x i16> %out
486}
487
488define <vscale x 4 x i32> @uqrshrnt_d(<vscale x 4 x i32> %a, <vscale x 2 x i64> %b) {
489; CHECK-LABEL: uqrshrnt_d:
490; CHECK:       // %bb.0:
491; CHECK-NEXT:    uqrshrnt z0.s, z1.d, #28
492; CHECK-NEXT:    ret
493  %out = call <vscale x 4 x i32> @llvm.aarch64.sve.uqrshrnt.nxv2i64(<vscale x 4 x i32> %a,
494                                                                    <vscale x 2 x i64> %b,
495                                                                    i32 28)
496  ret <vscale x 4 x i32> %out
497}
498
499;
500; SQRSHRNT
501;
502
503define <vscale x 16 x i8> @sqrshrnt_h(<vscale x 16 x i8> %a, <vscale x 8 x i16> %b) {
504; CHECK-LABEL: sqrshrnt_h:
505; CHECK:       // %bb.0:
506; CHECK-NEXT:    sqrshrnt z0.b, z1.h, #8
507; CHECK-NEXT:    ret
508  %out = call <vscale x 16 x i8> @llvm.aarch64.sve.sqrshrnt.nxv8i16(<vscale x 16 x i8> %a,
509                                                                    <vscale x 8 x i16> %b,
510                                                                    i32 8)
511  ret <vscale x 16 x i8> %out
512}
513
514define <vscale x 8 x i16> @sqrshrnt_s(<vscale x 8 x i16> %a, <vscale x 4 x i32> %b) {
515; CHECK-LABEL: sqrshrnt_s:
516; CHECK:       // %bb.0:
517; CHECK-NEXT:    sqrshrnt z0.h, z1.s, #12
518; CHECK-NEXT:    ret
519  %out = call <vscale x 8 x i16> @llvm.aarch64.sve.sqrshrnt.nxv4i32(<vscale x 8 x i16> %a,
520                                                                    <vscale x 4 x i32> %b,
521                                                                    i32 12)
522  ret <vscale x 8 x i16> %out
523}
524
525define <vscale x 4 x i32> @sqrshrnt_d(<vscale x 4 x i32> %a, <vscale x 2 x i64> %b) {
526; CHECK-LABEL: sqrshrnt_d:
527; CHECK:       // %bb.0:
528; CHECK-NEXT:    sqrshrnt z0.s, z1.d, #28
529; CHECK-NEXT:    ret
530  %out = call <vscale x 4 x i32> @llvm.aarch64.sve.sqrshrnt.nxv2i64(<vscale x 4 x i32> %a,
531                                                                    <vscale x 2 x i64> %b,
532                                                                    i32 28)
533  ret <vscale x 4 x i32> %out
534}
535
536;
537; SQRSHRUNT
538;
539
540define <vscale x 16 x i8> @sqrshrunt_h(<vscale x 16 x i8> %a, <vscale x 8 x i16> %b) {
541; CHECK-LABEL: sqrshrunt_h:
542; CHECK:       // %bb.0:
543; CHECK-NEXT:    sqrshrunt z0.b, z1.h, #1
544; CHECK-NEXT:    ret
545  %out = call <vscale x 16 x i8> @llvm.aarch64.sve.sqrshrunt.nxv8i16(<vscale x 16 x i8> %a,
546                                                                     <vscale x 8 x i16> %b,
547                                                                     i32 1)
548  ret <vscale x 16 x i8> %out
549}
550
551define <vscale x 8 x i16> @sqrshrunt_s(<vscale x 8 x i16> %a, <vscale x 4 x i32> %b) {
552; CHECK-LABEL: sqrshrunt_s:
553; CHECK:       // %bb.0:
554; CHECK-NEXT:    sqrshrunt z0.h, z1.s, #5
555; CHECK-NEXT:    ret
556  %out = call <vscale x 8 x i16> @llvm.aarch64.sve.sqrshrunt.nxv4i32(<vscale x 8 x i16> %a,
557                                                                     <vscale x 4 x i32> %b,
558                                                                     i32 5)
559  ret <vscale x 8 x i16> %out
560}
561
562define <vscale x 4 x i32> @sqrshrunt_d(<vscale x 4 x i32> %a, <vscale x 2 x i64> %b) {
563; CHECK-LABEL: sqrshrunt_d:
564; CHECK:       // %bb.0:
565; CHECK-NEXT:    sqrshrunt z0.s, z1.d, #5
566; CHECK-NEXT:    ret
567  %out = call <vscale x 4 x i32> @llvm.aarch64.sve.sqrshrunt.nxv2i64(<vscale x 4 x i32> %a,
568                                                                     <vscale x 2 x i64> %b,
569                                                                     i32 5)
570  ret <vscale x 4 x i32> %out
571}
572
573declare <vscale x 16 x i8> @llvm.aarch64.sve.shrnb.nxv8i16(<vscale x 8 x i16>, i32)
574declare <vscale x 8 x i16> @llvm.aarch64.sve.shrnb.nxv4i32(<vscale x 4 x i32>, i32)
575declare <vscale x 4 x i32> @llvm.aarch64.sve.shrnb.nxv2i64(<vscale x 2 x i64>, i32)
576
577declare <vscale x 16 x i8> @llvm.aarch64.sve.rshrnb.nxv8i16(<vscale x 8 x i16>, i32)
578declare <vscale x 8 x i16> @llvm.aarch64.sve.rshrnb.nxv4i32(<vscale x 4 x i32>, i32)
579declare <vscale x 4 x i32> @llvm.aarch64.sve.rshrnb.nxv2i64(<vscale x 2 x i64>, i32)
580
581declare <vscale x 16 x i8> @llvm.aarch64.sve.uqshrnb.nxv8i16(<vscale x 8 x i16>, i32)
582declare <vscale x 8 x i16> @llvm.aarch64.sve.uqshrnb.nxv4i32(<vscale x 4 x i32>, i32)
583declare <vscale x 4 x i32> @llvm.aarch64.sve.uqshrnb.nxv2i64(<vscale x 2 x i64>, i32)
584
585declare <vscale x 16 x i8> @llvm.aarch64.sve.sqshrnb.nxv8i16(<vscale x 8 x i16>, i32)
586declare <vscale x 8 x i16> @llvm.aarch64.sve.sqshrnb.nxv4i32(<vscale x 4 x i32>, i32)
587declare <vscale x 4 x i32> @llvm.aarch64.sve.sqshrnb.nxv2i64(<vscale x 2 x i64>, i32)
588
589declare <vscale x 16 x i8> @llvm.aarch64.sve.uqrshrnb.nxv8i16(<vscale x 8 x i16>, i32)
590declare <vscale x 8 x i16> @llvm.aarch64.sve.uqrshrnb.nxv4i32(<vscale x 4 x i32>, i32)
591declare <vscale x 4 x i32> @llvm.aarch64.sve.uqrshrnb.nxv2i64(<vscale x 2 x i64>, i32)
592
593declare <vscale x 16 x i8> @llvm.aarch64.sve.sqrshrnb.nxv8i16(<vscale x 8 x i16>, i32)
594declare <vscale x 8 x i16> @llvm.aarch64.sve.sqrshrnb.nxv4i32(<vscale x 4 x i32>, i32)
595declare <vscale x 4 x i32> @llvm.aarch64.sve.sqrshrnb.nxv2i64(<vscale x 2 x i64>, i32)
596
597declare <vscale x 16 x i8> @llvm.aarch64.sve.sqshrunb.nxv8i16(<vscale x 8 x i16>, i32)
598declare <vscale x 8 x i16> @llvm.aarch64.sve.sqshrunb.nxv4i32(<vscale x 4 x i32>, i32)
599declare <vscale x 4 x i32> @llvm.aarch64.sve.sqshrunb.nxv2i64(<vscale x 2 x i64>, i32)
600
601declare <vscale x 16 x i8> @llvm.aarch64.sve.sqrshrunb.nxv8i16(<vscale x 8 x i16>, i32)
602declare <vscale x 8 x i16> @llvm.aarch64.sve.sqrshrunb.nxv4i32(<vscale x 4 x i32>, i32)
603declare <vscale x 4 x i32> @llvm.aarch64.sve.sqrshrunb.nxv2i64(<vscale x 2 x i64>, i32)
604
605declare <vscale x 16 x i8> @llvm.aarch64.sve.shrnt.nxv8i16(<vscale x 16 x i8>, <vscale x 8 x i16>, i32)
606declare <vscale x 8 x i16> @llvm.aarch64.sve.shrnt.nxv4i32(<vscale x 8 x i16>, <vscale x 4 x i32>, i32)
607declare <vscale x 4 x i32> @llvm.aarch64.sve.shrnt.nxv2i64(<vscale x 4 x i32>, <vscale x 2 x i64>, i32)
608
609declare <vscale x 16 x i8> @llvm.aarch64.sve.rshrnt.nxv8i16(<vscale x 16 x i8>, <vscale x 8 x i16>, i32)
610declare <vscale x 8 x i16> @llvm.aarch64.sve.rshrnt.nxv4i32(<vscale x 8 x i16>, <vscale x 4 x i32>, i32)
611declare <vscale x 4 x i32> @llvm.aarch64.sve.rshrnt.nxv2i64(<vscale x 4 x i32>, <vscale x 2 x i64>, i32)
612
613declare <vscale x 16 x i8> @llvm.aarch64.sve.uqshrnt.nxv8i16(<vscale x 16 x i8>, <vscale x 8 x i16>, i32)
614declare <vscale x 8 x i16> @llvm.aarch64.sve.uqshrnt.nxv4i32(<vscale x 8 x i16>, <vscale x 4 x i32>, i32)
615declare <vscale x 4 x i32> @llvm.aarch64.sve.uqshrnt.nxv2i64(<vscale x 4 x i32>, <vscale x 2 x i64>, i32)
616
617declare <vscale x 16 x i8> @llvm.aarch64.sve.sqshrnt.nxv8i16(<vscale x 16 x i8>, <vscale x 8 x i16>, i32)
618declare <vscale x 8 x i16> @llvm.aarch64.sve.sqshrnt.nxv4i32(<vscale x 8 x i16>, <vscale x 4 x i32>, i32)
619declare <vscale x 4 x i32> @llvm.aarch64.sve.sqshrnt.nxv2i64(<vscale x 4 x i32>, <vscale x 2 x i64>, i32)
620
621declare <vscale x 16 x i8> @llvm.aarch64.sve.sqshrunt.nxv8i16(<vscale x 16 x i8>, <vscale x 8 x i16>, i32)
622declare <vscale x 8 x i16> @llvm.aarch64.sve.sqshrunt.nxv4i32(<vscale x 8 x i16>, <vscale x 4 x i32>, i32)
623declare <vscale x 4 x i32> @llvm.aarch64.sve.sqshrunt.nxv2i64(<vscale x 4 x i32>, <vscale x 2 x i64>, i32)
624
625declare <vscale x 16 x i8> @llvm.aarch64.sve.uqrshrnt.nxv8i16(<vscale x 16 x i8>, <vscale x 8 x i16>, i32)
626declare <vscale x 8 x i16> @llvm.aarch64.sve.uqrshrnt.nxv4i32(<vscale x 8 x i16>, <vscale x 4 x i32>, i32)
627declare <vscale x 4 x i32> @llvm.aarch64.sve.uqrshrnt.nxv2i64(<vscale x 4 x i32>, <vscale x 2 x i64>, i32)
628
629declare <vscale x 16 x i8> @llvm.aarch64.sve.sqrshrnt.nxv8i16(<vscale x 16 x i8>, <vscale x 8 x i16>, i32)
630declare <vscale x 8 x i16> @llvm.aarch64.sve.sqrshrnt.nxv4i32(<vscale x 8 x i16>, <vscale x 4 x i32>, i32)
631declare <vscale x 4 x i32> @llvm.aarch64.sve.sqrshrnt.nxv2i64(<vscale x 4 x i32>, <vscale x 2 x i64>, i32)
632
633declare <vscale x 16 x i8> @llvm.aarch64.sve.sqrshrunt.nxv8i16(<vscale x 16 x i8>, <vscale x 8 x i16>, i32)
634declare <vscale x 8 x i16> @llvm.aarch64.sve.sqrshrunt.nxv4i32(<vscale x 8 x i16>, <vscale x 4 x i32>, i32)
635declare <vscale x 4 x i32> @llvm.aarch64.sve.sqrshrunt.nxv2i64(<vscale x 4 x i32>, <vscale x 2 x i64>, i32)
636