xref: /llvm-project/llvm/test/CodeGen/AArch64/sve2-int-addsub-long.ll (revision 672f673004663aeb15ece1af4b5b219994924167) 
1; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve2 < %s | FileCheck %s
2
3;
4; ADCLB (vector, long, unpredicated)
5;
6define <vscale x 4 x i32> @adclb_i32(<vscale x 4 x i32> %a,
7                                     <vscale x 4 x i32> %b,
8                                     <vscale x 4 x i32> %c) {
9; CHECK-LABEL: adclb_i32
10; CHECK: adclb z0.s, z1.s, z2.s
11; CHECK-NEXT: ret
12  %res = call <vscale x 4 x i32> @llvm.aarch64.sve.adclb.nxv4i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b, <vscale x 4 x i32> %c)
13  ret <vscale x 4 x i32> %res
14}
15
16define <vscale x 2 x i64> @adclb_i64(<vscale x 2 x i64> %a,
17                                     <vscale x 2 x i64> %b,
18                                     <vscale x 2 x i64> %c) {
19; CHECK-LABEL: adclb_i64
20; CHECK: adclb z0.d, z1.d, z2.d
21; CHECK-NEXT: ret
22  %res = call <vscale x 2 x i64> @llvm.aarch64.sve.adclb.nxv2i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b, <vscale x 2 x i64> %c)
23  ret <vscale x 2 x i64> %res
24}
25
26;
27; ADCLT (vector, long, unpredicated)
28;
29define <vscale x 4 x i32> @adclt_i32(<vscale x 4 x i32> %a,
30                                     <vscale x 4 x i32> %b,
31                                     <vscale x 4 x i32> %c) {
32; CHECK-LABEL: adclt_i32
33; CHECK: adclt z0.s, z1.s, z2.s
34; CHECK-NEXT: ret
35  %res = call <vscale x 4 x i32> @llvm.aarch64.sve.adclt.nxv4i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b, <vscale x 4 x i32> %c)
36  ret <vscale x 4 x i32> %res
37}
38
39define <vscale x 2 x i64> @adclt_i64(<vscale x 2 x i64> %a,
40                                     <vscale x 2 x i64> %b,
41                                     <vscale x 2 x i64> %c) {
42; CHECK-LABEL: adclt_i64
43; CHECK: adclt z0.d, z1.d, z2.d
44; CHECK-NEXT: ret
45  %res = call <vscale x 2 x i64> @llvm.aarch64.sve.adclt.nxv2i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b, <vscale x 2 x i64> %c)
46  ret <vscale x 2 x i64> %res
47}
48
49;
50; SBCLB (vector, long, unpredicated)
51;
52define <vscale x 4 x i32> @sbclb_i32(<vscale x 4 x i32> %a,
53                                     <vscale x 4 x i32> %b,
54                                     <vscale x 4 x i32> %c) {
55; CHECK-LABEL: sbclb_i32
56; CHECK: sbclb z0.s, z1.s, z2.s
57; CHECK-NEXT: ret
58  %res = call <vscale x 4 x i32> @llvm.aarch64.sve.sbclb.nxv4i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b, <vscale x 4 x i32> %c)
59  ret <vscale x 4 x i32> %res
60}
61
62define <vscale x 2 x i64> @sbclb_i64(<vscale x 2 x i64> %a,
63                                     <vscale x 2 x i64> %b,
64                                     <vscale x 2 x i64> %c) {
65; CHECK-LABEL: sbclb_i64
66; CHECK: sbclb z0.d, z1.d, z2.d
67; CHECK-NEXT: ret
68  %res = call <vscale x 2 x i64> @llvm.aarch64.sve.sbclb.nxv2i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b, <vscale x 2 x i64> %c)
69  ret <vscale x 2 x i64> %res
70}
71
72;
73; SBCLT (vector, long, unpredicated)
74;
75define <vscale x 4 x i32> @sbclt_i32(<vscale x 4 x i32> %a,
76                                     <vscale x 4 x i32> %b,
77                                     <vscale x 4 x i32> %c) {
78; CHECK-LABEL: sbclt_i32
79; CHECK: sbclt z0.s, z1.s, z2.s
80; CHECK-NEXT: ret
81  %res = call <vscale x 4 x i32> @llvm.aarch64.sve.sbclt.nxv4i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b, <vscale x 4 x i32> %c)
82  ret <vscale x 4 x i32> %res
83}
84
85define <vscale x 2 x i64> @sbclt_i64(<vscale x 2 x i64> %a,
86                                     <vscale x 2 x i64> %b,
87                                     <vscale x 2 x i64> %c) {
88; CHECK-LABEL: sbclt_i64
89; CHECK: sbclt z0.d, z1.d, z2.d
90; CHECK-NEXT: ret
91  %res = call <vscale x 2 x i64> @llvm.aarch64.sve.sbclt.nxv2i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b, <vscale x 2 x i64> %c)
92  ret <vscale x 2 x i64> %res
93}
94
95declare <vscale x 4 x i32> @llvm.aarch64.sve.adclb.nxv4i32(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>)
96declare <vscale x 2 x i64> @llvm.aarch64.sve.adclb.nxv2i64(<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>)
97declare <vscale x 4 x i32> @llvm.aarch64.sve.adclt.nxv4i32(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>)
98declare <vscale x 2 x i64> @llvm.aarch64.sve.adclt.nxv2i64(<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>)
99declare <vscale x 4 x i32> @llvm.aarch64.sve.sbclb.nxv4i32(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>)
100declare <vscale x 2 x i64> @llvm.aarch64.sve.sbclb.nxv2i64(<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>)
101declare <vscale x 4 x i32> @llvm.aarch64.sve.sbclt.nxv4i32(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>)
102declare <vscale x 2 x i64> @llvm.aarch64.sve.sbclt.nxv2i64(<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>)
103