xref: /llvm-project/llvm/test/CodeGen/AArch64/sve-vselect-fold.ll (revision af1c8f0d142179826197f22c3880c980e6e47b3d) 
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve -verify-machineinstrs < %s | FileCheck %s
3
4; Test that the select returns %true, because the predicate is all active.
5define <vscale x 4 x i32> @select_ptrue_fold_all_active(<vscale x 4 x i32> %false, <vscale x 4 x i32> %true) {
6; CHECK-LABEL: select_ptrue_fold_all_active:
7; CHECK:       // %bb.0:
8; CHECK-NEXT:    mov z0.d, z1.d
9; CHECK-NEXT:    ret
10  %p = call <vscale x 4 x i1> @llvm.aarch64.sve.ptrue.nxv4i1(i32 31)
11  %res = select <vscale x 4 x i1> %p, <vscale x 4 x i32> %true, <vscale x 4 x i32> %false
12  ret <vscale x 4 x i32> %res
13}
14
15; Test that the select returns %true, because the predicate is all active for vscale_range(2, 2)
16define <vscale x 4 x i32> @select_ptrue_fold_vl8(<vscale x 4 x i32> %false, <vscale x 4 x i32> %true) vscale_range(2, 2) {
17; CHECK-LABEL: select_ptrue_fold_vl8:
18; CHECK:       // %bb.0:
19; CHECK-NEXT:    mov z0.d, z1.d
20; CHECK-NEXT:    ret
21  %p = call <vscale x 4 x i1> @llvm.aarch64.sve.ptrue.nxv4i1(i32 8)
22  %res = select <vscale x 4 x i1> %p, <vscale x 4 x i32> %true, <vscale x 4 x i32> %false
23  ret <vscale x 4 x i32> %res
24}
25
26define <vscale x 16 x i8> @select_ptrue_fold_all_inactive(<vscale x 16 x i8> %true, <vscale x 16 x i8> %false) {
27; CHECK-LABEL: select_ptrue_fold_all_inactive:
28; CHECK:       // %bb.0:
29; CHECK-NEXT:    mov z0.d, z1.d
30; CHECK-NEXT:    ret
31  %p = call <vscale x 16 x  i1> @llvm.aarch64.sve.convert.from.svbool.nxv16i1(<vscale x 16 x i1> zeroinitializer)
32  %res = select <vscale x 16 x  i1> %p, <vscale x 16 x i8> %true, <vscale x 16 x i8> %false
33  ret <vscale x 16 x i8> %res
34}
35
36define <vscale x 4 x i32> @select_ptrue_fold_all_inactive_reinterpret(<vscale x 4 x i32> %true, <vscale x 4 x i32> %false) {
37; CHECK-LABEL: select_ptrue_fold_all_inactive_reinterpret:
38; CHECK:       // %bb.0:
39; CHECK-NEXT:    mov z0.d, z1.d
40; CHECK-NEXT:    ret
41  %p = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> zeroinitializer)
42  %res = select <vscale x 4 x i1> %p, <vscale x 4 x i32> %true, <vscale x 4 x i32> %false
43  ret <vscale x 4 x i32> %res
44}
45
46; Test that the select remains, because predicate is not all active (only half lanes are set for vscale_range(2, 2))
47define <vscale x 4 x i32> @select_ptrue_no_fold_vl4(<vscale x 4 x i32> %true, <vscale x 4 x i32> %false) vscale_range(2, 2) {
48; CHECK-LABEL: select_ptrue_no_fold_vl4:
49; CHECK:       // %bb.0:
50; CHECK-NEXT:    ptrue p0.s, vl4
51; CHECK-NEXT:    sel z0.s, p0, z0.s, z1.s
52; CHECK-NEXT:    ret
53  %p = call <vscale x 4 x i1> @llvm.aarch64.sve.ptrue.nxv4i1(i32 4)
54  %res = select <vscale x 4 x i1> %p, <vscale x 4 x i32> %true, <vscale x 4 x i32> %false
55  ret <vscale x 4 x i32> %res
56}
57
58declare <vscale x 4 x i1> @llvm.aarch64.sve.ptrue.nxv4i1(i32)
59declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>)
60declare <vscale x 16 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv16i1(<vscale x 16 x i1>)
61