xref: /llvm-project/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-stores.ll (revision 8e0cd7382adacd8bc1741dc26bc0be6bdf8e238a) 
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mattr=+sve -force-streaming-compatible < %s | FileCheck %s
3; RUN: llc -mattr=+sme -force-streaming < %s | FileCheck %s
4; RUN: llc -force-streaming-compatible < %s | FileCheck %s --check-prefix=NONEON-NOSVE
5
6
7target triple = "aarch64-unknown-linux-gnu"
8
9define void @store_v4i8(ptr %a) {
10; CHECK-LABEL: store_v4i8:
11; CHECK:       // %bb.0:
12; CHECK-NEXT:    mov z0.h, #0 // =0x0
13; CHECK-NEXT:    ptrue p0.h, vl4
14; CHECK-NEXT:    st1b { z0.h }, p0, [x0]
15; CHECK-NEXT:    ret
16;
17; NONEON-NOSVE-LABEL: store_v4i8:
18; NONEON-NOSVE:       // %bb.0:
19; NONEON-NOSVE-NEXT:    str wzr, [x0]
20; NONEON-NOSVE-NEXT:    ret
21  store <4 x i8> zeroinitializer, ptr %a
22  ret void
23}
24
25define void @store_v8i8(ptr %a) {
26; CHECK-LABEL: store_v8i8:
27; CHECK:       // %bb.0:
28; CHECK-NEXT:    mov z0.b, #0 // =0x0
29; CHECK-NEXT:    str d0, [x0]
30; CHECK-NEXT:    ret
31;
32; NONEON-NOSVE-LABEL: store_v8i8:
33; NONEON-NOSVE:       // %bb.0:
34; NONEON-NOSVE-NEXT:    adrp x8, .LCPI1_0
35; NONEON-NOSVE-NEXT:    ldr d0, [x8, :lo12:.LCPI1_0]
36; NONEON-NOSVE-NEXT:    str d0, [x0]
37; NONEON-NOSVE-NEXT:    ret
38  store <8 x i8> zeroinitializer, ptr %a
39  ret void
40}
41
42define void @store_v16i8(ptr %a) {
43; CHECK-LABEL: store_v16i8:
44; CHECK:       // %bb.0:
45; CHECK-NEXT:    mov z0.b, #0 // =0x0
46; CHECK-NEXT:    str q0, [x0]
47; CHECK-NEXT:    ret
48;
49; NONEON-NOSVE-LABEL: store_v16i8:
50; NONEON-NOSVE:       // %bb.0:
51; NONEON-NOSVE-NEXT:    adrp x8, .LCPI2_0
52; NONEON-NOSVE-NEXT:    ldr q0, [x8, :lo12:.LCPI2_0]
53; NONEON-NOSVE-NEXT:    str q0, [x0]
54; NONEON-NOSVE-NEXT:    ret
55  store <16 x i8> zeroinitializer, ptr %a
56  ret void
57}
58
59define void @store_v32i8(ptr %a) {
60; CHECK-LABEL: store_v32i8:
61; CHECK:       // %bb.0:
62; CHECK-NEXT:    mov z0.b, #0 // =0x0
63; CHECK-NEXT:    stp q0, q0, [x0]
64; CHECK-NEXT:    ret
65;
66; NONEON-NOSVE-LABEL: store_v32i8:
67; NONEON-NOSVE:       // %bb.0:
68; NONEON-NOSVE-NEXT:    adrp x8, .LCPI3_0
69; NONEON-NOSVE-NEXT:    ldr q0, [x8, :lo12:.LCPI3_0]
70; NONEON-NOSVE-NEXT:    stp q0, q0, [x0]
71; NONEON-NOSVE-NEXT:    ret
72  store <32 x i8> zeroinitializer, ptr %a
73  ret void
74}
75
76define void @store_v2i16(ptr %a) {
77; CHECK-LABEL: store_v2i16:
78; CHECK:       // %bb.0:
79; CHECK-NEXT:    mov z0.s, #0 // =0x0
80; CHECK-NEXT:    ptrue p0.s, vl2
81; CHECK-NEXT:    st1h { z0.s }, p0, [x0]
82; CHECK-NEXT:    ret
83;
84; NONEON-NOSVE-LABEL: store_v2i16:
85; NONEON-NOSVE:       // %bb.0:
86; NONEON-NOSVE-NEXT:    str wzr, [x0]
87; NONEON-NOSVE-NEXT:    ret
88  store <2 x i16> zeroinitializer, ptr %a
89  ret void
90}
91
92define void @store_v2f16(ptr %a) {
93; CHECK-LABEL: store_v2f16:
94; CHECK:       // %bb.0:
95; CHECK-NEXT:    mov z0.h, #0 // =0x0
96; CHECK-NEXT:    fmov w8, s0
97; CHECK-NEXT:    str w8, [x0]
98; CHECK-NEXT:    ret
99;
100; NONEON-NOSVE-LABEL: store_v2f16:
101; NONEON-NOSVE:       // %bb.0:
102; NONEON-NOSVE-NEXT:    sub sp, sp, #16
103; NONEON-NOSVE-NEXT:    .cfi_def_cfa_offset 16
104; NONEON-NOSVE-NEXT:    adrp x8, .LCPI5_0
105; NONEON-NOSVE-NEXT:    ldr d0, [x8, :lo12:.LCPI5_0]
106; NONEON-NOSVE-NEXT:    str d0, [sp, #8]
107; NONEON-NOSVE-NEXT:    ldr w8, [sp, #8]
108; NONEON-NOSVE-NEXT:    str w8, [x0]
109; NONEON-NOSVE-NEXT:    add sp, sp, #16
110; NONEON-NOSVE-NEXT:    ret
111  store <2 x half> zeroinitializer, ptr %a
112  ret void
113}
114
115define void @store_v4i16(ptr %a) {
116; CHECK-LABEL: store_v4i16:
117; CHECK:       // %bb.0:
118; CHECK-NEXT:    mov z0.h, #0 // =0x0
119; CHECK-NEXT:    str d0, [x0]
120; CHECK-NEXT:    ret
121;
122; NONEON-NOSVE-LABEL: store_v4i16:
123; NONEON-NOSVE:       // %bb.0:
124; NONEON-NOSVE-NEXT:    adrp x8, .LCPI6_0
125; NONEON-NOSVE-NEXT:    ldr d0, [x8, :lo12:.LCPI6_0]
126; NONEON-NOSVE-NEXT:    str d0, [x0]
127; NONEON-NOSVE-NEXT:    ret
128  store <4 x i16> zeroinitializer, ptr %a
129  ret void
130}
131
132define void @store_v4f16(ptr %a) {
133; CHECK-LABEL: store_v4f16:
134; CHECK:       // %bb.0:
135; CHECK-NEXT:    mov z0.h, #0 // =0x0
136; CHECK-NEXT:    str d0, [x0]
137; CHECK-NEXT:    ret
138;
139; NONEON-NOSVE-LABEL: store_v4f16:
140; NONEON-NOSVE:       // %bb.0:
141; NONEON-NOSVE-NEXT:    adrp x8, .LCPI7_0
142; NONEON-NOSVE-NEXT:    ldr d0, [x8, :lo12:.LCPI7_0]
143; NONEON-NOSVE-NEXT:    str d0, [x0]
144; NONEON-NOSVE-NEXT:    ret
145  store <4 x half> zeroinitializer, ptr %a
146  ret void
147}
148
149define void @store_v8i16(ptr %a) {
150; CHECK-LABEL: store_v8i16:
151; CHECK:       // %bb.0:
152; CHECK-NEXT:    mov z0.h, #0 // =0x0
153; CHECK-NEXT:    str q0, [x0]
154; CHECK-NEXT:    ret
155;
156; NONEON-NOSVE-LABEL: store_v8i16:
157; NONEON-NOSVE:       // %bb.0:
158; NONEON-NOSVE-NEXT:    adrp x8, .LCPI8_0
159; NONEON-NOSVE-NEXT:    ldr q0, [x8, :lo12:.LCPI8_0]
160; NONEON-NOSVE-NEXT:    str q0, [x0]
161; NONEON-NOSVE-NEXT:    ret
162  store <8 x i16> zeroinitializer, ptr %a
163  ret void
164}
165
166define void @store_v8f16(ptr %a) {
167; CHECK-LABEL: store_v8f16:
168; CHECK:       // %bb.0:
169; CHECK-NEXT:    mov z0.h, #0 // =0x0
170; CHECK-NEXT:    str q0, [x0]
171; CHECK-NEXT:    ret
172;
173; NONEON-NOSVE-LABEL: store_v8f16:
174; NONEON-NOSVE:       // %bb.0:
175; NONEON-NOSVE-NEXT:    adrp x8, .LCPI9_0
176; NONEON-NOSVE-NEXT:    ldr q0, [x8, :lo12:.LCPI9_0]
177; NONEON-NOSVE-NEXT:    str q0, [x0]
178; NONEON-NOSVE-NEXT:    ret
179  store <8 x half> zeroinitializer, ptr %a
180  ret void
181}
182
183define void @store_v16i16(ptr %a) {
184; CHECK-LABEL: store_v16i16:
185; CHECK:       // %bb.0:
186; CHECK-NEXT:    mov z0.h, #0 // =0x0
187; CHECK-NEXT:    stp q0, q0, [x0]
188; CHECK-NEXT:    ret
189;
190; NONEON-NOSVE-LABEL: store_v16i16:
191; NONEON-NOSVE:       // %bb.0:
192; NONEON-NOSVE-NEXT:    adrp x8, .LCPI10_0
193; NONEON-NOSVE-NEXT:    ldr q0, [x8, :lo12:.LCPI10_0]
194; NONEON-NOSVE-NEXT:    stp q0, q0, [x0]
195; NONEON-NOSVE-NEXT:    ret
196  store <16 x i16> zeroinitializer, ptr %a
197  ret void
198}
199
200define void @store_v16f16(ptr %a) {
201; CHECK-LABEL: store_v16f16:
202; CHECK:       // %bb.0:
203; CHECK-NEXT:    mov z0.h, #0 // =0x0
204; CHECK-NEXT:    stp q0, q0, [x0]
205; CHECK-NEXT:    ret
206;
207; NONEON-NOSVE-LABEL: store_v16f16:
208; NONEON-NOSVE:       // %bb.0:
209; NONEON-NOSVE-NEXT:    adrp x8, .LCPI11_0
210; NONEON-NOSVE-NEXT:    ldr q0, [x8, :lo12:.LCPI11_0]
211; NONEON-NOSVE-NEXT:    stp q0, q0, [x0]
212; NONEON-NOSVE-NEXT:    ret
213  store <16 x half> zeroinitializer, ptr %a
214  ret void
215}
216
217define void @store_v2i32(ptr %a) {
218; CHECK-LABEL: store_v2i32:
219; CHECK:       // %bb.0:
220; CHECK-NEXT:    str xzr, [x0]
221; CHECK-NEXT:    ret
222;
223; NONEON-NOSVE-LABEL: store_v2i32:
224; NONEON-NOSVE:       // %bb.0:
225; NONEON-NOSVE-NEXT:    str xzr, [x0]
226; NONEON-NOSVE-NEXT:    ret
227  store <2 x i32> zeroinitializer, ptr %a
228  ret void
229}
230
231define void @store_v2f32(ptr %a) {
232; CHECK-LABEL: store_v2f32:
233; CHECK:       // %bb.0:
234; CHECK-NEXT:    str xzr, [x0]
235; CHECK-NEXT:    ret
236;
237; NONEON-NOSVE-LABEL: store_v2f32:
238; NONEON-NOSVE:       // %bb.0:
239; NONEON-NOSVE-NEXT:    str xzr, [x0]
240; NONEON-NOSVE-NEXT:    ret
241  store <2 x float> zeroinitializer, ptr %a
242  ret void
243}
244
245define void @store_v4i32(ptr %a) {
246; CHECK-LABEL: store_v4i32:
247; CHECK:       // %bb.0:
248; CHECK-NEXT:    stp xzr, xzr, [x0]
249; CHECK-NEXT:    ret
250;
251; NONEON-NOSVE-LABEL: store_v4i32:
252; NONEON-NOSVE:       // %bb.0:
253; NONEON-NOSVE-NEXT:    stp xzr, xzr, [x0]
254; NONEON-NOSVE-NEXT:    ret
255  store <4 x i32> zeroinitializer, ptr %a
256  ret void
257}
258
259define void @store_v4f32(ptr %a) {
260; CHECK-LABEL: store_v4f32:
261; CHECK:       // %bb.0:
262; CHECK-NEXT:    stp xzr, xzr, [x0]
263; CHECK-NEXT:    ret
264;
265; NONEON-NOSVE-LABEL: store_v4f32:
266; NONEON-NOSVE:       // %bb.0:
267; NONEON-NOSVE-NEXT:    stp xzr, xzr, [x0]
268; NONEON-NOSVE-NEXT:    ret
269  store <4 x float> zeroinitializer, ptr %a
270  ret void
271}
272
273define void @store_v8i32(ptr %a) {
274; CHECK-LABEL: store_v8i32:
275; CHECK:       // %bb.0:
276; CHECK-NEXT:    mov z0.s, #0 // =0x0
277; CHECK-NEXT:    stp q0, q0, [x0]
278; CHECK-NEXT:    ret
279;
280; NONEON-NOSVE-LABEL: store_v8i32:
281; NONEON-NOSVE:       // %bb.0:
282; NONEON-NOSVE-NEXT:    adrp x8, .LCPI16_0
283; NONEON-NOSVE-NEXT:    ldr q0, [x8, :lo12:.LCPI16_0]
284; NONEON-NOSVE-NEXT:    stp q0, q0, [x0]
285; NONEON-NOSVE-NEXT:    ret
286  store <8 x i32> zeroinitializer, ptr %a
287  ret void
288}
289
290define void @store_v8f32(ptr %a) {
291; CHECK-LABEL: store_v8f32:
292; CHECK:       // %bb.0:
293; CHECK-NEXT:    mov z0.s, #0 // =0x0
294; CHECK-NEXT:    stp q0, q0, [x0]
295; CHECK-NEXT:    ret
296;
297; NONEON-NOSVE-LABEL: store_v8f32:
298; NONEON-NOSVE:       // %bb.0:
299; NONEON-NOSVE-NEXT:    adrp x8, .LCPI17_0
300; NONEON-NOSVE-NEXT:    ldr q0, [x8, :lo12:.LCPI17_0]
301; NONEON-NOSVE-NEXT:    stp q0, q0, [x0]
302; NONEON-NOSVE-NEXT:    ret
303  store <8 x float> zeroinitializer, ptr %a
304  ret void
305}
306
307define void @store_v1i64(ptr %a) {
308; CHECK-LABEL: store_v1i64:
309; CHECK:       // %bb.0:
310; CHECK-NEXT:    mov z0.d, #0 // =0x0
311; CHECK-NEXT:    str d0, [x0]
312; CHECK-NEXT:    ret
313;
314; NONEON-NOSVE-LABEL: store_v1i64:
315; NONEON-NOSVE:       // %bb.0:
316; NONEON-NOSVE-NEXT:    sub sp, sp, #16
317; NONEON-NOSVE-NEXT:    .cfi_def_cfa_offset 16
318; NONEON-NOSVE-NEXT:    str xzr, [sp, #8]
319; NONEON-NOSVE-NEXT:    ldr d0, [sp, #8]
320; NONEON-NOSVE-NEXT:    str d0, [x0]
321; NONEON-NOSVE-NEXT:    add sp, sp, #16
322; NONEON-NOSVE-NEXT:    ret
323  store <1 x i64> zeroinitializer, ptr %a
324  ret void
325}
326
327define void @store_v1f64(ptr %a) {
328; CHECK-LABEL: store_v1f64:
329; CHECK:       // %bb.0:
330; CHECK-NEXT:    fmov d0, xzr
331; CHECK-NEXT:    str d0, [x0]
332; CHECK-NEXT:    ret
333;
334; NONEON-NOSVE-LABEL: store_v1f64:
335; NONEON-NOSVE:       // %bb.0:
336; NONEON-NOSVE-NEXT:    sub sp, sp, #16
337; NONEON-NOSVE-NEXT:    .cfi_def_cfa_offset 16
338; NONEON-NOSVE-NEXT:    str xzr, [sp, #8]
339; NONEON-NOSVE-NEXT:    ldr d0, [sp, #8]
340; NONEON-NOSVE-NEXT:    str d0, [x0]
341; NONEON-NOSVE-NEXT:    add sp, sp, #16
342; NONEON-NOSVE-NEXT:    ret
343  store <1 x double> zeroinitializer, ptr %a
344  ret void
345}
346
347define void @store_v2i64(ptr %a) {
348; CHECK-LABEL: store_v2i64:
349; CHECK:       // %bb.0:
350; CHECK-NEXT:    stp xzr, xzr, [x0]
351; CHECK-NEXT:    ret
352;
353; NONEON-NOSVE-LABEL: store_v2i64:
354; NONEON-NOSVE:       // %bb.0:
355; NONEON-NOSVE-NEXT:    stp xzr, xzr, [x0]
356; NONEON-NOSVE-NEXT:    ret
357  store <2 x i64> zeroinitializer, ptr %a
358  ret void
359}
360
361define void @store_v2f64(ptr %a) {
362; CHECK-LABEL: store_v2f64:
363; CHECK:       // %bb.0:
364; CHECK-NEXT:    stp xzr, xzr, [x0]
365; CHECK-NEXT:    ret
366;
367; NONEON-NOSVE-LABEL: store_v2f64:
368; NONEON-NOSVE:       // %bb.0:
369; NONEON-NOSVE-NEXT:    stp xzr, xzr, [x0]
370; NONEON-NOSVE-NEXT:    ret
371  store <2 x double> zeroinitializer, ptr %a
372  ret void
373}
374
375define void @store_v4i64(ptr %a) {
376; CHECK-LABEL: store_v4i64:
377; CHECK:       // %bb.0:
378; CHECK-NEXT:    mov z0.d, #0 // =0x0
379; CHECK-NEXT:    stp q0, q0, [x0]
380; CHECK-NEXT:    ret
381;
382; NONEON-NOSVE-LABEL: store_v4i64:
383; NONEON-NOSVE:       // %bb.0:
384; NONEON-NOSVE-NEXT:    adrp x8, .LCPI22_0
385; NONEON-NOSVE-NEXT:    ldr q0, [x8, :lo12:.LCPI22_0]
386; NONEON-NOSVE-NEXT:    stp q0, q0, [x0]
387; NONEON-NOSVE-NEXT:    ret
388  store <4 x i64> zeroinitializer, ptr %a
389  ret void
390}
391
392define void @store_v4f64(ptr %a) {
393; CHECK-LABEL: store_v4f64:
394; CHECK:       // %bb.0:
395; CHECK-NEXT:    mov z0.d, #0 // =0x0
396; CHECK-NEXT:    stp q0, q0, [x0]
397; CHECK-NEXT:    ret
398;
399; NONEON-NOSVE-LABEL: store_v4f64:
400; NONEON-NOSVE:       // %bb.0:
401; NONEON-NOSVE-NEXT:    adrp x8, .LCPI23_0
402; NONEON-NOSVE-NEXT:    ldr q0, [x8, :lo12:.LCPI23_0]
403; NONEON-NOSVE-NEXT:    stp q0, q0, [x0]
404; NONEON-NOSVE-NEXT:    ret
405  store <4 x double> zeroinitializer, ptr %a
406  ret void
407}
408