1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc -mattr=+sve -force-streaming-compatible < %s | FileCheck %s 3; RUN: llc -mattr=+sme -force-streaming < %s | FileCheck %s 4 5 6target triple = "aarch64-unknown-linux-gnu" 7 8; == Matching first N elements == 9 10define <4 x i1> @reshuffle_v4i1_nxv4i1(<vscale x 4 x i1> %a) { 11; CHECK-LABEL: reshuffle_v4i1_nxv4i1: 12; CHECK: // %bb.0: 13; CHECK-NEXT: mov z0.s, p0/z, #1 // =0x1 14; CHECK-NEXT: mov z1.s, z0.s[3] 15; CHECK-NEXT: mov z2.s, z0.s[2] 16; CHECK-NEXT: mov z3.s, z0.s[1] 17; CHECK-NEXT: zip1 z1.h, z2.h, z1.h 18; CHECK-NEXT: zip1 z0.h, z0.h, z3.h 19; CHECK-NEXT: zip1 z0.s, z0.s, z1.s 20; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 21; CHECK-NEXT: ret 22 %el0 = extractelement <vscale x 4 x i1> %a, i32 0 23 %el1 = extractelement <vscale x 4 x i1> %a, i32 1 24 %el2 = extractelement <vscale x 4 x i1> %a, i32 2 25 %el3 = extractelement <vscale x 4 x i1> %a, i32 3 26 %v0 = insertelement <4 x i1> undef, i1 %el0, i32 0 27 %v1 = insertelement <4 x i1> %v0, i1 %el1, i32 1 28 %v2 = insertelement <4 x i1> %v1, i1 %el2, i32 2 29 %v3 = insertelement <4 x i1> %v2, i1 %el3, i32 3 30 ret <4 x i1> %v3 31} 32