xref: /llvm-project/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-log-reduce.ll (revision 8e0cd7382adacd8bc1741dc26bc0be6bdf8e238a) 
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mattr=+sve -force-streaming-compatible < %s | FileCheck %s
3; RUN: llc -mattr=+sme -force-streaming < %s | FileCheck %s
4; RUN: llc -force-streaming-compatible < %s | FileCheck %s --check-prefix=NONEON-NOSVE
5
6
7target triple = "aarch64-unknown-linux-gnu"
8
9;
10; ANDV
11;
12
13define i8 @andv_v4i8(<4 x i8> %a) {
14; CHECK-LABEL: andv_v4i8:
15; CHECK:       // %bb.0:
16; CHECK-NEXT:    ptrue p0.h, vl4
17; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
18; CHECK-NEXT:    andv h0, p0, z0.h
19; CHECK-NEXT:    fmov w0, s0
20; CHECK-NEXT:    ret
21;
22; NONEON-NOSVE-LABEL: andv_v4i8:
23; NONEON-NOSVE:       // %bb.0:
24; NONEON-NOSVE-NEXT:    sub sp, sp, #16
25; NONEON-NOSVE-NEXT:    .cfi_def_cfa_offset 16
26; NONEON-NOSVE-NEXT:    str d0, [sp, #8]
27; NONEON-NOSVE-NEXT:    ldrh w8, [sp, #14]
28; NONEON-NOSVE-NEXT:    ldrh w9, [sp, #12]
29; NONEON-NOSVE-NEXT:    ldrh w10, [sp, #10]
30; NONEON-NOSVE-NEXT:    ldrh w11, [sp, #8]
31; NONEON-NOSVE-NEXT:    and w8, w9, w8
32; NONEON-NOSVE-NEXT:    and w10, w11, w10
33; NONEON-NOSVE-NEXT:    and w0, w10, w8
34; NONEON-NOSVE-NEXT:    add sp, sp, #16
35; NONEON-NOSVE-NEXT:    ret
36  %res = call i8 @llvm.vector.reduce.and.v4i8(<4 x i8> %a)
37  ret i8 %res
38}
39
40define i8 @andv_v8i8(<8 x i8> %a) {
41; CHECK-LABEL: andv_v8i8:
42; CHECK:       // %bb.0:
43; CHECK-NEXT:    ptrue p0.b, vl8
44; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
45; CHECK-NEXT:    andv b0, p0, z0.b
46; CHECK-NEXT:    fmov w0, s0
47; CHECK-NEXT:    ret
48;
49; NONEON-NOSVE-LABEL: andv_v8i8:
50; NONEON-NOSVE:       // %bb.0:
51; NONEON-NOSVE-NEXT:    sub sp, sp, #16
52; NONEON-NOSVE-NEXT:    .cfi_def_cfa_offset 16
53; NONEON-NOSVE-NEXT:    str d0, [sp, #8]
54; NONEON-NOSVE-NEXT:    ldrb w8, [sp, #13]
55; NONEON-NOSVE-NEXT:    ldrb w9, [sp, #12]
56; NONEON-NOSVE-NEXT:    ldrb w10, [sp, #11]
57; NONEON-NOSVE-NEXT:    ldrb w11, [sp, #10]
58; NONEON-NOSVE-NEXT:    ldrb w12, [sp, #9]
59; NONEON-NOSVE-NEXT:    ldrb w13, [sp, #8]
60; NONEON-NOSVE-NEXT:    ldrb w14, [sp, #14]
61; NONEON-NOSVE-NEXT:    and w8, w9, w8
62; NONEON-NOSVE-NEXT:    ldrb w9, [sp, #15]
63; NONEON-NOSVE-NEXT:    and w12, w13, w12
64; NONEON-NOSVE-NEXT:    and w10, w11, w10
65; NONEON-NOSVE-NEXT:    and w10, w12, w10
66; NONEON-NOSVE-NEXT:    and w8, w8, w14
67; NONEON-NOSVE-NEXT:    and w8, w10, w8
68; NONEON-NOSVE-NEXT:    and w0, w8, w9
69; NONEON-NOSVE-NEXT:    add sp, sp, #16
70; NONEON-NOSVE-NEXT:    ret
71  %res = call i8 @llvm.vector.reduce.and.v8i8(<8 x i8> %a)
72  ret i8 %res
73}
74
75define i8 @andv_v16i8(<16 x i8> %a) {
76; CHECK-LABEL: andv_v16i8:
77; CHECK:       // %bb.0:
78; CHECK-NEXT:    ptrue p0.b, vl16
79; CHECK-NEXT:    // kill: def $q0 killed $q0 def $z0
80; CHECK-NEXT:    andv b0, p0, z0.b
81; CHECK-NEXT:    fmov w0, s0
82; CHECK-NEXT:    ret
83;
84; NONEON-NOSVE-LABEL: andv_v16i8:
85; NONEON-NOSVE:       // %bb.0:
86; NONEON-NOSVE-NEXT:    str q0, [sp, #-16]!
87; NONEON-NOSVE-NEXT:    .cfi_def_cfa_offset 16
88; NONEON-NOSVE-NEXT:    ldrb w9, [sp, #5]
89; NONEON-NOSVE-NEXT:    ldrb w10, [sp, #1]
90; NONEON-NOSVE-NEXT:    ldrb w11, [sp]
91; NONEON-NOSVE-NEXT:    ldrb w12, [sp, #4]
92; NONEON-NOSVE-NEXT:    ldrb w13, [sp, #3]
93; NONEON-NOSVE-NEXT:    ldrb w14, [sp, #2]
94; NONEON-NOSVE-NEXT:    and w10, w11, w10
95; NONEON-NOSVE-NEXT:    ldrb w8, [sp, #12]
96; NONEON-NOSVE-NEXT:    ldrb w15, [sp, #8]
97; NONEON-NOSVE-NEXT:    and w11, w14, w13
98; NONEON-NOSVE-NEXT:    and w9, w12, w9
99; NONEON-NOSVE-NEXT:    ldrb w16, [sp, #6]
100; NONEON-NOSVE-NEXT:    ldrb w12, [sp, #7]
101; NONEON-NOSVE-NEXT:    and w10, w10, w11
102; NONEON-NOSVE-NEXT:    ldrb w13, [sp, #11]
103; NONEON-NOSVE-NEXT:    ldrb w11, [sp, #13]
104; NONEON-NOSVE-NEXT:    and w9, w9, w16
105; NONEON-NOSVE-NEXT:    ldrb w14, [sp, #9]
106; NONEON-NOSVE-NEXT:    and w12, w12, w15
107; NONEON-NOSVE-NEXT:    ldrb w15, [sp, #14]
108; NONEON-NOSVE-NEXT:    and w8, w13, w8
109; NONEON-NOSVE-NEXT:    ldrb w16, [sp, #10]
110; NONEON-NOSVE-NEXT:    ldrb w13, [sp, #15]
111; NONEON-NOSVE-NEXT:    and w12, w12, w14
112; NONEON-NOSVE-NEXT:    and w8, w8, w11
113; NONEON-NOSVE-NEXT:    and w9, w10, w9
114; NONEON-NOSVE-NEXT:    and w10, w12, w16
115; NONEON-NOSVE-NEXT:    and w8, w8, w15
116; NONEON-NOSVE-NEXT:    and w9, w9, w10
117; NONEON-NOSVE-NEXT:    and w8, w8, w13
118; NONEON-NOSVE-NEXT:    and w0, w9, w8
119; NONEON-NOSVE-NEXT:    add sp, sp, #16
120; NONEON-NOSVE-NEXT:    ret
121  %res = call i8 @llvm.vector.reduce.and.v16i8(<16 x i8> %a)
122  ret i8 %res
123}
124
125define i8 @andv_v32i8(ptr %a) {
126; CHECK-LABEL: andv_v32i8:
127; CHECK:       // %bb.0:
128; CHECK-NEXT:    ldp q1, q0, [x0]
129; CHECK-NEXT:    ptrue p0.b, vl16
130; CHECK-NEXT:    and z0.d, z1.d, z0.d
131; CHECK-NEXT:    andv b0, p0, z0.b
132; CHECK-NEXT:    fmov w0, s0
133; CHECK-NEXT:    ret
134;
135; NONEON-NOSVE-LABEL: andv_v32i8:
136; NONEON-NOSVE:       // %bb.0:
137; NONEON-NOSVE-NEXT:    ldp q1, q0, [x0]
138; NONEON-NOSVE-NEXT:    stp q1, q0, [sp, #-32]!
139; NONEON-NOSVE-NEXT:    .cfi_def_cfa_offset 32
140; NONEON-NOSVE-NEXT:    ldrb w8, [sp, #17]
141; NONEON-NOSVE-NEXT:    ldrb w9, [sp, #1]
142; NONEON-NOSVE-NEXT:    ldrb w10, [sp, #16]
143; NONEON-NOSVE-NEXT:    ldrb w11, [sp]
144; NONEON-NOSVE-NEXT:    ldrb w12, [sp, #18]
145; NONEON-NOSVE-NEXT:    ldrb w13, [sp, #2]
146; NONEON-NOSVE-NEXT:    and w8, w9, w8
147; NONEON-NOSVE-NEXT:    ldrb w14, [sp, #19]
148; NONEON-NOSVE-NEXT:    ldrb w15, [sp, #3]
149; NONEON-NOSVE-NEXT:    and w9, w11, w10
150; NONEON-NOSVE-NEXT:    and w10, w13, w12
151; NONEON-NOSVE-NEXT:    ldrb w12, [sp, #21]
152; NONEON-NOSVE-NEXT:    ldrb w13, [sp, #5]
153; NONEON-NOSVE-NEXT:    and w11, w15, w14
154; NONEON-NOSVE-NEXT:    and w8, w9, w8
155; NONEON-NOSVE-NEXT:    ldrb w16, [sp, #20]
156; NONEON-NOSVE-NEXT:    ldrb w17, [sp, #4]
157; NONEON-NOSVE-NEXT:    and w9, w10, w11
158; NONEON-NOSVE-NEXT:    and w10, w13, w12
159; NONEON-NOSVE-NEXT:    ldrb w11, [sp, #22]
160; NONEON-NOSVE-NEXT:    ldrb w12, [sp, #6]
161; NONEON-NOSVE-NEXT:    and w14, w17, w16
162; NONEON-NOSVE-NEXT:    ldrb w13, [sp, #23]
163; NONEON-NOSVE-NEXT:    ldrb w15, [sp, #8]
164; NONEON-NOSVE-NEXT:    and w10, w14, w10
165; NONEON-NOSVE-NEXT:    ldrb w14, [sp, #7]
166; NONEON-NOSVE-NEXT:    and w11, w12, w11
167; NONEON-NOSVE-NEXT:    ldrb w12, [sp, #24]
168; NONEON-NOSVE-NEXT:    and w8, w8, w9
169; NONEON-NOSVE-NEXT:    and w9, w10, w11
170; NONEON-NOSVE-NEXT:    and w10, w14, w13
171; NONEON-NOSVE-NEXT:    ldrb w13, [sp, #9]
172; NONEON-NOSVE-NEXT:    and w8, w8, w9
173; NONEON-NOSVE-NEXT:    and w11, w15, w12
174; NONEON-NOSVE-NEXT:    ldrb w12, [sp, #25]
175; NONEON-NOSVE-NEXT:    ldrb w14, [sp, #26]
176; NONEON-NOSVE-NEXT:    and w9, w10, w11
177; NONEON-NOSVE-NEXT:    ldrb w11, [sp, #27]
178; NONEON-NOSVE-NEXT:    ldrb w15, [sp, #10]
179; NONEON-NOSVE-NEXT:    and w10, w13, w12
180; NONEON-NOSVE-NEXT:    ldrb w12, [sp, #11]
181; NONEON-NOSVE-NEXT:    ldrb w13, [sp, #12]
182; NONEON-NOSVE-NEXT:    and w9, w9, w10
183; NONEON-NOSVE-NEXT:    ldrb w10, [sp, #28]
184; NONEON-NOSVE-NEXT:    ldrb w16, [sp, #14]
185; NONEON-NOSVE-NEXT:    and w11, w12, w11
186; NONEON-NOSVE-NEXT:    ldrb w12, [sp, #29]
187; NONEON-NOSVE-NEXT:    ldrb w17, [sp, #15]
188; NONEON-NOSVE-NEXT:    and w10, w13, w10
189; NONEON-NOSVE-NEXT:    ldrb w13, [sp, #13]
190; NONEON-NOSVE-NEXT:    and w14, w15, w14
191; NONEON-NOSVE-NEXT:    and w10, w11, w10
192; NONEON-NOSVE-NEXT:    ldrb w11, [sp, #30]
193; NONEON-NOSVE-NEXT:    and w9, w9, w14
194; NONEON-NOSVE-NEXT:    and w12, w13, w12
195; NONEON-NOSVE-NEXT:    ldrb w13, [sp, #31]
196; NONEON-NOSVE-NEXT:    and w8, w8, w9
197; NONEON-NOSVE-NEXT:    and w10, w10, w12
198; NONEON-NOSVE-NEXT:    and w11, w16, w11
199; NONEON-NOSVE-NEXT:    and w10, w10, w11
200; NONEON-NOSVE-NEXT:    and w11, w17, w13
201; NONEON-NOSVE-NEXT:    and w9, w10, w11
202; NONEON-NOSVE-NEXT:    and w0, w8, w9
203; NONEON-NOSVE-NEXT:    add sp, sp, #32
204; NONEON-NOSVE-NEXT:    ret
205  %op = load <32 x i8>, ptr %a
206  %res = call i8 @llvm.vector.reduce.and.v32i8(<32 x i8> %op)
207  ret i8 %res
208}
209
210define i16 @andv_v2i16(<2 x i16> %a) {
211; CHECK-LABEL: andv_v2i16:
212; CHECK:       // %bb.0:
213; CHECK-NEXT:    ptrue p0.s, vl2
214; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
215; CHECK-NEXT:    andv s0, p0, z0.s
216; CHECK-NEXT:    fmov w0, s0
217; CHECK-NEXT:    ret
218;
219; NONEON-NOSVE-LABEL: andv_v2i16:
220; NONEON-NOSVE:       // %bb.0:
221; NONEON-NOSVE-NEXT:    sub sp, sp, #16
222; NONEON-NOSVE-NEXT:    .cfi_def_cfa_offset 16
223; NONEON-NOSVE-NEXT:    str d0, [sp, #8]
224; NONEON-NOSVE-NEXT:    ldp w9, w8, [sp, #8]
225; NONEON-NOSVE-NEXT:    and w0, w9, w8
226; NONEON-NOSVE-NEXT:    add sp, sp, #16
227; NONEON-NOSVE-NEXT:    ret
228  %res = call i16 @llvm.vector.reduce.and.v2i16(<2 x i16> %a)
229  ret i16 %res
230}
231
232define i16 @andv_v4i16(<4 x i16> %a) {
233; CHECK-LABEL: andv_v4i16:
234; CHECK:       // %bb.0:
235; CHECK-NEXT:    ptrue p0.h, vl4
236; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
237; CHECK-NEXT:    andv h0, p0, z0.h
238; CHECK-NEXT:    fmov w0, s0
239; CHECK-NEXT:    ret
240;
241; NONEON-NOSVE-LABEL: andv_v4i16:
242; NONEON-NOSVE:       // %bb.0:
243; NONEON-NOSVE-NEXT:    sub sp, sp, #16
244; NONEON-NOSVE-NEXT:    .cfi_def_cfa_offset 16
245; NONEON-NOSVE-NEXT:    str d0, [sp, #8]
246; NONEON-NOSVE-NEXT:    ldrh w8, [sp, #14]
247; NONEON-NOSVE-NEXT:    ldrh w9, [sp, #12]
248; NONEON-NOSVE-NEXT:    ldrh w10, [sp, #10]
249; NONEON-NOSVE-NEXT:    ldrh w11, [sp, #8]
250; NONEON-NOSVE-NEXT:    and w8, w9, w8
251; NONEON-NOSVE-NEXT:    and w10, w11, w10
252; NONEON-NOSVE-NEXT:    and w0, w10, w8
253; NONEON-NOSVE-NEXT:    add sp, sp, #16
254; NONEON-NOSVE-NEXT:    ret
255  %res = call i16 @llvm.vector.reduce.and.v4i16(<4 x i16> %a)
256  ret i16 %res
257}
258
259define i16 @andv_v8i16(<8 x i16> %a) {
260; CHECK-LABEL: andv_v8i16:
261; CHECK:       // %bb.0:
262; CHECK-NEXT:    ptrue p0.h, vl8
263; CHECK-NEXT:    // kill: def $q0 killed $q0 def $z0
264; CHECK-NEXT:    andv h0, p0, z0.h
265; CHECK-NEXT:    fmov w0, s0
266; CHECK-NEXT:    ret
267;
268; NONEON-NOSVE-LABEL: andv_v8i16:
269; NONEON-NOSVE:       // %bb.0:
270; NONEON-NOSVE-NEXT:    str q0, [sp, #-16]!
271; NONEON-NOSVE-NEXT:    .cfi_def_cfa_offset 16
272; NONEON-NOSVE-NEXT:    ldrh w8, [sp, #10]
273; NONEON-NOSVE-NEXT:    ldrh w9, [sp, #8]
274; NONEON-NOSVE-NEXT:    ldrh w10, [sp, #6]
275; NONEON-NOSVE-NEXT:    ldrh w11, [sp, #4]
276; NONEON-NOSVE-NEXT:    ldrh w12, [sp, #2]
277; NONEON-NOSVE-NEXT:    ldrh w13, [sp]
278; NONEON-NOSVE-NEXT:    and w8, w9, w8
279; NONEON-NOSVE-NEXT:    ldrh w14, [sp, #12]
280; NONEON-NOSVE-NEXT:    ldrh w9, [sp, #14]
281; NONEON-NOSVE-NEXT:    and w12, w13, w12
282; NONEON-NOSVE-NEXT:    and w10, w11, w10
283; NONEON-NOSVE-NEXT:    and w10, w12, w10
284; NONEON-NOSVE-NEXT:    and w8, w8, w14
285; NONEON-NOSVE-NEXT:    and w8, w10, w8
286; NONEON-NOSVE-NEXT:    and w0, w8, w9
287; NONEON-NOSVE-NEXT:    add sp, sp, #16
288; NONEON-NOSVE-NEXT:    ret
289  %res = call i16 @llvm.vector.reduce.and.v8i16(<8 x i16> %a)
290  ret i16 %res
291}
292
293define i16 @andv_v16i16(ptr %a) {
294; CHECK-LABEL: andv_v16i16:
295; CHECK:       // %bb.0:
296; CHECK-NEXT:    ldp q1, q0, [x0]
297; CHECK-NEXT:    ptrue p0.h, vl8
298; CHECK-NEXT:    and z0.d, z1.d, z0.d
299; CHECK-NEXT:    andv h0, p0, z0.h
300; CHECK-NEXT:    fmov w0, s0
301; CHECK-NEXT:    ret
302;
303; NONEON-NOSVE-LABEL: andv_v16i16:
304; NONEON-NOSVE:       // %bb.0:
305; NONEON-NOSVE-NEXT:    ldp q1, q0, [x0]
306; NONEON-NOSVE-NEXT:    stp q1, q0, [sp, #-32]!
307; NONEON-NOSVE-NEXT:    .cfi_def_cfa_offset 32
308; NONEON-NOSVE-NEXT:    ldrh w8, [sp, #18]
309; NONEON-NOSVE-NEXT:    ldrh w9, [sp, #2]
310; NONEON-NOSVE-NEXT:    ldrh w10, [sp, #16]
311; NONEON-NOSVE-NEXT:    ldrh w11, [sp]
312; NONEON-NOSVE-NEXT:    ldrh w12, [sp, #20]
313; NONEON-NOSVE-NEXT:    ldrh w13, [sp, #4]
314; NONEON-NOSVE-NEXT:    and w8, w9, w8
315; NONEON-NOSVE-NEXT:    ldrh w14, [sp, #22]
316; NONEON-NOSVE-NEXT:    ldrh w15, [sp, #6]
317; NONEON-NOSVE-NEXT:    and w9, w11, w10
318; NONEON-NOSVE-NEXT:    and w12, w13, w12
319; NONEON-NOSVE-NEXT:    ldrh w10, [sp, #26]
320; NONEON-NOSVE-NEXT:    ldrh w11, [sp, #10]
321; NONEON-NOSVE-NEXT:    and w13, w15, w14
322; NONEON-NOSVE-NEXT:    and w8, w9, w8
323; NONEON-NOSVE-NEXT:    ldrh w16, [sp, #24]
324; NONEON-NOSVE-NEXT:    ldrh w17, [sp, #8]
325; NONEON-NOSVE-NEXT:    and w9, w12, w13
326; NONEON-NOSVE-NEXT:    and w10, w11, w10
327; NONEON-NOSVE-NEXT:    ldrh w11, [sp, #28]
328; NONEON-NOSVE-NEXT:    ldrh w15, [sp, #12]
329; NONEON-NOSVE-NEXT:    and w14, w17, w16
330; NONEON-NOSVE-NEXT:    ldrh w12, [sp, #30]
331; NONEON-NOSVE-NEXT:    ldrh w13, [sp, #14]
332; NONEON-NOSVE-NEXT:    and w10, w14, w10
333; NONEON-NOSVE-NEXT:    and w11, w15, w11
334; NONEON-NOSVE-NEXT:    and w8, w8, w9
335; NONEON-NOSVE-NEXT:    and w9, w10, w11
336; NONEON-NOSVE-NEXT:    and w8, w8, w9
337; NONEON-NOSVE-NEXT:    and w9, w13, w12
338; NONEON-NOSVE-NEXT:    and w0, w8, w9
339; NONEON-NOSVE-NEXT:    add sp, sp, #32
340; NONEON-NOSVE-NEXT:    ret
341  %op = load <16 x i16>, ptr %a
342  %res = call i16 @llvm.vector.reduce.and.v16i16(<16 x i16> %op)
343  ret i16 %res
344}
345
346define i32 @andv_v2i32(<2 x i32> %a) {
347; CHECK-LABEL: andv_v2i32:
348; CHECK:       // %bb.0:
349; CHECK-NEXT:    ptrue p0.s, vl2
350; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
351; CHECK-NEXT:    andv s0, p0, z0.s
352; CHECK-NEXT:    fmov w0, s0
353; CHECK-NEXT:    ret
354;
355; NONEON-NOSVE-LABEL: andv_v2i32:
356; NONEON-NOSVE:       // %bb.0:
357; NONEON-NOSVE-NEXT:    sub sp, sp, #16
358; NONEON-NOSVE-NEXT:    .cfi_def_cfa_offset 16
359; NONEON-NOSVE-NEXT:    str d0, [sp, #8]
360; NONEON-NOSVE-NEXT:    ldp w9, w8, [sp, #8]
361; NONEON-NOSVE-NEXT:    and w0, w9, w8
362; NONEON-NOSVE-NEXT:    add sp, sp, #16
363; NONEON-NOSVE-NEXT:    ret
364  %res = call i32 @llvm.vector.reduce.and.v2i32(<2 x i32> %a)
365  ret i32 %res
366}
367
368define i32 @andv_v4i32(<4 x i32> %a) {
369; CHECK-LABEL: andv_v4i32:
370; CHECK:       // %bb.0:
371; CHECK-NEXT:    ptrue p0.s, vl4
372; CHECK-NEXT:    // kill: def $q0 killed $q0 def $z0
373; CHECK-NEXT:    andv s0, p0, z0.s
374; CHECK-NEXT:    fmov w0, s0
375; CHECK-NEXT:    ret
376;
377; NONEON-NOSVE-LABEL: andv_v4i32:
378; NONEON-NOSVE:       // %bb.0:
379; NONEON-NOSVE-NEXT:    str q0, [sp, #-16]!
380; NONEON-NOSVE-NEXT:    .cfi_def_cfa_offset 16
381; NONEON-NOSVE-NEXT:    ldp w9, w8, [sp, #8]
382; NONEON-NOSVE-NEXT:    ldp w11, w10, [sp], #16
383; NONEON-NOSVE-NEXT:    and w10, w11, w10
384; NONEON-NOSVE-NEXT:    and w8, w9, w8
385; NONEON-NOSVE-NEXT:    and w0, w10, w8
386; NONEON-NOSVE-NEXT:    ret
387  %res = call i32 @llvm.vector.reduce.and.v4i32(<4 x i32> %a)
388  ret i32 %res
389}
390
391define i32 @andv_v8i32(ptr %a) {
392; CHECK-LABEL: andv_v8i32:
393; CHECK:       // %bb.0:
394; CHECK-NEXT:    ldp q1, q0, [x0]
395; CHECK-NEXT:    ptrue p0.s, vl4
396; CHECK-NEXT:    and z0.d, z1.d, z0.d
397; CHECK-NEXT:    andv s0, p0, z0.s
398; CHECK-NEXT:    fmov w0, s0
399; CHECK-NEXT:    ret
400;
401; NONEON-NOSVE-LABEL: andv_v8i32:
402; NONEON-NOSVE:       // %bb.0:
403; NONEON-NOSVE-NEXT:    ldp q1, q0, [x0]
404; NONEON-NOSVE-NEXT:    stp q1, q0, [sp, #-32]!
405; NONEON-NOSVE-NEXT:    .cfi_def_cfa_offset 32
406; NONEON-NOSVE-NEXT:    ldp w9, w8, [sp, #16]
407; NONEON-NOSVE-NEXT:    ldp w11, w10, [sp]
408; NONEON-NOSVE-NEXT:    ldp w12, w13, [sp, #24]
409; NONEON-NOSVE-NEXT:    ldp w14, w15, [sp, #8]
410; NONEON-NOSVE-NEXT:    and w8, w10, w8
411; NONEON-NOSVE-NEXT:    and w9, w11, w9
412; NONEON-NOSVE-NEXT:    and w8, w9, w8
413; NONEON-NOSVE-NEXT:    and w10, w14, w12
414; NONEON-NOSVE-NEXT:    and w11, w15, w13
415; NONEON-NOSVE-NEXT:    and w9, w10, w11
416; NONEON-NOSVE-NEXT:    and w0, w8, w9
417; NONEON-NOSVE-NEXT:    add sp, sp, #32
418; NONEON-NOSVE-NEXT:    ret
419  %op = load <8 x i32>, ptr %a
420  %res = call i32 @llvm.vector.reduce.and.v8i32(<8 x i32> %op)
421  ret i32 %res
422}
423
424define i64 @andv_v2i64(<2 x i64> %a) {
425; CHECK-LABEL: andv_v2i64:
426; CHECK:       // %bb.0:
427; CHECK-NEXT:    ptrue p0.d, vl2
428; CHECK-NEXT:    // kill: def $q0 killed $q0 def $z0
429; CHECK-NEXT:    andv d0, p0, z0.d
430; CHECK-NEXT:    fmov x0, d0
431; CHECK-NEXT:    ret
432;
433; NONEON-NOSVE-LABEL: andv_v2i64:
434; NONEON-NOSVE:       // %bb.0:
435; NONEON-NOSVE-NEXT:    str q0, [sp, #-16]!
436; NONEON-NOSVE-NEXT:    .cfi_def_cfa_offset 16
437; NONEON-NOSVE-NEXT:    ldp x9, x8, [sp], #16
438; NONEON-NOSVE-NEXT:    and x0, x9, x8
439; NONEON-NOSVE-NEXT:    ret
440  %res = call i64 @llvm.vector.reduce.and.v2i64(<2 x i64> %a)
441  ret i64 %res
442}
443
444define i64 @andv_v4i64(ptr %a) {
445; CHECK-LABEL: andv_v4i64:
446; CHECK:       // %bb.0:
447; CHECK-NEXT:    ldp q1, q0, [x0]
448; CHECK-NEXT:    ptrue p0.d, vl2
449; CHECK-NEXT:    and z0.d, z1.d, z0.d
450; CHECK-NEXT:    andv d0, p0, z0.d
451; CHECK-NEXT:    fmov x0, d0
452; CHECK-NEXT:    ret
453;
454; NONEON-NOSVE-LABEL: andv_v4i64:
455; NONEON-NOSVE:       // %bb.0:
456; NONEON-NOSVE-NEXT:    ldp q1, q0, [x0]
457; NONEON-NOSVE-NEXT:    stp q1, q0, [sp, #-32]!
458; NONEON-NOSVE-NEXT:    .cfi_def_cfa_offset 32
459; NONEON-NOSVE-NEXT:    ldp x9, x8, [sp, #16]
460; NONEON-NOSVE-NEXT:    ldp x11, x10, [sp], #32
461; NONEON-NOSVE-NEXT:    and x8, x10, x8
462; NONEON-NOSVE-NEXT:    and x9, x11, x9
463; NONEON-NOSVE-NEXT:    and x0, x9, x8
464; NONEON-NOSVE-NEXT:    ret
465  %op = load <4 x i64>, ptr %a
466  %res = call i64 @llvm.vector.reduce.and.v4i64(<4 x i64> %op)
467  ret i64 %res
468}
469
470;
471; EORV
472;
473
474define i8 @eorv_v4i8(<4 x i8> %a) {
475; CHECK-LABEL: eorv_v4i8:
476; CHECK:       // %bb.0:
477; CHECK-NEXT:    ptrue p0.h, vl4
478; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
479; CHECK-NEXT:    eorv h0, p0, z0.h
480; CHECK-NEXT:    fmov w0, s0
481; CHECK-NEXT:    ret
482;
483; NONEON-NOSVE-LABEL: eorv_v4i8:
484; NONEON-NOSVE:       // %bb.0:
485; NONEON-NOSVE-NEXT:    sub sp, sp, #16
486; NONEON-NOSVE-NEXT:    .cfi_def_cfa_offset 16
487; NONEON-NOSVE-NEXT:    str d0, [sp, #8]
488; NONEON-NOSVE-NEXT:    ldrh w8, [sp, #14]
489; NONEON-NOSVE-NEXT:    ldrh w9, [sp, #12]
490; NONEON-NOSVE-NEXT:    ldrh w10, [sp, #10]
491; NONEON-NOSVE-NEXT:    ldrh w11, [sp, #8]
492; NONEON-NOSVE-NEXT:    eor w8, w9, w8
493; NONEON-NOSVE-NEXT:    eor w10, w11, w10
494; NONEON-NOSVE-NEXT:    eor w0, w10, w8
495; NONEON-NOSVE-NEXT:    add sp, sp, #16
496; NONEON-NOSVE-NEXT:    ret
497  %res = call i8 @llvm.vector.reduce.xor.v4i8(<4 x i8> %a)
498  ret i8 %res
499}
500
501define i8 @eorv_v8i8(<8 x i8> %a) {
502; CHECK-LABEL: eorv_v8i8:
503; CHECK:       // %bb.0:
504; CHECK-NEXT:    ptrue p0.b, vl8
505; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
506; CHECK-NEXT:    eorv b0, p0, z0.b
507; CHECK-NEXT:    fmov w0, s0
508; CHECK-NEXT:    ret
509;
510; NONEON-NOSVE-LABEL: eorv_v8i8:
511; NONEON-NOSVE:       // %bb.0:
512; NONEON-NOSVE-NEXT:    sub sp, sp, #16
513; NONEON-NOSVE-NEXT:    .cfi_def_cfa_offset 16
514; NONEON-NOSVE-NEXT:    str d0, [sp, #8]
515; NONEON-NOSVE-NEXT:    ldrb w8, [sp, #13]
516; NONEON-NOSVE-NEXT:    ldrb w9, [sp, #12]
517; NONEON-NOSVE-NEXT:    ldrb w10, [sp, #11]
518; NONEON-NOSVE-NEXT:    ldrb w11, [sp, #10]
519; NONEON-NOSVE-NEXT:    ldrb w12, [sp, #9]
520; NONEON-NOSVE-NEXT:    ldrb w13, [sp, #8]
521; NONEON-NOSVE-NEXT:    ldrb w14, [sp, #14]
522; NONEON-NOSVE-NEXT:    eor w8, w9, w8
523; NONEON-NOSVE-NEXT:    ldrb w9, [sp, #15]
524; NONEON-NOSVE-NEXT:    eor w12, w13, w12
525; NONEON-NOSVE-NEXT:    eor w10, w11, w10
526; NONEON-NOSVE-NEXT:    eor w10, w12, w10
527; NONEON-NOSVE-NEXT:    eor w8, w8, w14
528; NONEON-NOSVE-NEXT:    eor w8, w10, w8
529; NONEON-NOSVE-NEXT:    eor w0, w8, w9
530; NONEON-NOSVE-NEXT:    add sp, sp, #16
531; NONEON-NOSVE-NEXT:    ret
532  %res = call i8 @llvm.vector.reduce.xor.v8i8(<8 x i8> %a)
533  ret i8 %res
534}
535
536define i8 @eorv_v16i8(<16 x i8> %a) {
537; CHECK-LABEL: eorv_v16i8:
538; CHECK:       // %bb.0:
539; CHECK-NEXT:    ptrue p0.b, vl16
540; CHECK-NEXT:    // kill: def $q0 killed $q0 def $z0
541; CHECK-NEXT:    eorv b0, p0, z0.b
542; CHECK-NEXT:    fmov w0, s0
543; CHECK-NEXT:    ret
544;
545; NONEON-NOSVE-LABEL: eorv_v16i8:
546; NONEON-NOSVE:       // %bb.0:
547; NONEON-NOSVE-NEXT:    str q0, [sp, #-16]!
548; NONEON-NOSVE-NEXT:    .cfi_def_cfa_offset 16
549; NONEON-NOSVE-NEXT:    ldrb w9, [sp, #5]
550; NONEON-NOSVE-NEXT:    ldrb w10, [sp, #1]
551; NONEON-NOSVE-NEXT:    ldrb w11, [sp]
552; NONEON-NOSVE-NEXT:    ldrb w12, [sp, #4]
553; NONEON-NOSVE-NEXT:    ldrb w13, [sp, #3]
554; NONEON-NOSVE-NEXT:    ldrb w14, [sp, #2]
555; NONEON-NOSVE-NEXT:    eor w10, w11, w10
556; NONEON-NOSVE-NEXT:    ldrb w8, [sp, #12]
557; NONEON-NOSVE-NEXT:    ldrb w15, [sp, #8]
558; NONEON-NOSVE-NEXT:    eor w11, w14, w13
559; NONEON-NOSVE-NEXT:    eor w9, w12, w9
560; NONEON-NOSVE-NEXT:    ldrb w16, [sp, #6]
561; NONEON-NOSVE-NEXT:    ldrb w12, [sp, #7]
562; NONEON-NOSVE-NEXT:    eor w10, w10, w11
563; NONEON-NOSVE-NEXT:    ldrb w13, [sp, #11]
564; NONEON-NOSVE-NEXT:    ldrb w11, [sp, #13]
565; NONEON-NOSVE-NEXT:    eor w9, w9, w16
566; NONEON-NOSVE-NEXT:    ldrb w14, [sp, #9]
567; NONEON-NOSVE-NEXT:    eor w12, w12, w15
568; NONEON-NOSVE-NEXT:    ldrb w15, [sp, #14]
569; NONEON-NOSVE-NEXT:    eor w8, w13, w8
570; NONEON-NOSVE-NEXT:    ldrb w16, [sp, #10]
571; NONEON-NOSVE-NEXT:    ldrb w13, [sp, #15]
572; NONEON-NOSVE-NEXT:    eor w12, w12, w14
573; NONEON-NOSVE-NEXT:    eor w8, w8, w11
574; NONEON-NOSVE-NEXT:    eor w9, w10, w9
575; NONEON-NOSVE-NEXT:    eor w10, w12, w16
576; NONEON-NOSVE-NEXT:    eor w8, w8, w15
577; NONEON-NOSVE-NEXT:    eor w9, w9, w10
578; NONEON-NOSVE-NEXT:    eor w8, w8, w13
579; NONEON-NOSVE-NEXT:    eor w0, w9, w8
580; NONEON-NOSVE-NEXT:    add sp, sp, #16
581; NONEON-NOSVE-NEXT:    ret
582  %res = call i8 @llvm.vector.reduce.xor.v16i8(<16 x i8> %a)
583  ret i8 %res
584}
585
586define i8 @eorv_v32i8(ptr %a) {
587; CHECK-LABEL: eorv_v32i8:
588; CHECK:       // %bb.0:
589; CHECK-NEXT:    ldp q1, q0, [x0]
590; CHECK-NEXT:    ptrue p0.b, vl16
591; CHECK-NEXT:    eor z0.d, z1.d, z0.d
592; CHECK-NEXT:    eorv b0, p0, z0.b
593; CHECK-NEXT:    fmov w0, s0
594; CHECK-NEXT:    ret
595;
596; NONEON-NOSVE-LABEL: eorv_v32i8:
597; NONEON-NOSVE:       // %bb.0:
598; NONEON-NOSVE-NEXT:    ldp q1, q0, [x0]
599; NONEON-NOSVE-NEXT:    stp q1, q0, [sp, #-32]!
600; NONEON-NOSVE-NEXT:    .cfi_def_cfa_offset 32
601; NONEON-NOSVE-NEXT:    ldrb w8, [sp, #17]
602; NONEON-NOSVE-NEXT:    ldrb w9, [sp, #1]
603; NONEON-NOSVE-NEXT:    ldrb w10, [sp, #16]
604; NONEON-NOSVE-NEXT:    ldrb w11, [sp]
605; NONEON-NOSVE-NEXT:    ldrb w12, [sp, #18]
606; NONEON-NOSVE-NEXT:    ldrb w13, [sp, #2]
607; NONEON-NOSVE-NEXT:    eor w8, w9, w8
608; NONEON-NOSVE-NEXT:    ldrb w14, [sp, #19]
609; NONEON-NOSVE-NEXT:    ldrb w15, [sp, #3]
610; NONEON-NOSVE-NEXT:    eor w9, w11, w10
611; NONEON-NOSVE-NEXT:    eor w10, w13, w12
612; NONEON-NOSVE-NEXT:    ldrb w12, [sp, #21]
613; NONEON-NOSVE-NEXT:    ldrb w13, [sp, #5]
614; NONEON-NOSVE-NEXT:    eor w11, w15, w14
615; NONEON-NOSVE-NEXT:    eor w8, w9, w8
616; NONEON-NOSVE-NEXT:    ldrb w16, [sp, #20]
617; NONEON-NOSVE-NEXT:    ldrb w17, [sp, #4]
618; NONEON-NOSVE-NEXT:    eor w9, w10, w11
619; NONEON-NOSVE-NEXT:    eor w10, w13, w12
620; NONEON-NOSVE-NEXT:    ldrb w11, [sp, #22]
621; NONEON-NOSVE-NEXT:    ldrb w12, [sp, #6]
622; NONEON-NOSVE-NEXT:    eor w14, w17, w16
623; NONEON-NOSVE-NEXT:    ldrb w13, [sp, #23]
624; NONEON-NOSVE-NEXT:    ldrb w15, [sp, #8]
625; NONEON-NOSVE-NEXT:    eor w10, w14, w10
626; NONEON-NOSVE-NEXT:    ldrb w14, [sp, #7]
627; NONEON-NOSVE-NEXT:    eor w11, w12, w11
628; NONEON-NOSVE-NEXT:    ldrb w12, [sp, #24]
629; NONEON-NOSVE-NEXT:    eor w8, w8, w9
630; NONEON-NOSVE-NEXT:    eor w9, w10, w11
631; NONEON-NOSVE-NEXT:    eor w10, w14, w13
632; NONEON-NOSVE-NEXT:    ldrb w13, [sp, #9]
633; NONEON-NOSVE-NEXT:    eor w8, w8, w9
634; NONEON-NOSVE-NEXT:    eor w11, w15, w12
635; NONEON-NOSVE-NEXT:    ldrb w12, [sp, #25]
636; NONEON-NOSVE-NEXT:    ldrb w14, [sp, #26]
637; NONEON-NOSVE-NEXT:    eor w9, w10, w11
638; NONEON-NOSVE-NEXT:    ldrb w11, [sp, #27]
639; NONEON-NOSVE-NEXT:    ldrb w15, [sp, #10]
640; NONEON-NOSVE-NEXT:    eor w10, w13, w12
641; NONEON-NOSVE-NEXT:    ldrb w12, [sp, #11]
642; NONEON-NOSVE-NEXT:    ldrb w13, [sp, #12]
643; NONEON-NOSVE-NEXT:    eor w9, w9, w10
644; NONEON-NOSVE-NEXT:    ldrb w10, [sp, #28]
645; NONEON-NOSVE-NEXT:    ldrb w16, [sp, #14]
646; NONEON-NOSVE-NEXT:    eor w11, w12, w11
647; NONEON-NOSVE-NEXT:    ldrb w12, [sp, #29]
648; NONEON-NOSVE-NEXT:    ldrb w17, [sp, #15]
649; NONEON-NOSVE-NEXT:    eor w10, w13, w10
650; NONEON-NOSVE-NEXT:    ldrb w13, [sp, #13]
651; NONEON-NOSVE-NEXT:    eor w14, w15, w14
652; NONEON-NOSVE-NEXT:    eor w10, w11, w10
653; NONEON-NOSVE-NEXT:    ldrb w11, [sp, #30]
654; NONEON-NOSVE-NEXT:    eor w9, w9, w14
655; NONEON-NOSVE-NEXT:    eor w12, w13, w12
656; NONEON-NOSVE-NEXT:    ldrb w13, [sp, #31]
657; NONEON-NOSVE-NEXT:    eor w8, w8, w9
658; NONEON-NOSVE-NEXT:    eor w10, w10, w12
659; NONEON-NOSVE-NEXT:    eor w11, w16, w11
660; NONEON-NOSVE-NEXT:    eor w10, w10, w11
661; NONEON-NOSVE-NEXT:    eor w11, w17, w13
662; NONEON-NOSVE-NEXT:    eor w9, w10, w11
663; NONEON-NOSVE-NEXT:    eor w0, w8, w9
664; NONEON-NOSVE-NEXT:    add sp, sp, #32
665; NONEON-NOSVE-NEXT:    ret
666  %op = load <32 x i8>, ptr %a
667  %res = call i8 @llvm.vector.reduce.xor.v32i8(<32 x i8> %op)
668  ret i8 %res
669}
670
671define i16 @eorv_v2i16(<2 x i16> %a) {
672; CHECK-LABEL: eorv_v2i16:
673; CHECK:       // %bb.0:
674; CHECK-NEXT:    ptrue p0.s, vl2
675; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
676; CHECK-NEXT:    eorv s0, p0, z0.s
677; CHECK-NEXT:    fmov w0, s0
678; CHECK-NEXT:    ret
679;
680; NONEON-NOSVE-LABEL: eorv_v2i16:
681; NONEON-NOSVE:       // %bb.0:
682; NONEON-NOSVE-NEXT:    sub sp, sp, #16
683; NONEON-NOSVE-NEXT:    .cfi_def_cfa_offset 16
684; NONEON-NOSVE-NEXT:    str d0, [sp, #8]
685; NONEON-NOSVE-NEXT:    ldp w9, w8, [sp, #8]
686; NONEON-NOSVE-NEXT:    eor w0, w9, w8
687; NONEON-NOSVE-NEXT:    add sp, sp, #16
688; NONEON-NOSVE-NEXT:    ret
689  %res = call i16 @llvm.vector.reduce.xor.v2i16(<2 x i16> %a)
690  ret i16 %res
691}
692
693define i16 @eorv_v4i16(<4 x i16> %a) {
694; CHECK-LABEL: eorv_v4i16:
695; CHECK:       // %bb.0:
696; CHECK-NEXT:    ptrue p0.h, vl4
697; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
698; CHECK-NEXT:    eorv h0, p0, z0.h
699; CHECK-NEXT:    fmov w0, s0
700; CHECK-NEXT:    ret
701;
702; NONEON-NOSVE-LABEL: eorv_v4i16:
703; NONEON-NOSVE:       // %bb.0:
704; NONEON-NOSVE-NEXT:    sub sp, sp, #16
705; NONEON-NOSVE-NEXT:    .cfi_def_cfa_offset 16
706; NONEON-NOSVE-NEXT:    str d0, [sp, #8]
707; NONEON-NOSVE-NEXT:    ldrh w8, [sp, #14]
708; NONEON-NOSVE-NEXT:    ldrh w9, [sp, #12]
709; NONEON-NOSVE-NEXT:    ldrh w10, [sp, #10]
710; NONEON-NOSVE-NEXT:    ldrh w11, [sp, #8]
711; NONEON-NOSVE-NEXT:    eor w8, w9, w8
712; NONEON-NOSVE-NEXT:    eor w10, w11, w10
713; NONEON-NOSVE-NEXT:    eor w0, w10, w8
714; NONEON-NOSVE-NEXT:    add sp, sp, #16
715; NONEON-NOSVE-NEXT:    ret
716  %res = call i16 @llvm.vector.reduce.xor.v4i16(<4 x i16> %a)
717  ret i16 %res
718}
719
720define i16 @eorv_v8i16(<8 x i16> %a) {
721; CHECK-LABEL: eorv_v8i16:
722; CHECK:       // %bb.0:
723; CHECK-NEXT:    ptrue p0.h, vl8
724; CHECK-NEXT:    // kill: def $q0 killed $q0 def $z0
725; CHECK-NEXT:    eorv h0, p0, z0.h
726; CHECK-NEXT:    fmov w0, s0
727; CHECK-NEXT:    ret
728;
729; NONEON-NOSVE-LABEL: eorv_v8i16:
730; NONEON-NOSVE:       // %bb.0:
731; NONEON-NOSVE-NEXT:    str q0, [sp, #-16]!
732; NONEON-NOSVE-NEXT:    .cfi_def_cfa_offset 16
733; NONEON-NOSVE-NEXT:    ldrh w8, [sp, #10]
734; NONEON-NOSVE-NEXT:    ldrh w9, [sp, #8]
735; NONEON-NOSVE-NEXT:    ldrh w10, [sp, #6]
736; NONEON-NOSVE-NEXT:    ldrh w11, [sp, #4]
737; NONEON-NOSVE-NEXT:    ldrh w12, [sp, #2]
738; NONEON-NOSVE-NEXT:    ldrh w13, [sp]
739; NONEON-NOSVE-NEXT:    eor w8, w9, w8
740; NONEON-NOSVE-NEXT:    ldrh w14, [sp, #12]
741; NONEON-NOSVE-NEXT:    ldrh w9, [sp, #14]
742; NONEON-NOSVE-NEXT:    eor w12, w13, w12
743; NONEON-NOSVE-NEXT:    eor w10, w11, w10
744; NONEON-NOSVE-NEXT:    eor w10, w12, w10
745; NONEON-NOSVE-NEXT:    eor w8, w8, w14
746; NONEON-NOSVE-NEXT:    eor w8, w10, w8
747; NONEON-NOSVE-NEXT:    eor w0, w8, w9
748; NONEON-NOSVE-NEXT:    add sp, sp, #16
749; NONEON-NOSVE-NEXT:    ret
750  %res = call i16 @llvm.vector.reduce.xor.v8i16(<8 x i16> %a)
751  ret i16 %res
752}
753
754define i16 @eorv_v16i16(ptr %a) {
755; CHECK-LABEL: eorv_v16i16:
756; CHECK:       // %bb.0:
757; CHECK-NEXT:    ldp q1, q0, [x0]
758; CHECK-NEXT:    ptrue p0.h, vl8
759; CHECK-NEXT:    eor z0.d, z1.d, z0.d
760; CHECK-NEXT:    eorv h0, p0, z0.h
761; CHECK-NEXT:    fmov w0, s0
762; CHECK-NEXT:    ret
763;
764; NONEON-NOSVE-LABEL: eorv_v16i16:
765; NONEON-NOSVE:       // %bb.0:
766; NONEON-NOSVE-NEXT:    ldp q1, q0, [x0]
767; NONEON-NOSVE-NEXT:    stp q1, q0, [sp, #-32]!
768; NONEON-NOSVE-NEXT:    .cfi_def_cfa_offset 32
769; NONEON-NOSVE-NEXT:    ldrh w8, [sp, #18]
770; NONEON-NOSVE-NEXT:    ldrh w9, [sp, #2]
771; NONEON-NOSVE-NEXT:    ldrh w10, [sp, #16]
772; NONEON-NOSVE-NEXT:    ldrh w11, [sp]
773; NONEON-NOSVE-NEXT:    ldrh w12, [sp, #20]
774; NONEON-NOSVE-NEXT:    ldrh w13, [sp, #4]
775; NONEON-NOSVE-NEXT:    eor w8, w9, w8
776; NONEON-NOSVE-NEXT:    ldrh w14, [sp, #22]
777; NONEON-NOSVE-NEXT:    ldrh w15, [sp, #6]
778; NONEON-NOSVE-NEXT:    eor w9, w11, w10
779; NONEON-NOSVE-NEXT:    eor w12, w13, w12
780; NONEON-NOSVE-NEXT:    ldrh w10, [sp, #26]
781; NONEON-NOSVE-NEXT:    ldrh w11, [sp, #10]
782; NONEON-NOSVE-NEXT:    eor w13, w15, w14
783; NONEON-NOSVE-NEXT:    eor w8, w9, w8
784; NONEON-NOSVE-NEXT:    ldrh w16, [sp, #24]
785; NONEON-NOSVE-NEXT:    ldrh w17, [sp, #8]
786; NONEON-NOSVE-NEXT:    eor w9, w12, w13
787; NONEON-NOSVE-NEXT:    eor w10, w11, w10
788; NONEON-NOSVE-NEXT:    ldrh w11, [sp, #28]
789; NONEON-NOSVE-NEXT:    ldrh w15, [sp, #12]
790; NONEON-NOSVE-NEXT:    eor w14, w17, w16
791; NONEON-NOSVE-NEXT:    ldrh w12, [sp, #30]
792; NONEON-NOSVE-NEXT:    ldrh w13, [sp, #14]
793; NONEON-NOSVE-NEXT:    eor w10, w14, w10
794; NONEON-NOSVE-NEXT:    eor w11, w15, w11
795; NONEON-NOSVE-NEXT:    eor w8, w8, w9
796; NONEON-NOSVE-NEXT:    eor w9, w10, w11
797; NONEON-NOSVE-NEXT:    eor w8, w8, w9
798; NONEON-NOSVE-NEXT:    eor w9, w13, w12
799; NONEON-NOSVE-NEXT:    eor w0, w8, w9
800; NONEON-NOSVE-NEXT:    add sp, sp, #32
801; NONEON-NOSVE-NEXT:    ret
802  %op = load <16 x i16>, ptr %a
803  %res = call i16 @llvm.vector.reduce.xor.v16i16(<16 x i16> %op)
804  ret i16 %res
805}
806
807define i32 @eorv_v2i32(<2 x i32> %a) {
808; CHECK-LABEL: eorv_v2i32:
809; CHECK:       // %bb.0:
810; CHECK-NEXT:    ptrue p0.s, vl2
811; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
812; CHECK-NEXT:    eorv s0, p0, z0.s
813; CHECK-NEXT:    fmov w0, s0
814; CHECK-NEXT:    ret
815;
816; NONEON-NOSVE-LABEL: eorv_v2i32:
817; NONEON-NOSVE:       // %bb.0:
818; NONEON-NOSVE-NEXT:    sub sp, sp, #16
819; NONEON-NOSVE-NEXT:    .cfi_def_cfa_offset 16
820; NONEON-NOSVE-NEXT:    str d0, [sp, #8]
821; NONEON-NOSVE-NEXT:    ldp w9, w8, [sp, #8]
822; NONEON-NOSVE-NEXT:    eor w0, w9, w8
823; NONEON-NOSVE-NEXT:    add sp, sp, #16
824; NONEON-NOSVE-NEXT:    ret
825  %res = call i32 @llvm.vector.reduce.xor.v2i32(<2 x i32> %a)
826  ret i32 %res
827}
828
829define i32 @eorv_v4i32(<4 x i32> %a) {
830; CHECK-LABEL: eorv_v4i32:
831; CHECK:       // %bb.0:
832; CHECK-NEXT:    ptrue p0.s, vl4
833; CHECK-NEXT:    // kill: def $q0 killed $q0 def $z0
834; CHECK-NEXT:    eorv s0, p0, z0.s
835; CHECK-NEXT:    fmov w0, s0
836; CHECK-NEXT:    ret
837;
838; NONEON-NOSVE-LABEL: eorv_v4i32:
839; NONEON-NOSVE:       // %bb.0:
840; NONEON-NOSVE-NEXT:    str q0, [sp, #-16]!
841; NONEON-NOSVE-NEXT:    .cfi_def_cfa_offset 16
842; NONEON-NOSVE-NEXT:    ldp w9, w8, [sp, #8]
843; NONEON-NOSVE-NEXT:    ldp w11, w10, [sp], #16
844; NONEON-NOSVE-NEXT:    eor w10, w11, w10
845; NONEON-NOSVE-NEXT:    eor w8, w9, w8
846; NONEON-NOSVE-NEXT:    eor w0, w10, w8
847; NONEON-NOSVE-NEXT:    ret
848  %res = call i32 @llvm.vector.reduce.xor.v4i32(<4 x i32> %a)
849  ret i32 %res
850}
851
852define i32 @eorv_v8i32(ptr %a) {
853; CHECK-LABEL: eorv_v8i32:
854; CHECK:       // %bb.0:
855; CHECK-NEXT:    ldp q1, q0, [x0]
856; CHECK-NEXT:    ptrue p0.s, vl4
857; CHECK-NEXT:    eor z0.d, z1.d, z0.d
858; CHECK-NEXT:    eorv s0, p0, z0.s
859; CHECK-NEXT:    fmov w0, s0
860; CHECK-NEXT:    ret
861;
862; NONEON-NOSVE-LABEL: eorv_v8i32:
863; NONEON-NOSVE:       // %bb.0:
864; NONEON-NOSVE-NEXT:    ldp q1, q0, [x0]
865; NONEON-NOSVE-NEXT:    stp q1, q0, [sp, #-32]!
866; NONEON-NOSVE-NEXT:    .cfi_def_cfa_offset 32
867; NONEON-NOSVE-NEXT:    ldp w9, w8, [sp, #16]
868; NONEON-NOSVE-NEXT:    ldp w11, w10, [sp]
869; NONEON-NOSVE-NEXT:    ldp w12, w13, [sp, #24]
870; NONEON-NOSVE-NEXT:    ldp w14, w15, [sp, #8]
871; NONEON-NOSVE-NEXT:    eor w8, w10, w8
872; NONEON-NOSVE-NEXT:    eor w9, w11, w9
873; NONEON-NOSVE-NEXT:    eor w8, w9, w8
874; NONEON-NOSVE-NEXT:    eor w10, w14, w12
875; NONEON-NOSVE-NEXT:    eor w11, w15, w13
876; NONEON-NOSVE-NEXT:    eor w9, w10, w11
877; NONEON-NOSVE-NEXT:    eor w0, w8, w9
878; NONEON-NOSVE-NEXT:    add sp, sp, #32
879; NONEON-NOSVE-NEXT:    ret
880  %op = load <8 x i32>, ptr %a
881  %res = call i32 @llvm.vector.reduce.xor.v8i32(<8 x i32> %op)
882  ret i32 %res
883}
884
885define i64 @eorv_v2i64(<2 x i64> %a) {
886; CHECK-LABEL: eorv_v2i64:
887; CHECK:       // %bb.0:
888; CHECK-NEXT:    ptrue p0.d, vl2
889; CHECK-NEXT:    // kill: def $q0 killed $q0 def $z0
890; CHECK-NEXT:    eorv d0, p0, z0.d
891; CHECK-NEXT:    fmov x0, d0
892; CHECK-NEXT:    ret
893;
894; NONEON-NOSVE-LABEL: eorv_v2i64:
895; NONEON-NOSVE:       // %bb.0:
896; NONEON-NOSVE-NEXT:    str q0, [sp, #-16]!
897; NONEON-NOSVE-NEXT:    .cfi_def_cfa_offset 16
898; NONEON-NOSVE-NEXT:    ldp x9, x8, [sp], #16
899; NONEON-NOSVE-NEXT:    eor x0, x9, x8
900; NONEON-NOSVE-NEXT:    ret
901  %res = call i64 @llvm.vector.reduce.xor.v2i64(<2 x i64> %a)
902  ret i64 %res
903}
904
905define i64 @eorv_v4i64(ptr %a) {
906; CHECK-LABEL: eorv_v4i64:
907; CHECK:       // %bb.0:
908; CHECK-NEXT:    ldp q1, q0, [x0]
909; CHECK-NEXT:    ptrue p0.d, vl2
910; CHECK-NEXT:    eor z0.d, z1.d, z0.d
911; CHECK-NEXT:    eorv d0, p0, z0.d
912; CHECK-NEXT:    fmov x0, d0
913; CHECK-NEXT:    ret
914;
915; NONEON-NOSVE-LABEL: eorv_v4i64:
916; NONEON-NOSVE:       // %bb.0:
917; NONEON-NOSVE-NEXT:    ldp q1, q0, [x0]
918; NONEON-NOSVE-NEXT:    stp q1, q0, [sp, #-32]!
919; NONEON-NOSVE-NEXT:    .cfi_def_cfa_offset 32
920; NONEON-NOSVE-NEXT:    ldp x9, x8, [sp, #16]
921; NONEON-NOSVE-NEXT:    ldp x11, x10, [sp], #32
922; NONEON-NOSVE-NEXT:    eor x8, x10, x8
923; NONEON-NOSVE-NEXT:    eor x9, x11, x9
924; NONEON-NOSVE-NEXT:    eor x0, x9, x8
925; NONEON-NOSVE-NEXT:    ret
926  %op = load <4 x i64>, ptr %a
927  %res = call i64 @llvm.vector.reduce.xor.v4i64(<4 x i64> %op)
928  ret i64 %res
929}
930
931;
932; ORV
933;
934
935define i8 @orv_v4i8(<4 x i8> %a) {
936; CHECK-LABEL: orv_v4i8:
937; CHECK:       // %bb.0:
938; CHECK-NEXT:    ptrue p0.h, vl4
939; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
940; CHECK-NEXT:    orv h0, p0, z0.h
941; CHECK-NEXT:    fmov w0, s0
942; CHECK-NEXT:    ret
943;
944; NONEON-NOSVE-LABEL: orv_v4i8:
945; NONEON-NOSVE:       // %bb.0:
946; NONEON-NOSVE-NEXT:    sub sp, sp, #16
947; NONEON-NOSVE-NEXT:    .cfi_def_cfa_offset 16
948; NONEON-NOSVE-NEXT:    str d0, [sp, #8]
949; NONEON-NOSVE-NEXT:    ldrh w8, [sp, #14]
950; NONEON-NOSVE-NEXT:    ldrh w9, [sp, #12]
951; NONEON-NOSVE-NEXT:    ldrh w10, [sp, #10]
952; NONEON-NOSVE-NEXT:    ldrh w11, [sp, #8]
953; NONEON-NOSVE-NEXT:    orr w8, w9, w8
954; NONEON-NOSVE-NEXT:    orr w10, w11, w10
955; NONEON-NOSVE-NEXT:    orr w0, w10, w8
956; NONEON-NOSVE-NEXT:    add sp, sp, #16
957; NONEON-NOSVE-NEXT:    ret
958  %res = call i8 @llvm.vector.reduce.or.v4i8(<4 x i8> %a)
959  ret i8 %res
960}
961
962define i8 @orv_v8i8(<8 x i8> %a) {
963; CHECK-LABEL: orv_v8i8:
964; CHECK:       // %bb.0:
965; CHECK-NEXT:    ptrue p0.b, vl8
966; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
967; CHECK-NEXT:    orv b0, p0, z0.b
968; CHECK-NEXT:    fmov w0, s0
969; CHECK-NEXT:    ret
970;
971; NONEON-NOSVE-LABEL: orv_v8i8:
972; NONEON-NOSVE:       // %bb.0:
973; NONEON-NOSVE-NEXT:    sub sp, sp, #16
974; NONEON-NOSVE-NEXT:    .cfi_def_cfa_offset 16
975; NONEON-NOSVE-NEXT:    str d0, [sp, #8]
976; NONEON-NOSVE-NEXT:    ldrb w8, [sp, #13]
977; NONEON-NOSVE-NEXT:    ldrb w9, [sp, #12]
978; NONEON-NOSVE-NEXT:    ldrb w10, [sp, #11]
979; NONEON-NOSVE-NEXT:    ldrb w11, [sp, #10]
980; NONEON-NOSVE-NEXT:    ldrb w12, [sp, #9]
981; NONEON-NOSVE-NEXT:    ldrb w13, [sp, #8]
982; NONEON-NOSVE-NEXT:    ldrb w14, [sp, #14]
983; NONEON-NOSVE-NEXT:    orr w8, w9, w8
984; NONEON-NOSVE-NEXT:    ldrb w9, [sp, #15]
985; NONEON-NOSVE-NEXT:    orr w12, w13, w12
986; NONEON-NOSVE-NEXT:    orr w10, w11, w10
987; NONEON-NOSVE-NEXT:    orr w10, w12, w10
988; NONEON-NOSVE-NEXT:    orr w8, w8, w14
989; NONEON-NOSVE-NEXT:    orr w8, w10, w8
990; NONEON-NOSVE-NEXT:    orr w0, w8, w9
991; NONEON-NOSVE-NEXT:    add sp, sp, #16
992; NONEON-NOSVE-NEXT:    ret
993  %res = call i8 @llvm.vector.reduce.or.v8i8(<8 x i8> %a)
994  ret i8 %res
995}
996
997define i8 @orv_v16i8(<16 x i8> %a) {
998; CHECK-LABEL: orv_v16i8:
999; CHECK:       // %bb.0:
1000; CHECK-NEXT:    ptrue p0.b, vl16
1001; CHECK-NEXT:    // kill: def $q0 killed $q0 def $z0
1002; CHECK-NEXT:    orv b0, p0, z0.b
1003; CHECK-NEXT:    fmov w0, s0
1004; CHECK-NEXT:    ret
1005;
1006; NONEON-NOSVE-LABEL: orv_v16i8:
1007; NONEON-NOSVE:       // %bb.0:
1008; NONEON-NOSVE-NEXT:    str q0, [sp, #-16]!
1009; NONEON-NOSVE-NEXT:    .cfi_def_cfa_offset 16
1010; NONEON-NOSVE-NEXT:    ldrb w9, [sp, #5]
1011; NONEON-NOSVE-NEXT:    ldrb w10, [sp, #1]
1012; NONEON-NOSVE-NEXT:    ldrb w11, [sp]
1013; NONEON-NOSVE-NEXT:    ldrb w12, [sp, #4]
1014; NONEON-NOSVE-NEXT:    ldrb w13, [sp, #3]
1015; NONEON-NOSVE-NEXT:    ldrb w14, [sp, #2]
1016; NONEON-NOSVE-NEXT:    orr w10, w11, w10
1017; NONEON-NOSVE-NEXT:    ldrb w8, [sp, #12]
1018; NONEON-NOSVE-NEXT:    ldrb w15, [sp, #8]
1019; NONEON-NOSVE-NEXT:    orr w11, w14, w13
1020; NONEON-NOSVE-NEXT:    orr w9, w12, w9
1021; NONEON-NOSVE-NEXT:    ldrb w16, [sp, #6]
1022; NONEON-NOSVE-NEXT:    ldrb w12, [sp, #7]
1023; NONEON-NOSVE-NEXT:    orr w10, w10, w11
1024; NONEON-NOSVE-NEXT:    ldrb w13, [sp, #11]
1025; NONEON-NOSVE-NEXT:    ldrb w11, [sp, #13]
1026; NONEON-NOSVE-NEXT:    orr w9, w9, w16
1027; NONEON-NOSVE-NEXT:    ldrb w14, [sp, #9]
1028; NONEON-NOSVE-NEXT:    orr w12, w12, w15
1029; NONEON-NOSVE-NEXT:    ldrb w15, [sp, #14]
1030; NONEON-NOSVE-NEXT:    orr w8, w13, w8
1031; NONEON-NOSVE-NEXT:    ldrb w16, [sp, #10]
1032; NONEON-NOSVE-NEXT:    ldrb w13, [sp, #15]
1033; NONEON-NOSVE-NEXT:    orr w12, w12, w14
1034; NONEON-NOSVE-NEXT:    orr w8, w8, w11
1035; NONEON-NOSVE-NEXT:    orr w9, w10, w9
1036; NONEON-NOSVE-NEXT:    orr w10, w12, w16
1037; NONEON-NOSVE-NEXT:    orr w8, w8, w15
1038; NONEON-NOSVE-NEXT:    orr w9, w9, w10
1039; NONEON-NOSVE-NEXT:    orr w8, w8, w13
1040; NONEON-NOSVE-NEXT:    orr w0, w9, w8
1041; NONEON-NOSVE-NEXT:    add sp, sp, #16
1042; NONEON-NOSVE-NEXT:    ret
1043  %res = call i8 @llvm.vector.reduce.or.v16i8(<16 x i8> %a)
1044  ret i8 %res
1045}
1046
1047define i8 @orv_v32i8(ptr %a) {
1048; CHECK-LABEL: orv_v32i8:
1049; CHECK:       // %bb.0:
1050; CHECK-NEXT:    ldp q1, q0, [x0]
1051; CHECK-NEXT:    ptrue p0.b, vl16
1052; CHECK-NEXT:    orr z0.d, z1.d, z0.d
1053; CHECK-NEXT:    orv b0, p0, z0.b
1054; CHECK-NEXT:    fmov w0, s0
1055; CHECK-NEXT:    ret
1056;
1057; NONEON-NOSVE-LABEL: orv_v32i8:
1058; NONEON-NOSVE:       // %bb.0:
1059; NONEON-NOSVE-NEXT:    ldp q1, q0, [x0]
1060; NONEON-NOSVE-NEXT:    stp q1, q0, [sp, #-32]!
1061; NONEON-NOSVE-NEXT:    .cfi_def_cfa_offset 32
1062; NONEON-NOSVE-NEXT:    ldrb w8, [sp, #17]
1063; NONEON-NOSVE-NEXT:    ldrb w9, [sp, #1]
1064; NONEON-NOSVE-NEXT:    ldrb w10, [sp, #16]
1065; NONEON-NOSVE-NEXT:    ldrb w11, [sp]
1066; NONEON-NOSVE-NEXT:    ldrb w12, [sp, #18]
1067; NONEON-NOSVE-NEXT:    ldrb w13, [sp, #2]
1068; NONEON-NOSVE-NEXT:    orr w8, w9, w8
1069; NONEON-NOSVE-NEXT:    ldrb w14, [sp, #19]
1070; NONEON-NOSVE-NEXT:    ldrb w15, [sp, #3]
1071; NONEON-NOSVE-NEXT:    orr w9, w11, w10
1072; NONEON-NOSVE-NEXT:    orr w10, w13, w12
1073; NONEON-NOSVE-NEXT:    ldrb w12, [sp, #21]
1074; NONEON-NOSVE-NEXT:    ldrb w13, [sp, #5]
1075; NONEON-NOSVE-NEXT:    orr w11, w15, w14
1076; NONEON-NOSVE-NEXT:    orr w8, w9, w8
1077; NONEON-NOSVE-NEXT:    ldrb w16, [sp, #20]
1078; NONEON-NOSVE-NEXT:    ldrb w17, [sp, #4]
1079; NONEON-NOSVE-NEXT:    orr w9, w10, w11
1080; NONEON-NOSVE-NEXT:    orr w10, w13, w12
1081; NONEON-NOSVE-NEXT:    ldrb w11, [sp, #22]
1082; NONEON-NOSVE-NEXT:    ldrb w12, [sp, #6]
1083; NONEON-NOSVE-NEXT:    orr w14, w17, w16
1084; NONEON-NOSVE-NEXT:    ldrb w13, [sp, #23]
1085; NONEON-NOSVE-NEXT:    ldrb w15, [sp, #8]
1086; NONEON-NOSVE-NEXT:    orr w10, w14, w10
1087; NONEON-NOSVE-NEXT:    ldrb w14, [sp, #7]
1088; NONEON-NOSVE-NEXT:    orr w11, w12, w11
1089; NONEON-NOSVE-NEXT:    ldrb w12, [sp, #24]
1090; NONEON-NOSVE-NEXT:    orr w8, w8, w9
1091; NONEON-NOSVE-NEXT:    orr w9, w10, w11
1092; NONEON-NOSVE-NEXT:    orr w10, w14, w13
1093; NONEON-NOSVE-NEXT:    ldrb w13, [sp, #9]
1094; NONEON-NOSVE-NEXT:    orr w8, w8, w9
1095; NONEON-NOSVE-NEXT:    orr w11, w15, w12
1096; NONEON-NOSVE-NEXT:    ldrb w12, [sp, #25]
1097; NONEON-NOSVE-NEXT:    ldrb w14, [sp, #26]
1098; NONEON-NOSVE-NEXT:    orr w9, w10, w11
1099; NONEON-NOSVE-NEXT:    ldrb w11, [sp, #27]
1100; NONEON-NOSVE-NEXT:    ldrb w15, [sp, #10]
1101; NONEON-NOSVE-NEXT:    orr w10, w13, w12
1102; NONEON-NOSVE-NEXT:    ldrb w12, [sp, #11]
1103; NONEON-NOSVE-NEXT:    ldrb w13, [sp, #12]
1104; NONEON-NOSVE-NEXT:    orr w9, w9, w10
1105; NONEON-NOSVE-NEXT:    ldrb w10, [sp, #28]
1106; NONEON-NOSVE-NEXT:    ldrb w16, [sp, #14]
1107; NONEON-NOSVE-NEXT:    orr w11, w12, w11
1108; NONEON-NOSVE-NEXT:    ldrb w12, [sp, #29]
1109; NONEON-NOSVE-NEXT:    ldrb w17, [sp, #15]
1110; NONEON-NOSVE-NEXT:    orr w10, w13, w10
1111; NONEON-NOSVE-NEXT:    ldrb w13, [sp, #13]
1112; NONEON-NOSVE-NEXT:    orr w14, w15, w14
1113; NONEON-NOSVE-NEXT:    orr w10, w11, w10
1114; NONEON-NOSVE-NEXT:    ldrb w11, [sp, #30]
1115; NONEON-NOSVE-NEXT:    orr w9, w9, w14
1116; NONEON-NOSVE-NEXT:    orr w12, w13, w12
1117; NONEON-NOSVE-NEXT:    ldrb w13, [sp, #31]
1118; NONEON-NOSVE-NEXT:    orr w8, w8, w9
1119; NONEON-NOSVE-NEXT:    orr w10, w10, w12
1120; NONEON-NOSVE-NEXT:    orr w11, w16, w11
1121; NONEON-NOSVE-NEXT:    orr w10, w10, w11
1122; NONEON-NOSVE-NEXT:    orr w11, w17, w13
1123; NONEON-NOSVE-NEXT:    orr w9, w10, w11
1124; NONEON-NOSVE-NEXT:    orr w0, w8, w9
1125; NONEON-NOSVE-NEXT:    add sp, sp, #32
1126; NONEON-NOSVE-NEXT:    ret
1127  %op = load <32 x i8>, ptr %a
1128  %res = call i8 @llvm.vector.reduce.or.v32i8(<32 x i8> %op)
1129  ret i8 %res
1130}
1131
1132define i16 @orv_v2i16(<2 x i16> %a) {
1133; CHECK-LABEL: orv_v2i16:
1134; CHECK:       // %bb.0:
1135; CHECK-NEXT:    ptrue p0.s, vl2
1136; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
1137; CHECK-NEXT:    orv s0, p0, z0.s
1138; CHECK-NEXT:    fmov w0, s0
1139; CHECK-NEXT:    ret
1140;
1141; NONEON-NOSVE-LABEL: orv_v2i16:
1142; NONEON-NOSVE:       // %bb.0:
1143; NONEON-NOSVE-NEXT:    sub sp, sp, #16
1144; NONEON-NOSVE-NEXT:    .cfi_def_cfa_offset 16
1145; NONEON-NOSVE-NEXT:    str d0, [sp, #8]
1146; NONEON-NOSVE-NEXT:    ldp w9, w8, [sp, #8]
1147; NONEON-NOSVE-NEXT:    orr w0, w9, w8
1148; NONEON-NOSVE-NEXT:    add sp, sp, #16
1149; NONEON-NOSVE-NEXT:    ret
1150  %res = call i16 @llvm.vector.reduce.or.v2i16(<2 x i16> %a)
1151  ret i16 %res
1152}
1153
1154define i16 @orv_v4i16(<4 x i16> %a) {
1155; CHECK-LABEL: orv_v4i16:
1156; CHECK:       // %bb.0:
1157; CHECK-NEXT:    ptrue p0.h, vl4
1158; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
1159; CHECK-NEXT:    orv h0, p0, z0.h
1160; CHECK-NEXT:    fmov w0, s0
1161; CHECK-NEXT:    ret
1162;
1163; NONEON-NOSVE-LABEL: orv_v4i16:
1164; NONEON-NOSVE:       // %bb.0:
1165; NONEON-NOSVE-NEXT:    sub sp, sp, #16
1166; NONEON-NOSVE-NEXT:    .cfi_def_cfa_offset 16
1167; NONEON-NOSVE-NEXT:    str d0, [sp, #8]
1168; NONEON-NOSVE-NEXT:    ldrh w8, [sp, #14]
1169; NONEON-NOSVE-NEXT:    ldrh w9, [sp, #12]
1170; NONEON-NOSVE-NEXT:    ldrh w10, [sp, #10]
1171; NONEON-NOSVE-NEXT:    ldrh w11, [sp, #8]
1172; NONEON-NOSVE-NEXT:    orr w8, w9, w8
1173; NONEON-NOSVE-NEXT:    orr w10, w11, w10
1174; NONEON-NOSVE-NEXT:    orr w0, w10, w8
1175; NONEON-NOSVE-NEXT:    add sp, sp, #16
1176; NONEON-NOSVE-NEXT:    ret
1177  %res = call i16 @llvm.vector.reduce.or.v4i16(<4 x i16> %a)
1178  ret i16 %res
1179}
1180
1181define i16 @orv_v8i16(<8 x i16> %a) {
1182; CHECK-LABEL: orv_v8i16:
1183; CHECK:       // %bb.0:
1184; CHECK-NEXT:    ptrue p0.h, vl8
1185; CHECK-NEXT:    // kill: def $q0 killed $q0 def $z0
1186; CHECK-NEXT:    orv h0, p0, z0.h
1187; CHECK-NEXT:    fmov w0, s0
1188; CHECK-NEXT:    ret
1189;
1190; NONEON-NOSVE-LABEL: orv_v8i16:
1191; NONEON-NOSVE:       // %bb.0:
1192; NONEON-NOSVE-NEXT:    str q0, [sp, #-16]!
1193; NONEON-NOSVE-NEXT:    .cfi_def_cfa_offset 16
1194; NONEON-NOSVE-NEXT:    ldrh w8, [sp, #10]
1195; NONEON-NOSVE-NEXT:    ldrh w9, [sp, #8]
1196; NONEON-NOSVE-NEXT:    ldrh w10, [sp, #6]
1197; NONEON-NOSVE-NEXT:    ldrh w11, [sp, #4]
1198; NONEON-NOSVE-NEXT:    ldrh w12, [sp, #2]
1199; NONEON-NOSVE-NEXT:    ldrh w13, [sp]
1200; NONEON-NOSVE-NEXT:    orr w8, w9, w8
1201; NONEON-NOSVE-NEXT:    ldrh w14, [sp, #12]
1202; NONEON-NOSVE-NEXT:    ldrh w9, [sp, #14]
1203; NONEON-NOSVE-NEXT:    orr w12, w13, w12
1204; NONEON-NOSVE-NEXT:    orr w10, w11, w10
1205; NONEON-NOSVE-NEXT:    orr w10, w12, w10
1206; NONEON-NOSVE-NEXT:    orr w8, w8, w14
1207; NONEON-NOSVE-NEXT:    orr w8, w10, w8
1208; NONEON-NOSVE-NEXT:    orr w0, w8, w9
1209; NONEON-NOSVE-NEXT:    add sp, sp, #16
1210; NONEON-NOSVE-NEXT:    ret
1211  %res = call i16 @llvm.vector.reduce.or.v8i16(<8 x i16> %a)
1212  ret i16 %res
1213}
1214
1215define i16 @orv_v16i16(ptr %a) {
1216; CHECK-LABEL: orv_v16i16:
1217; CHECK:       // %bb.0:
1218; CHECK-NEXT:    ldp q1, q0, [x0]
1219; CHECK-NEXT:    ptrue p0.h, vl8
1220; CHECK-NEXT:    orr z0.d, z1.d, z0.d
1221; CHECK-NEXT:    orv h0, p0, z0.h
1222; CHECK-NEXT:    fmov w0, s0
1223; CHECK-NEXT:    ret
1224;
1225; NONEON-NOSVE-LABEL: orv_v16i16:
1226; NONEON-NOSVE:       // %bb.0:
1227; NONEON-NOSVE-NEXT:    ldp q1, q0, [x0]
1228; NONEON-NOSVE-NEXT:    stp q1, q0, [sp, #-32]!
1229; NONEON-NOSVE-NEXT:    .cfi_def_cfa_offset 32
1230; NONEON-NOSVE-NEXT:    ldrh w8, [sp, #18]
1231; NONEON-NOSVE-NEXT:    ldrh w9, [sp, #2]
1232; NONEON-NOSVE-NEXT:    ldrh w10, [sp, #16]
1233; NONEON-NOSVE-NEXT:    ldrh w11, [sp]
1234; NONEON-NOSVE-NEXT:    ldrh w12, [sp, #20]
1235; NONEON-NOSVE-NEXT:    ldrh w13, [sp, #4]
1236; NONEON-NOSVE-NEXT:    orr w8, w9, w8
1237; NONEON-NOSVE-NEXT:    ldrh w14, [sp, #22]
1238; NONEON-NOSVE-NEXT:    ldrh w15, [sp, #6]
1239; NONEON-NOSVE-NEXT:    orr w9, w11, w10
1240; NONEON-NOSVE-NEXT:    orr w12, w13, w12
1241; NONEON-NOSVE-NEXT:    ldrh w10, [sp, #26]
1242; NONEON-NOSVE-NEXT:    ldrh w11, [sp, #10]
1243; NONEON-NOSVE-NEXT:    orr w13, w15, w14
1244; NONEON-NOSVE-NEXT:    orr w8, w9, w8
1245; NONEON-NOSVE-NEXT:    ldrh w16, [sp, #24]
1246; NONEON-NOSVE-NEXT:    ldrh w17, [sp, #8]
1247; NONEON-NOSVE-NEXT:    orr w9, w12, w13
1248; NONEON-NOSVE-NEXT:    orr w10, w11, w10
1249; NONEON-NOSVE-NEXT:    ldrh w11, [sp, #28]
1250; NONEON-NOSVE-NEXT:    ldrh w15, [sp, #12]
1251; NONEON-NOSVE-NEXT:    orr w14, w17, w16
1252; NONEON-NOSVE-NEXT:    ldrh w12, [sp, #30]
1253; NONEON-NOSVE-NEXT:    ldrh w13, [sp, #14]
1254; NONEON-NOSVE-NEXT:    orr w10, w14, w10
1255; NONEON-NOSVE-NEXT:    orr w11, w15, w11
1256; NONEON-NOSVE-NEXT:    orr w8, w8, w9
1257; NONEON-NOSVE-NEXT:    orr w9, w10, w11
1258; NONEON-NOSVE-NEXT:    orr w8, w8, w9
1259; NONEON-NOSVE-NEXT:    orr w9, w13, w12
1260; NONEON-NOSVE-NEXT:    orr w0, w8, w9
1261; NONEON-NOSVE-NEXT:    add sp, sp, #32
1262; NONEON-NOSVE-NEXT:    ret
1263  %op = load <16 x i16>, ptr %a
1264  %res = call i16 @llvm.vector.reduce.or.v16i16(<16 x i16> %op)
1265  ret i16 %res
1266}
1267
1268define i32 @orv_v2i32(<2 x i32> %a) {
1269; CHECK-LABEL: orv_v2i32:
1270; CHECK:       // %bb.0:
1271; CHECK-NEXT:    ptrue p0.s, vl2
1272; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
1273; CHECK-NEXT:    orv s0, p0, z0.s
1274; CHECK-NEXT:    fmov w0, s0
1275; CHECK-NEXT:    ret
1276;
1277; NONEON-NOSVE-LABEL: orv_v2i32:
1278; NONEON-NOSVE:       // %bb.0:
1279; NONEON-NOSVE-NEXT:    sub sp, sp, #16
1280; NONEON-NOSVE-NEXT:    .cfi_def_cfa_offset 16
1281; NONEON-NOSVE-NEXT:    str d0, [sp, #8]
1282; NONEON-NOSVE-NEXT:    ldp w9, w8, [sp, #8]
1283; NONEON-NOSVE-NEXT:    orr w0, w9, w8
1284; NONEON-NOSVE-NEXT:    add sp, sp, #16
1285; NONEON-NOSVE-NEXT:    ret
1286  %res = call i32 @llvm.vector.reduce.or.v2i32(<2 x i32> %a)
1287  ret i32 %res
1288}
1289
1290define i32 @orv_v4i32(<4 x i32> %a) {
1291; CHECK-LABEL: orv_v4i32:
1292; CHECK:       // %bb.0:
1293; CHECK-NEXT:    ptrue p0.s, vl4
1294; CHECK-NEXT:    // kill: def $q0 killed $q0 def $z0
1295; CHECK-NEXT:    orv s0, p0, z0.s
1296; CHECK-NEXT:    fmov w0, s0
1297; CHECK-NEXT:    ret
1298;
1299; NONEON-NOSVE-LABEL: orv_v4i32:
1300; NONEON-NOSVE:       // %bb.0:
1301; NONEON-NOSVE-NEXT:    str q0, [sp, #-16]!
1302; NONEON-NOSVE-NEXT:    .cfi_def_cfa_offset 16
1303; NONEON-NOSVE-NEXT:    ldp w9, w8, [sp, #8]
1304; NONEON-NOSVE-NEXT:    ldp w11, w10, [sp], #16
1305; NONEON-NOSVE-NEXT:    orr w10, w11, w10
1306; NONEON-NOSVE-NEXT:    orr w8, w9, w8
1307; NONEON-NOSVE-NEXT:    orr w0, w10, w8
1308; NONEON-NOSVE-NEXT:    ret
1309  %res = call i32 @llvm.vector.reduce.or.v4i32(<4 x i32> %a)
1310  ret i32 %res
1311}
1312
1313define i32 @orv_v8i32(ptr %a) {
1314; CHECK-LABEL: orv_v8i32:
1315; CHECK:       // %bb.0:
1316; CHECK-NEXT:    ldp q1, q0, [x0]
1317; CHECK-NEXT:    ptrue p0.s, vl4
1318; CHECK-NEXT:    orr z0.d, z1.d, z0.d
1319; CHECK-NEXT:    orv s0, p0, z0.s
1320; CHECK-NEXT:    fmov w0, s0
1321; CHECK-NEXT:    ret
1322;
1323; NONEON-NOSVE-LABEL: orv_v8i32:
1324; NONEON-NOSVE:       // %bb.0:
1325; NONEON-NOSVE-NEXT:    ldp q1, q0, [x0]
1326; NONEON-NOSVE-NEXT:    stp q1, q0, [sp, #-32]!
1327; NONEON-NOSVE-NEXT:    .cfi_def_cfa_offset 32
1328; NONEON-NOSVE-NEXT:    ldp w9, w8, [sp, #16]
1329; NONEON-NOSVE-NEXT:    ldp w11, w10, [sp]
1330; NONEON-NOSVE-NEXT:    ldp w12, w13, [sp, #24]
1331; NONEON-NOSVE-NEXT:    ldp w14, w15, [sp, #8]
1332; NONEON-NOSVE-NEXT:    orr w8, w10, w8
1333; NONEON-NOSVE-NEXT:    orr w9, w11, w9
1334; NONEON-NOSVE-NEXT:    orr w8, w9, w8
1335; NONEON-NOSVE-NEXT:    orr w10, w14, w12
1336; NONEON-NOSVE-NEXT:    orr w11, w15, w13
1337; NONEON-NOSVE-NEXT:    orr w9, w10, w11
1338; NONEON-NOSVE-NEXT:    orr w0, w8, w9
1339; NONEON-NOSVE-NEXT:    add sp, sp, #32
1340; NONEON-NOSVE-NEXT:    ret
1341  %op = load <8 x i32>, ptr %a
1342  %res = call i32 @llvm.vector.reduce.or.v8i32(<8 x i32> %op)
1343  ret i32 %res
1344}
1345
1346define i64 @orv_v2i64(<2 x i64> %a) {
1347; CHECK-LABEL: orv_v2i64:
1348; CHECK:       // %bb.0:
1349; CHECK-NEXT:    ptrue p0.d, vl2
1350; CHECK-NEXT:    // kill: def $q0 killed $q0 def $z0
1351; CHECK-NEXT:    orv d0, p0, z0.d
1352; CHECK-NEXT:    fmov x0, d0
1353; CHECK-NEXT:    ret
1354;
1355; NONEON-NOSVE-LABEL: orv_v2i64:
1356; NONEON-NOSVE:       // %bb.0:
1357; NONEON-NOSVE-NEXT:    str q0, [sp, #-16]!
1358; NONEON-NOSVE-NEXT:    .cfi_def_cfa_offset 16
1359; NONEON-NOSVE-NEXT:    ldp x9, x8, [sp], #16
1360; NONEON-NOSVE-NEXT:    orr x0, x9, x8
1361; NONEON-NOSVE-NEXT:    ret
1362  %res = call i64 @llvm.vector.reduce.or.v2i64(<2 x i64> %a)
1363  ret i64 %res
1364}
1365
1366define i64 @orv_v4i64(ptr %a) {
1367; CHECK-LABEL: orv_v4i64:
1368; CHECK:       // %bb.0:
1369; CHECK-NEXT:    ldp q1, q0, [x0]
1370; CHECK-NEXT:    ptrue p0.d, vl2
1371; CHECK-NEXT:    orr z0.d, z1.d, z0.d
1372; CHECK-NEXT:    orv d0, p0, z0.d
1373; CHECK-NEXT:    fmov x0, d0
1374; CHECK-NEXT:    ret
1375;
1376; NONEON-NOSVE-LABEL: orv_v4i64:
1377; NONEON-NOSVE:       // %bb.0:
1378; NONEON-NOSVE-NEXT:    ldp q1, q0, [x0]
1379; NONEON-NOSVE-NEXT:    stp q1, q0, [sp, #-32]!
1380; NONEON-NOSVE-NEXT:    .cfi_def_cfa_offset 32
1381; NONEON-NOSVE-NEXT:    ldp x9, x8, [sp, #16]
1382; NONEON-NOSVE-NEXT:    ldp x11, x10, [sp], #32
1383; NONEON-NOSVE-NEXT:    orr x8, x10, x8
1384; NONEON-NOSVE-NEXT:    orr x9, x11, x9
1385; NONEON-NOSVE-NEXT:    orr x0, x9, x8
1386; NONEON-NOSVE-NEXT:    ret
1387  %op = load <4 x i64>, ptr %a
1388  %res = call i64 @llvm.vector.reduce.or.v4i64(<4 x i64> %op)
1389  ret i64 %res
1390}
1391
1392declare i8 @llvm.vector.reduce.and.v4i8(<4 x i8>)
1393declare i8 @llvm.vector.reduce.and.v8i8(<8 x i8>)
1394declare i8 @llvm.vector.reduce.and.v16i8(<16 x i8>)
1395declare i8 @llvm.vector.reduce.and.v32i8(<32 x i8>)
1396
1397declare i16 @llvm.vector.reduce.and.v2i16(<2 x i16>)
1398declare i16 @llvm.vector.reduce.and.v4i16(<4 x i16>)
1399declare i16 @llvm.vector.reduce.and.v8i16(<8 x i16>)
1400declare i16 @llvm.vector.reduce.and.v16i16(<16 x i16>)
1401
1402declare i32 @llvm.vector.reduce.and.v2i32(<2 x i32>)
1403declare i32 @llvm.vector.reduce.and.v4i32(<4 x i32>)
1404declare i32 @llvm.vector.reduce.and.v8i32(<8 x i32>)
1405
1406declare i64 @llvm.vector.reduce.and.v2i64(<2 x i64>)
1407declare i64 @llvm.vector.reduce.and.v4i64(<4 x i64>)
1408
1409declare i8 @llvm.vector.reduce.or.v4i8(<4 x i8>)
1410declare i8 @llvm.vector.reduce.or.v8i8(<8 x i8>)
1411declare i8 @llvm.vector.reduce.or.v16i8(<16 x i8>)
1412declare i8 @llvm.vector.reduce.or.v32i8(<32 x i8>)
1413
1414declare i16 @llvm.vector.reduce.or.v2i16(<2 x i16>)
1415declare i16 @llvm.vector.reduce.or.v4i16(<4 x i16>)
1416declare i16 @llvm.vector.reduce.or.v8i16(<8 x i16>)
1417declare i16 @llvm.vector.reduce.or.v16i16(<16 x i16>)
1418
1419declare i32 @llvm.vector.reduce.or.v2i32(<2 x i32>)
1420declare i32 @llvm.vector.reduce.or.v4i32(<4 x i32>)
1421declare i32 @llvm.vector.reduce.or.v8i32(<8 x i32>)
1422
1423declare i64 @llvm.vector.reduce.or.v2i64(<2 x i64>)
1424declare i64 @llvm.vector.reduce.or.v4i64(<4 x i64>)
1425
1426declare i8 @llvm.vector.reduce.xor.v4i8(<4 x i8>)
1427declare i8 @llvm.vector.reduce.xor.v8i8(<8 x i8>)
1428declare i8 @llvm.vector.reduce.xor.v16i8(<16 x i8>)
1429declare i8 @llvm.vector.reduce.xor.v32i8(<32 x i8>)
1430
1431declare i16 @llvm.vector.reduce.xor.v2i16(<2 x i16>)
1432declare i16 @llvm.vector.reduce.xor.v4i16(<4 x i16>)
1433declare i16 @llvm.vector.reduce.xor.v8i16(<8 x i16>)
1434declare i16 @llvm.vector.reduce.xor.v16i16(<16 x i16>)
1435
1436declare i32 @llvm.vector.reduce.xor.v2i32(<2 x i32>)
1437declare i32 @llvm.vector.reduce.xor.v4i32(<4 x i32>)
1438declare i32 @llvm.vector.reduce.xor.v8i32(<8 x i32>)
1439
1440declare i64 @llvm.vector.reduce.xor.v2i64(<2 x i64>)
1441declare i64 @llvm.vector.reduce.xor.v4i64(<4 x i64>)
1442