xref: /llvm-project/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-to-int.ll (revision ca98a3d9bbc254cbb7f028866a7d2077b7994ee8) 
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mattr=+sve -force-streaming-compatible  < %s | FileCheck %s
3; RUN: llc -force-streaming-compatible < %s | FileCheck %s --check-prefix=NONEON-NOSVE
4
5target triple = "aarch64-unknown-linux-gnu"
6
7;
8; FCVTZU H -> H
9;
10
11define <4 x i16> @fcvtzu_v4f16_v4i16(<4 x half> %op1) {
12; CHECK-LABEL: fcvtzu_v4f16_v4i16:
13; CHECK:       // %bb.0:
14; CHECK-NEXT:    ptrue p0.h, vl4
15; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
16; CHECK-NEXT:    fcvtzu z0.h, p0/m, z0.h
17; CHECK-NEXT:    // kill: def $d0 killed $d0 killed $z0
18; CHECK-NEXT:    ret
19;
20; NONEON-NOSVE-LABEL: fcvtzu_v4f16_v4i16:
21; NONEON-NOSVE:       // %bb.0:
22; NONEON-NOSVE-NEXT:    str d0, [sp, #-16]!
23; NONEON-NOSVE-NEXT:    .cfi_def_cfa_offset 16
24; NONEON-NOSVE-NEXT:    ldr h0, [sp, #6]
25; NONEON-NOSVE-NEXT:    fcvt s0, h0
26; NONEON-NOSVE-NEXT:    fcvtzs w8, s0
27; NONEON-NOSVE-NEXT:    ldr h0, [sp, #4]
28; NONEON-NOSVE-NEXT:    fcvt s0, h0
29; NONEON-NOSVE-NEXT:    strh w8, [sp, #14]
30; NONEON-NOSVE-NEXT:    fcvtzs w8, s0
31; NONEON-NOSVE-NEXT:    ldr h0, [sp, #2]
32; NONEON-NOSVE-NEXT:    fcvt s0, h0
33; NONEON-NOSVE-NEXT:    strh w8, [sp, #12]
34; NONEON-NOSVE-NEXT:    fcvtzs w8, s0
35; NONEON-NOSVE-NEXT:    ldr h0, [sp]
36; NONEON-NOSVE-NEXT:    fcvt s0, h0
37; NONEON-NOSVE-NEXT:    strh w8, [sp, #10]
38; NONEON-NOSVE-NEXT:    fcvtzs w8, s0
39; NONEON-NOSVE-NEXT:    strh w8, [sp, #8]
40; NONEON-NOSVE-NEXT:    ldr d0, [sp, #8]
41; NONEON-NOSVE-NEXT:    add sp, sp, #16
42; NONEON-NOSVE-NEXT:    ret
43  %res = fptoui <4 x half> %op1 to <4 x i16>
44  ret <4 x i16> %res
45}
46
47define void @fcvtzu_v8f16_v8i16(ptr %a, ptr %b) {
48; CHECK-LABEL: fcvtzu_v8f16_v8i16:
49; CHECK:       // %bb.0:
50; CHECK-NEXT:    ptrue p0.h, vl8
51; CHECK-NEXT:    ldr q0, [x0]
52; CHECK-NEXT:    fcvtzu z0.h, p0/m, z0.h
53; CHECK-NEXT:    str q0, [x1]
54; CHECK-NEXT:    ret
55;
56; NONEON-NOSVE-LABEL: fcvtzu_v8f16_v8i16:
57; NONEON-NOSVE:       // %bb.0:
58; NONEON-NOSVE-NEXT:    ldr q0, [x0]
59; NONEON-NOSVE-NEXT:    str q0, [sp, #-32]!
60; NONEON-NOSVE-NEXT:    .cfi_def_cfa_offset 32
61; NONEON-NOSVE-NEXT:    ldr h0, [sp, #14]
62; NONEON-NOSVE-NEXT:    fcvt s0, h0
63; NONEON-NOSVE-NEXT:    fcvtzs w8, s0
64; NONEON-NOSVE-NEXT:    ldr h0, [sp, #12]
65; NONEON-NOSVE-NEXT:    fcvt s0, h0
66; NONEON-NOSVE-NEXT:    strh w8, [sp, #30]
67; NONEON-NOSVE-NEXT:    fcvtzs w8, s0
68; NONEON-NOSVE-NEXT:    ldr h0, [sp, #10]
69; NONEON-NOSVE-NEXT:    fcvt s0, h0
70; NONEON-NOSVE-NEXT:    strh w8, [sp, #28]
71; NONEON-NOSVE-NEXT:    fcvtzs w8, s0
72; NONEON-NOSVE-NEXT:    ldr h0, [sp, #8]
73; NONEON-NOSVE-NEXT:    fcvt s0, h0
74; NONEON-NOSVE-NEXT:    strh w8, [sp, #26]
75; NONEON-NOSVE-NEXT:    fcvtzs w8, s0
76; NONEON-NOSVE-NEXT:    ldr h0, [sp, #6]
77; NONEON-NOSVE-NEXT:    fcvt s0, h0
78; NONEON-NOSVE-NEXT:    strh w8, [sp, #24]
79; NONEON-NOSVE-NEXT:    fcvtzs w8, s0
80; NONEON-NOSVE-NEXT:    ldr h0, [sp, #4]
81; NONEON-NOSVE-NEXT:    fcvt s0, h0
82; NONEON-NOSVE-NEXT:    strh w8, [sp, #22]
83; NONEON-NOSVE-NEXT:    fcvtzs w8, s0
84; NONEON-NOSVE-NEXT:    ldr h0, [sp, #2]
85; NONEON-NOSVE-NEXT:    fcvt s0, h0
86; NONEON-NOSVE-NEXT:    strh w8, [sp, #20]
87; NONEON-NOSVE-NEXT:    fcvtzs w8, s0
88; NONEON-NOSVE-NEXT:    ldr h0, [sp]
89; NONEON-NOSVE-NEXT:    fcvt s0, h0
90; NONEON-NOSVE-NEXT:    strh w8, [sp, #18]
91; NONEON-NOSVE-NEXT:    fcvtzs w8, s0
92; NONEON-NOSVE-NEXT:    strh w8, [sp, #16]
93; NONEON-NOSVE-NEXT:    ldr q0, [sp, #16]
94; NONEON-NOSVE-NEXT:    str q0, [x1]
95; NONEON-NOSVE-NEXT:    add sp, sp, #32
96; NONEON-NOSVE-NEXT:    ret
97  %op1 = load <8 x half>, ptr %a
98  %res = fptoui <8 x half> %op1 to <8 x i16>
99  store <8 x i16> %res, ptr %b
100  ret void
101}
102
103define void @fcvtzu_v16f16_v16i16(ptr %a, ptr %b) {
104; CHECK-LABEL: fcvtzu_v16f16_v16i16:
105; CHECK:       // %bb.0:
106; CHECK-NEXT:    ldp q0, q1, [x0]
107; CHECK-NEXT:    ptrue p0.h, vl8
108; CHECK-NEXT:    fcvtzu z0.h, p0/m, z0.h
109; CHECK-NEXT:    fcvtzu z1.h, p0/m, z1.h
110; CHECK-NEXT:    stp q0, q1, [x1]
111; CHECK-NEXT:    ret
112;
113; NONEON-NOSVE-LABEL: fcvtzu_v16f16_v16i16:
114; NONEON-NOSVE:       // %bb.0:
115; NONEON-NOSVE-NEXT:    ldp q1, q0, [x0]
116; NONEON-NOSVE-NEXT:    stp q1, q0, [sp, #-64]!
117; NONEON-NOSVE-NEXT:    .cfi_def_cfa_offset 64
118; NONEON-NOSVE-NEXT:    ldr h0, [sp, #30]
119; NONEON-NOSVE-NEXT:    fcvt s0, h0
120; NONEON-NOSVE-NEXT:    fcvtzs w8, s0
121; NONEON-NOSVE-NEXT:    ldr h0, [sp, #28]
122; NONEON-NOSVE-NEXT:    fcvt s0, h0
123; NONEON-NOSVE-NEXT:    strh w8, [sp, #62]
124; NONEON-NOSVE-NEXT:    fcvtzs w8, s0
125; NONEON-NOSVE-NEXT:    ldr h0, [sp, #26]
126; NONEON-NOSVE-NEXT:    fcvt s0, h0
127; NONEON-NOSVE-NEXT:    strh w8, [sp, #60]
128; NONEON-NOSVE-NEXT:    fcvtzs w8, s0
129; NONEON-NOSVE-NEXT:    ldr h0, [sp, #24]
130; NONEON-NOSVE-NEXT:    fcvt s0, h0
131; NONEON-NOSVE-NEXT:    strh w8, [sp, #58]
132; NONEON-NOSVE-NEXT:    fcvtzs w8, s0
133; NONEON-NOSVE-NEXT:    ldr h0, [sp, #22]
134; NONEON-NOSVE-NEXT:    fcvt s0, h0
135; NONEON-NOSVE-NEXT:    strh w8, [sp, #56]
136; NONEON-NOSVE-NEXT:    fcvtzs w8, s0
137; NONEON-NOSVE-NEXT:    ldr h0, [sp, #20]
138; NONEON-NOSVE-NEXT:    fcvt s0, h0
139; NONEON-NOSVE-NEXT:    strh w8, [sp, #54]
140; NONEON-NOSVE-NEXT:    fcvtzs w8, s0
141; NONEON-NOSVE-NEXT:    ldr h0, [sp, #18]
142; NONEON-NOSVE-NEXT:    fcvt s0, h0
143; NONEON-NOSVE-NEXT:    strh w8, [sp, #52]
144; NONEON-NOSVE-NEXT:    fcvtzs w8, s0
145; NONEON-NOSVE-NEXT:    ldr h0, [sp, #16]
146; NONEON-NOSVE-NEXT:    fcvt s0, h0
147; NONEON-NOSVE-NEXT:    strh w8, [sp, #50]
148; NONEON-NOSVE-NEXT:    fcvtzs w8, s0
149; NONEON-NOSVE-NEXT:    ldr h0, [sp, #14]
150; NONEON-NOSVE-NEXT:    fcvt s0, h0
151; NONEON-NOSVE-NEXT:    strh w8, [sp, #48]
152; NONEON-NOSVE-NEXT:    fcvtzs w8, s0
153; NONEON-NOSVE-NEXT:    ldr h0, [sp, #12]
154; NONEON-NOSVE-NEXT:    fcvt s0, h0
155; NONEON-NOSVE-NEXT:    strh w8, [sp, #46]
156; NONEON-NOSVE-NEXT:    fcvtzs w8, s0
157; NONEON-NOSVE-NEXT:    ldr h0, [sp, #10]
158; NONEON-NOSVE-NEXT:    fcvt s0, h0
159; NONEON-NOSVE-NEXT:    strh w8, [sp, #44]
160; NONEON-NOSVE-NEXT:    fcvtzs w8, s0
161; NONEON-NOSVE-NEXT:    ldr h0, [sp, #8]
162; NONEON-NOSVE-NEXT:    fcvt s0, h0
163; NONEON-NOSVE-NEXT:    strh w8, [sp, #42]
164; NONEON-NOSVE-NEXT:    fcvtzs w8, s0
165; NONEON-NOSVE-NEXT:    ldr h0, [sp, #6]
166; NONEON-NOSVE-NEXT:    fcvt s0, h0
167; NONEON-NOSVE-NEXT:    strh w8, [sp, #40]
168; NONEON-NOSVE-NEXT:    fcvtzs w8, s0
169; NONEON-NOSVE-NEXT:    ldr h0, [sp, #4]
170; NONEON-NOSVE-NEXT:    fcvt s0, h0
171; NONEON-NOSVE-NEXT:    strh w8, [sp, #38]
172; NONEON-NOSVE-NEXT:    fcvtzs w8, s0
173; NONEON-NOSVE-NEXT:    ldr h0, [sp, #2]
174; NONEON-NOSVE-NEXT:    fcvt s0, h0
175; NONEON-NOSVE-NEXT:    strh w8, [sp, #36]
176; NONEON-NOSVE-NEXT:    fcvtzs w8, s0
177; NONEON-NOSVE-NEXT:    ldr h0, [sp]
178; NONEON-NOSVE-NEXT:    fcvt s0, h0
179; NONEON-NOSVE-NEXT:    strh w8, [sp, #34]
180; NONEON-NOSVE-NEXT:    fcvtzs w8, s0
181; NONEON-NOSVE-NEXT:    strh w8, [sp, #32]
182; NONEON-NOSVE-NEXT:    ldp q0, q1, [sp, #32]
183; NONEON-NOSVE-NEXT:    stp q0, q1, [x1]
184; NONEON-NOSVE-NEXT:    add sp, sp, #64
185; NONEON-NOSVE-NEXT:    ret
186  %op1 = load <16 x half>, ptr %a
187  %res = fptoui <16 x half> %op1 to <16 x i16>
188  store <16 x i16> %res, ptr %b
189  ret void
190}
191
192;
193; FCVTZU H -> S
194;
195
196define <2 x i32> @fcvtzu_v2f16_v2i32(<2 x half> %op1) {
197; CHECK-LABEL: fcvtzu_v2f16_v2i32:
198; CHECK:       // %bb.0:
199; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
200; CHECK-NEXT:    ptrue p0.s, vl4
201; CHECK-NEXT:    uunpklo z0.s, z0.h
202; CHECK-NEXT:    fcvtzu z0.s, p0/m, z0.h
203; CHECK-NEXT:    // kill: def $d0 killed $d0 killed $z0
204; CHECK-NEXT:    ret
205;
206; NONEON-NOSVE-LABEL: fcvtzu_v2f16_v2i32:
207; NONEON-NOSVE:       // %bb.0:
208; NONEON-NOSVE-NEXT:    str d0, [sp, #-16]!
209; NONEON-NOSVE-NEXT:    .cfi_def_cfa_offset 16
210; NONEON-NOSVE-NEXT:    ldr h0, [sp, #2]
211; NONEON-NOSVE-NEXT:    fcvt s0, h0
212; NONEON-NOSVE-NEXT:    fcvtzu w9, s0
213; NONEON-NOSVE-NEXT:    ldr h0, [sp]
214; NONEON-NOSVE-NEXT:    fcvt s0, h0
215; NONEON-NOSVE-NEXT:    fcvtzu w8, s0
216; NONEON-NOSVE-NEXT:    stp w8, w9, [sp, #8]
217; NONEON-NOSVE-NEXT:    ldr d0, [sp, #8]
218; NONEON-NOSVE-NEXT:    add sp, sp, #16
219; NONEON-NOSVE-NEXT:    ret
220  %res = fptoui <2 x half> %op1 to <2 x i32>
221  ret <2 x i32> %res
222}
223
224define <4 x i32> @fcvtzu_v4f16_v4i32(<4 x half> %op1) {
225; CHECK-LABEL: fcvtzu_v4f16_v4i32:
226; CHECK:       // %bb.0:
227; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
228; CHECK-NEXT:    ptrue p0.s, vl4
229; CHECK-NEXT:    uunpklo z0.s, z0.h
230; CHECK-NEXT:    fcvtzu z0.s, p0/m, z0.h
231; CHECK-NEXT:    // kill: def $q0 killed $q0 killed $z0
232; CHECK-NEXT:    ret
233;
234; NONEON-NOSVE-LABEL: fcvtzu_v4f16_v4i32:
235; NONEON-NOSVE:       // %bb.0:
236; NONEON-NOSVE-NEXT:    sub sp, sp, #32
237; NONEON-NOSVE-NEXT:    .cfi_def_cfa_offset 32
238; NONEON-NOSVE-NEXT:    str d0, [sp, #8]
239; NONEON-NOSVE-NEXT:    ldr h0, [sp, #14]
240; NONEON-NOSVE-NEXT:    fcvt s0, h0
241; NONEON-NOSVE-NEXT:    fcvtzu w9, s0
242; NONEON-NOSVE-NEXT:    ldr h0, [sp, #12]
243; NONEON-NOSVE-NEXT:    fcvt s0, h0
244; NONEON-NOSVE-NEXT:    fcvtzu w8, s0
245; NONEON-NOSVE-NEXT:    ldr h0, [sp, #10]
246; NONEON-NOSVE-NEXT:    fcvt s0, h0
247; NONEON-NOSVE-NEXT:    stp w8, w9, [sp, #24]
248; NONEON-NOSVE-NEXT:    fcvtzu w9, s0
249; NONEON-NOSVE-NEXT:    ldr h0, [sp, #8]
250; NONEON-NOSVE-NEXT:    fcvt s0, h0
251; NONEON-NOSVE-NEXT:    fcvtzu w8, s0
252; NONEON-NOSVE-NEXT:    stp w8, w9, [sp, #16]
253; NONEON-NOSVE-NEXT:    ldr q0, [sp, #16]
254; NONEON-NOSVE-NEXT:    add sp, sp, #32
255; NONEON-NOSVE-NEXT:    ret
256  %res = fptoui <4 x half> %op1 to <4 x i32>
257  ret <4 x i32> %res
258}
259
260define void @fcvtzu_v8f16_v8i32(ptr %a, ptr %b) {
261; CHECK-LABEL: fcvtzu_v8f16_v8i32:
262; CHECK:       // %bb.0:
263; CHECK-NEXT:    ldr q0, [x0]
264; CHECK-NEXT:    ptrue p0.s, vl4
265; CHECK-NEXT:    uunpklo z1.s, z0.h
266; CHECK-NEXT:    ext z0.b, z0.b, z0.b, #8
267; CHECK-NEXT:    uunpklo z0.s, z0.h
268; CHECK-NEXT:    fcvtzu z1.s, p0/m, z1.h
269; CHECK-NEXT:    fcvtzu z0.s, p0/m, z0.h
270; CHECK-NEXT:    stp q1, q0, [x1]
271; CHECK-NEXT:    ret
272;
273; NONEON-NOSVE-LABEL: fcvtzu_v8f16_v8i32:
274; NONEON-NOSVE:       // %bb.0:
275; NONEON-NOSVE-NEXT:    ldr q0, [x0]
276; NONEON-NOSVE-NEXT:    str q0, [sp, #-64]!
277; NONEON-NOSVE-NEXT:    .cfi_def_cfa_offset 64
278; NONEON-NOSVE-NEXT:    ldp d1, d0, [sp]
279; NONEON-NOSVE-NEXT:    stp d0, d1, [sp, #16]
280; NONEON-NOSVE-NEXT:    ldr h0, [sp, #30]
281; NONEON-NOSVE-NEXT:    fcvt s0, h0
282; NONEON-NOSVE-NEXT:    fcvtzu w9, s0
283; NONEON-NOSVE-NEXT:    ldr h0, [sp, #28]
284; NONEON-NOSVE-NEXT:    fcvt s0, h0
285; NONEON-NOSVE-NEXT:    fcvtzu w8, s0
286; NONEON-NOSVE-NEXT:    ldr h0, [sp, #26]
287; NONEON-NOSVE-NEXT:    fcvt s0, h0
288; NONEON-NOSVE-NEXT:    stp w8, w9, [sp, #56]
289; NONEON-NOSVE-NEXT:    fcvtzu w9, s0
290; NONEON-NOSVE-NEXT:    ldr h0, [sp, #24]
291; NONEON-NOSVE-NEXT:    fcvt s0, h0
292; NONEON-NOSVE-NEXT:    fcvtzu w8, s0
293; NONEON-NOSVE-NEXT:    ldr h0, [sp, #22]
294; NONEON-NOSVE-NEXT:    fcvt s0, h0
295; NONEON-NOSVE-NEXT:    stp w8, w9, [sp, #48]
296; NONEON-NOSVE-NEXT:    fcvtzu w9, s0
297; NONEON-NOSVE-NEXT:    ldr h0, [sp, #20]
298; NONEON-NOSVE-NEXT:    fcvt s0, h0
299; NONEON-NOSVE-NEXT:    fcvtzu w8, s0
300; NONEON-NOSVE-NEXT:    ldr h0, [sp, #18]
301; NONEON-NOSVE-NEXT:    fcvt s0, h0
302; NONEON-NOSVE-NEXT:    stp w8, w9, [sp, #40]
303; NONEON-NOSVE-NEXT:    fcvtzu w9, s0
304; NONEON-NOSVE-NEXT:    ldr h0, [sp, #16]
305; NONEON-NOSVE-NEXT:    fcvt s0, h0
306; NONEON-NOSVE-NEXT:    fcvtzu w8, s0
307; NONEON-NOSVE-NEXT:    stp w8, w9, [sp, #32]
308; NONEON-NOSVE-NEXT:    ldp q0, q1, [sp, #32]
309; NONEON-NOSVE-NEXT:    stp q1, q0, [x1]
310; NONEON-NOSVE-NEXT:    add sp, sp, #64
311; NONEON-NOSVE-NEXT:    ret
312  %op1 = load <8 x half>, ptr %a
313  %res = fptoui <8 x half> %op1 to <8 x i32>
314  store <8 x i32> %res, ptr %b
315  ret void
316}
317
318define void @fcvtzu_v16f16_v16i32(ptr %a, ptr %b) {
319; CHECK-LABEL: fcvtzu_v16f16_v16i32:
320; CHECK:       // %bb.0:
321; CHECK-NEXT:    ldp q1, q0, [x0]
322; CHECK-NEXT:    ptrue p0.s, vl4
323; CHECK-NEXT:    uunpklo z2.s, z0.h
324; CHECK-NEXT:    ext z0.b, z0.b, z0.b, #8
325; CHECK-NEXT:    uunpklo z3.s, z1.h
326; CHECK-NEXT:    ext z1.b, z1.b, z1.b, #8
327; CHECK-NEXT:    uunpklo z0.s, z0.h
328; CHECK-NEXT:    uunpklo z1.s, z1.h
329; CHECK-NEXT:    fcvtzu z2.s, p0/m, z2.h
330; CHECK-NEXT:    fcvtzu z3.s, p0/m, z3.h
331; CHECK-NEXT:    fcvtzu z0.s, p0/m, z0.h
332; CHECK-NEXT:    fcvtzu z1.s, p0/m, z1.h
333; CHECK-NEXT:    stp q2, q0, [x1, #32]
334; CHECK-NEXT:    stp q3, q1, [x1]
335; CHECK-NEXT:    ret
336;
337; NONEON-NOSVE-LABEL: fcvtzu_v16f16_v16i32:
338; NONEON-NOSVE:       // %bb.0:
339; NONEON-NOSVE-NEXT:    ldp q0, q1, [x0]
340; NONEON-NOSVE-NEXT:    stp q0, q1, [sp, #-128]!
341; NONEON-NOSVE-NEXT:    .cfi_def_cfa_offset 128
342; NONEON-NOSVE-NEXT:    ldp d1, d0, [sp]
343; NONEON-NOSVE-NEXT:    stp d0, d1, [sp, #32]
344; NONEON-NOSVE-NEXT:    ldp d1, d0, [sp, #16]
345; NONEON-NOSVE-NEXT:    stp d0, d1, [sp, #48]
346; NONEON-NOSVE-NEXT:    ldr h0, [sp, #46]
347; NONEON-NOSVE-NEXT:    fcvt s0, h0
348; NONEON-NOSVE-NEXT:    fcvtzu w9, s0
349; NONEON-NOSVE-NEXT:    ldr h0, [sp, #44]
350; NONEON-NOSVE-NEXT:    fcvt s0, h0
351; NONEON-NOSVE-NEXT:    fcvtzu w8, s0
352; NONEON-NOSVE-NEXT:    ldr h0, [sp, #42]
353; NONEON-NOSVE-NEXT:    fcvt s0, h0
354; NONEON-NOSVE-NEXT:    stp w8, w9, [sp, #88]
355; NONEON-NOSVE-NEXT:    fcvtzu w9, s0
356; NONEON-NOSVE-NEXT:    ldr h0, [sp, #40]
357; NONEON-NOSVE-NEXT:    fcvt s0, h0
358; NONEON-NOSVE-NEXT:    fcvtzu w8, s0
359; NONEON-NOSVE-NEXT:    ldr h0, [sp, #38]
360; NONEON-NOSVE-NEXT:    fcvt s0, h0
361; NONEON-NOSVE-NEXT:    stp w8, w9, [sp, #80]
362; NONEON-NOSVE-NEXT:    fcvtzu w9, s0
363; NONEON-NOSVE-NEXT:    ldr h0, [sp, #36]
364; NONEON-NOSVE-NEXT:    fcvt s0, h0
365; NONEON-NOSVE-NEXT:    fcvtzu w8, s0
366; NONEON-NOSVE-NEXT:    ldr h0, [sp, #34]
367; NONEON-NOSVE-NEXT:    fcvt s0, h0
368; NONEON-NOSVE-NEXT:    stp w8, w9, [sp, #72]
369; NONEON-NOSVE-NEXT:    fcvtzu w9, s0
370; NONEON-NOSVE-NEXT:    ldr h0, [sp, #32]
371; NONEON-NOSVE-NEXT:    fcvt s0, h0
372; NONEON-NOSVE-NEXT:    fcvtzu w8, s0
373; NONEON-NOSVE-NEXT:    ldr h0, [sp, #62]
374; NONEON-NOSVE-NEXT:    fcvt s0, h0
375; NONEON-NOSVE-NEXT:    stp w8, w9, [sp, #64]
376; NONEON-NOSVE-NEXT:    ldp q3, q2, [sp, #64]
377; NONEON-NOSVE-NEXT:    fcvtzu w9, s0
378; NONEON-NOSVE-NEXT:    ldr h0, [sp, #60]
379; NONEON-NOSVE-NEXT:    fcvt s0, h0
380; NONEON-NOSVE-NEXT:    fcvtzu w8, s0
381; NONEON-NOSVE-NEXT:    ldr h0, [sp, #58]
382; NONEON-NOSVE-NEXT:    fcvt s0, h0
383; NONEON-NOSVE-NEXT:    stp w8, w9, [sp, #120]
384; NONEON-NOSVE-NEXT:    fcvtzu w9, s0
385; NONEON-NOSVE-NEXT:    ldr h0, [sp, #56]
386; NONEON-NOSVE-NEXT:    fcvt s0, h0
387; NONEON-NOSVE-NEXT:    fcvtzu w8, s0
388; NONEON-NOSVE-NEXT:    ldr h0, [sp, #54]
389; NONEON-NOSVE-NEXT:    fcvt s0, h0
390; NONEON-NOSVE-NEXT:    stp w8, w9, [sp, #112]
391; NONEON-NOSVE-NEXT:    fcvtzu w9, s0
392; NONEON-NOSVE-NEXT:    ldr h0, [sp, #52]
393; NONEON-NOSVE-NEXT:    fcvt s0, h0
394; NONEON-NOSVE-NEXT:    fcvtzu w8, s0
395; NONEON-NOSVE-NEXT:    ldr h0, [sp, #50]
396; NONEON-NOSVE-NEXT:    fcvt s0, h0
397; NONEON-NOSVE-NEXT:    stp w8, w9, [sp, #104]
398; NONEON-NOSVE-NEXT:    fcvtzu w9, s0
399; NONEON-NOSVE-NEXT:    ldr h0, [sp, #48]
400; NONEON-NOSVE-NEXT:    fcvt s0, h0
401; NONEON-NOSVE-NEXT:    fcvtzu w8, s0
402; NONEON-NOSVE-NEXT:    stp w8, w9, [sp, #96]
403; NONEON-NOSVE-NEXT:    ldp q0, q1, [sp, #96]
404; NONEON-NOSVE-NEXT:    stp q2, q3, [x1]
405; NONEON-NOSVE-NEXT:    stp q1, q0, [x1, #32]
406; NONEON-NOSVE-NEXT:    add sp, sp, #128
407; NONEON-NOSVE-NEXT:    ret
408  %op1 = load <16 x half>, ptr %a
409  %res = fptoui <16 x half> %op1 to <16 x i32>
410  store <16 x i32> %res, ptr %b
411  ret void
412}
413
414;
415; FCVTZU H -> D
416;
417
418define <1 x i64> @fcvtzu_v1f16_v1i64(<1 x half> %op1) {
419; CHECK-LABEL: fcvtzu_v1f16_v1i64:
420; CHECK:       // %bb.0:
421; CHECK-NEXT:    ptrue p0.d
422; CHECK-NEXT:    // kill: def $h0 killed $h0 def $z0
423; CHECK-NEXT:    fcvtzu z0.d, p0/m, z0.h
424; CHECK-NEXT:    // kill: def $d0 killed $d0 killed $z0
425; CHECK-NEXT:    ret
426;
427; NONEON-NOSVE-LABEL: fcvtzu_v1f16_v1i64:
428; NONEON-NOSVE:       // %bb.0:
429; NONEON-NOSVE-NEXT:    sub sp, sp, #16
430; NONEON-NOSVE-NEXT:    .cfi_def_cfa_offset 16
431; NONEON-NOSVE-NEXT:    fcvt s0, h0
432; NONEON-NOSVE-NEXT:    fcvtzu x8, s0
433; NONEON-NOSVE-NEXT:    str x8, [sp, #8]
434; NONEON-NOSVE-NEXT:    ldr d0, [sp, #8]
435; NONEON-NOSVE-NEXT:    add sp, sp, #16
436; NONEON-NOSVE-NEXT:    ret
437  %res = fptoui <1 x half> %op1 to <1 x i64>
438  ret <1 x i64> %res
439}
440
441define <2 x i64> @fcvtzu_v2f16_v2i64(<2 x half> %op1) {
442; CHECK-LABEL: fcvtzu_v2f16_v2i64:
443; CHECK:       // %bb.0:
444; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
445; CHECK-NEXT:    mov z1.h, z0.h[1]
446; CHECK-NEXT:    ptrue p0.d
447; CHECK-NEXT:    fcvtzu z0.d, p0/m, z0.h
448; CHECK-NEXT:    fcvtzu z1.d, p0/m, z1.h
449; CHECK-NEXT:    zip1 z0.d, z0.d, z1.d
450; CHECK-NEXT:    // kill: def $q0 killed $q0 killed $z0
451; CHECK-NEXT:    ret
452;
453; NONEON-NOSVE-LABEL: fcvtzu_v2f16_v2i64:
454; NONEON-NOSVE:       // %bb.0:
455; NONEON-NOSVE-NEXT:    sub sp, sp, #32
456; NONEON-NOSVE-NEXT:    .cfi_def_cfa_offset 32
457; NONEON-NOSVE-NEXT:    str d0, [sp, #8]
458; NONEON-NOSVE-NEXT:    ldr h0, [sp, #10]
459; NONEON-NOSVE-NEXT:    fcvt s0, h0
460; NONEON-NOSVE-NEXT:    fcvtzu x9, s0
461; NONEON-NOSVE-NEXT:    ldr h0, [sp, #8]
462; NONEON-NOSVE-NEXT:    fcvt s0, h0
463; NONEON-NOSVE-NEXT:    fcvtzu x8, s0
464; NONEON-NOSVE-NEXT:    stp x8, x9, [sp, #16]
465; NONEON-NOSVE-NEXT:    ldr q0, [sp, #16]
466; NONEON-NOSVE-NEXT:    add sp, sp, #32
467; NONEON-NOSVE-NEXT:    ret
468  %res = fptoui <2 x half> %op1 to <2 x i64>
469  ret <2 x i64> %res
470}
471
472define void @fcvtzu_v4f16_v4i64(ptr %a, ptr %b) {
473; CHECK-LABEL: fcvtzu_v4f16_v4i64:
474; CHECK:       // %bb.0:
475; CHECK-NEXT:    ldr d0, [x0]
476; CHECK-NEXT:    ptrue p0.d
477; CHECK-NEXT:    mov z1.h, z0.h[3]
478; CHECK-NEXT:    mov z2.h, z0.h[2]
479; CHECK-NEXT:    mov z3.h, z0.h[1]
480; CHECK-NEXT:    fcvtzu z0.d, p0/m, z0.h
481; CHECK-NEXT:    fcvtzu z1.d, p0/m, z1.h
482; CHECK-NEXT:    fcvtzu z2.d, p0/m, z2.h
483; CHECK-NEXT:    fcvtzu z3.d, p0/m, z3.h
484; CHECK-NEXT:    zip1 z1.d, z2.d, z1.d
485; CHECK-NEXT:    zip1 z0.d, z0.d, z3.d
486; CHECK-NEXT:    stp q0, q1, [x1]
487; CHECK-NEXT:    ret
488;
489; NONEON-NOSVE-LABEL: fcvtzu_v4f16_v4i64:
490; NONEON-NOSVE:       // %bb.0:
491; NONEON-NOSVE-NEXT:    sub sp, sp, #48
492; NONEON-NOSVE-NEXT:    .cfi_def_cfa_offset 48
493; NONEON-NOSVE-NEXT:    ldr d0, [x0]
494; NONEON-NOSVE-NEXT:    str d0, [sp, #8]
495; NONEON-NOSVE-NEXT:    ldr h0, [sp, #10]
496; NONEON-NOSVE-NEXT:    fcvt s0, h0
497; NONEON-NOSVE-NEXT:    fcvtzu x9, s0
498; NONEON-NOSVE-NEXT:    ldr h0, [sp, #8]
499; NONEON-NOSVE-NEXT:    fcvt s0, h0
500; NONEON-NOSVE-NEXT:    fcvtzu x8, s0
501; NONEON-NOSVE-NEXT:    ldr h0, [sp, #14]
502; NONEON-NOSVE-NEXT:    fcvt s0, h0
503; NONEON-NOSVE-NEXT:    stp x8, x9, [sp, #16]
504; NONEON-NOSVE-NEXT:    fcvtzu x9, s0
505; NONEON-NOSVE-NEXT:    ldr h0, [sp, #12]
506; NONEON-NOSVE-NEXT:    fcvt s0, h0
507; NONEON-NOSVE-NEXT:    fcvtzu x8, s0
508; NONEON-NOSVE-NEXT:    stp x8, x9, [sp, #32]
509; NONEON-NOSVE-NEXT:    ldp q1, q0, [sp, #16]
510; NONEON-NOSVE-NEXT:    stp q1, q0, [x1]
511; NONEON-NOSVE-NEXT:    add sp, sp, #48
512; NONEON-NOSVE-NEXT:    ret
513  %op1 = load <4 x half>, ptr %a
514  %res = fptoui <4 x half> %op1 to <4 x i64>
515  store <4 x i64> %res, ptr %b
516  ret void
517}
518
519define void @fcvtzu_v8f16_v8i64(ptr %a, ptr %b) {
520; CHECK-LABEL: fcvtzu_v8f16_v8i64:
521; CHECK:       // %bb.0:
522; CHECK-NEXT:    ldr q0, [x0]
523; CHECK-NEXT:    ptrue p0.d
524; CHECK-NEXT:    mov z1.d, z0.d
525; CHECK-NEXT:    mov z2.h, z0.h[3]
526; CHECK-NEXT:    mov z3.h, z0.h[2]
527; CHECK-NEXT:    mov z4.h, z0.h[1]
528; CHECK-NEXT:    ext z1.b, z1.b, z0.b, #8
529; CHECK-NEXT:    fcvtzu z2.d, p0/m, z2.h
530; CHECK-NEXT:    fcvtzu z3.d, p0/m, z3.h
531; CHECK-NEXT:    fcvtzu z0.d, p0/m, z0.h
532; CHECK-NEXT:    fcvtzu z4.d, p0/m, z4.h
533; CHECK-NEXT:    mov z5.h, z1.h[3]
534; CHECK-NEXT:    mov z6.h, z1.h[2]
535; CHECK-NEXT:    mov z7.h, z1.h[1]
536; CHECK-NEXT:    fcvtzu z1.d, p0/m, z1.h
537; CHECK-NEXT:    zip1 z2.d, z3.d, z2.d
538; CHECK-NEXT:    zip1 z0.d, z0.d, z4.d
539; CHECK-NEXT:    fcvtzu z5.d, p0/m, z5.h
540; CHECK-NEXT:    fcvtzu z6.d, p0/m, z6.h
541; CHECK-NEXT:    fcvtzu z7.d, p0/m, z7.h
542; CHECK-NEXT:    stp q0, q2, [x1]
543; CHECK-NEXT:    zip1 z3.d, z6.d, z5.d
544; CHECK-NEXT:    zip1 z1.d, z1.d, z7.d
545; CHECK-NEXT:    stp q1, q3, [x1, #32]
546; CHECK-NEXT:    ret
547;
548; NONEON-NOSVE-LABEL: fcvtzu_v8f16_v8i64:
549; NONEON-NOSVE:       // %bb.0:
550; NONEON-NOSVE-NEXT:    ldr q0, [x0]
551; NONEON-NOSVE-NEXT:    str q0, [sp, #-96]!
552; NONEON-NOSVE-NEXT:    .cfi_def_cfa_offset 96
553; NONEON-NOSVE-NEXT:    ldp d1, d0, [sp]
554; NONEON-NOSVE-NEXT:    stp d0, d1, [sp, #16]
555; NONEON-NOSVE-NEXT:    ldr h0, [sp, #26]
556; NONEON-NOSVE-NEXT:    fcvt s0, h0
557; NONEON-NOSVE-NEXT:    fcvtzu x9, s0
558; NONEON-NOSVE-NEXT:    ldr h0, [sp, #24]
559; NONEON-NOSVE-NEXT:    fcvt s0, h0
560; NONEON-NOSVE-NEXT:    fcvtzu x8, s0
561; NONEON-NOSVE-NEXT:    ldr h0, [sp, #30]
562; NONEON-NOSVE-NEXT:    fcvt s0, h0
563; NONEON-NOSVE-NEXT:    stp x8, x9, [sp, #64]
564; NONEON-NOSVE-NEXT:    fcvtzu x9, s0
565; NONEON-NOSVE-NEXT:    ldr h0, [sp, #28]
566; NONEON-NOSVE-NEXT:    fcvt s0, h0
567; NONEON-NOSVE-NEXT:    fcvtzu x8, s0
568; NONEON-NOSVE-NEXT:    ldr h0, [sp, #18]
569; NONEON-NOSVE-NEXT:    fcvt s0, h0
570; NONEON-NOSVE-NEXT:    stp x8, x9, [sp, #80]
571; NONEON-NOSVE-NEXT:    ldp q2, q3, [sp, #64]
572; NONEON-NOSVE-NEXT:    fcvtzu x9, s0
573; NONEON-NOSVE-NEXT:    ldr h0, [sp, #16]
574; NONEON-NOSVE-NEXT:    fcvt s0, h0
575; NONEON-NOSVE-NEXT:    fcvtzu x8, s0
576; NONEON-NOSVE-NEXT:    ldr h0, [sp, #22]
577; NONEON-NOSVE-NEXT:    fcvt s0, h0
578; NONEON-NOSVE-NEXT:    stp x8, x9, [sp, #32]
579; NONEON-NOSVE-NEXT:    fcvtzu x9, s0
580; NONEON-NOSVE-NEXT:    ldr h0, [sp, #20]
581; NONEON-NOSVE-NEXT:    fcvt s0, h0
582; NONEON-NOSVE-NEXT:    fcvtzu x8, s0
583; NONEON-NOSVE-NEXT:    stp x8, x9, [sp, #48]
584; NONEON-NOSVE-NEXT:    ldp q1, q0, [sp, #32]
585; NONEON-NOSVE-NEXT:    stp q2, q3, [x1]
586; NONEON-NOSVE-NEXT:    stp q1, q0, [x1, #32]
587; NONEON-NOSVE-NEXT:    add sp, sp, #96
588; NONEON-NOSVE-NEXT:    ret
589  %op1 = load <8 x half>, ptr %a
590  %res = fptoui <8 x half> %op1 to <8 x i64>
591  store <8 x i64> %res, ptr %b
592  ret void
593}
594
595define void @fcvtzu_v16f16_v16i64(ptr %a, ptr %b) {
596; CHECK-LABEL: fcvtzu_v16f16_v16i64:
597; CHECK:       // %bb.0:
598; CHECK-NEXT:    ldp q1, q0, [x0]
599; CHECK-NEXT:    ptrue p0.d
600; CHECK-NEXT:    mov z3.h, z1.h[1]
601; CHECK-NEXT:    mov z5.h, z0.h[3]
602; CHECK-NEXT:    mov z6.h, z0.h[2]
603; CHECK-NEXT:    mov z16.d, z0.d
604; CHECK-NEXT:    movprfx z2, z1
605; CHECK-NEXT:    fcvtzu z2.d, p0/m, z1.h
606; CHECK-NEXT:    mov z4.h, z1.h[3]
607; CHECK-NEXT:    mov z7.h, z1.h[2]
608; CHECK-NEXT:    mov z17.h, z0.h[1]
609; CHECK-NEXT:    ext z1.b, z1.b, z1.b, #8
610; CHECK-NEXT:    fcvtzu z3.d, p0/m, z3.h
611; CHECK-NEXT:    fcvtzu z5.d, p0/m, z5.h
612; CHECK-NEXT:    fcvtzu z6.d, p0/m, z6.h
613; CHECK-NEXT:    ext z16.b, z16.b, z0.b, #8
614; CHECK-NEXT:    fcvtzu z0.d, p0/m, z0.h
615; CHECK-NEXT:    fcvtzu z4.d, p0/m, z4.h
616; CHECK-NEXT:    fcvtzu z17.d, p0/m, z17.h
617; CHECK-NEXT:    fcvtzu z7.d, p0/m, z7.h
618; CHECK-NEXT:    mov z20.h, z1.h[3]
619; CHECK-NEXT:    mov z18.h, z16.h[3]
620; CHECK-NEXT:    mov z19.h, z16.h[2]
621; CHECK-NEXT:    mov z21.h, z16.h[1]
622; CHECK-NEXT:    zip1 z2.d, z2.d, z3.d
623; CHECK-NEXT:    mov z3.h, z1.h[2]
624; CHECK-NEXT:    zip1 z5.d, z6.d, z5.d
625; CHECK-NEXT:    mov z6.h, z1.h[1]
626; CHECK-NEXT:    zip1 z0.d, z0.d, z17.d
627; CHECK-NEXT:    fcvtzu z16.d, p0/m, z16.h
628; CHECK-NEXT:    fcvtzu z18.d, p0/m, z18.h
629; CHECK-NEXT:    movprfx z17, z21
630; CHECK-NEXT:    fcvtzu z17.d, p0/m, z21.h
631; CHECK-NEXT:    fcvtzu z19.d, p0/m, z19.h
632; CHECK-NEXT:    zip1 z4.d, z7.d, z4.d
633; CHECK-NEXT:    movprfx z7, z20
634; CHECK-NEXT:    fcvtzu z7.d, p0/m, z20.h
635; CHECK-NEXT:    fcvtzu z3.d, p0/m, z3.h
636; CHECK-NEXT:    fcvtzu z1.d, p0/m, z1.h
637; CHECK-NEXT:    stp q0, q5, [x1, #64]
638; CHECK-NEXT:    fcvtzu z6.d, p0/m, z6.h
639; CHECK-NEXT:    zip1 z0.d, z19.d, z18.d
640; CHECK-NEXT:    zip1 z5.d, z16.d, z17.d
641; CHECK-NEXT:    stp q2, q4, [x1]
642; CHECK-NEXT:    zip1 z2.d, z3.d, z7.d
643; CHECK-NEXT:    zip1 z1.d, z1.d, z6.d
644; CHECK-NEXT:    stp q5, q0, [x1, #96]
645; CHECK-NEXT:    stp q1, q2, [x1, #32]
646; CHECK-NEXT:    ret
647;
648; NONEON-NOSVE-LABEL: fcvtzu_v16f16_v16i64:
649; NONEON-NOSVE:       // %bb.0:
650; NONEON-NOSVE-NEXT:    sub sp, sp, #192
651; NONEON-NOSVE-NEXT:    .cfi_def_cfa_offset 192
652; NONEON-NOSVE-NEXT:    ldp q0, q1, [x0]
653; NONEON-NOSVE-NEXT:    stp q0, q1, [sp]
654; NONEON-NOSVE-NEXT:    ldp d1, d0, [sp]
655; NONEON-NOSVE-NEXT:    stp d0, d1, [sp, #32]
656; NONEON-NOSVE-NEXT:    ldp d1, d0, [sp, #16]
657; NONEON-NOSVE-NEXT:    stp d0, d1, [sp, #48]
658; NONEON-NOSVE-NEXT:    ldr h0, [sp, #42]
659; NONEON-NOSVE-NEXT:    fcvt s0, h0
660; NONEON-NOSVE-NEXT:    fcvtzu x9, s0
661; NONEON-NOSVE-NEXT:    ldr h0, [sp, #40]
662; NONEON-NOSVE-NEXT:    fcvt s0, h0
663; NONEON-NOSVE-NEXT:    fcvtzu x8, s0
664; NONEON-NOSVE-NEXT:    ldr h0, [sp, #46]
665; NONEON-NOSVE-NEXT:    fcvt s0, h0
666; NONEON-NOSVE-NEXT:    stp x8, x9, [sp, #96]
667; NONEON-NOSVE-NEXT:    fcvtzu x9, s0
668; NONEON-NOSVE-NEXT:    ldr h0, [sp, #44]
669; NONEON-NOSVE-NEXT:    fcvt s0, h0
670; NONEON-NOSVE-NEXT:    fcvtzu x8, s0
671; NONEON-NOSVE-NEXT:    ldr h0, [sp, #34]
672; NONEON-NOSVE-NEXT:    fcvt s0, h0
673; NONEON-NOSVE-NEXT:    stp x8, x9, [sp, #112]
674; NONEON-NOSVE-NEXT:    fcvtzu x9, s0
675; NONEON-NOSVE-NEXT:    ldr h0, [sp, #32]
676; NONEON-NOSVE-NEXT:    fcvt s0, h0
677; NONEON-NOSVE-NEXT:    fcvtzu x8, s0
678; NONEON-NOSVE-NEXT:    ldr h0, [sp, #38]
679; NONEON-NOSVE-NEXT:    fcvt s0, h0
680; NONEON-NOSVE-NEXT:    stp x8, x9, [sp, #64]
681; NONEON-NOSVE-NEXT:    fcvtzu x9, s0
682; NONEON-NOSVE-NEXT:    ldr h0, [sp, #36]
683; NONEON-NOSVE-NEXT:    fcvt s0, h0
684; NONEON-NOSVE-NEXT:    fcvtzu x8, s0
685; NONEON-NOSVE-NEXT:    ldr h0, [sp, #58]
686; NONEON-NOSVE-NEXT:    fcvt s0, h0
687; NONEON-NOSVE-NEXT:    stp x8, x9, [sp, #80]
688; NONEON-NOSVE-NEXT:    ldp q3, q4, [sp, #64]
689; NONEON-NOSVE-NEXT:    fcvtzu x9, s0
690; NONEON-NOSVE-NEXT:    ldr h0, [sp, #56]
691; NONEON-NOSVE-NEXT:    fcvt s0, h0
692; NONEON-NOSVE-NEXT:    fcvtzu x8, s0
693; NONEON-NOSVE-NEXT:    ldr h0, [sp, #62]
694; NONEON-NOSVE-NEXT:    fcvt s0, h0
695; NONEON-NOSVE-NEXT:    stp x8, x9, [sp, #160]
696; NONEON-NOSVE-NEXT:    fcvtzu x9, s0
697; NONEON-NOSVE-NEXT:    ldr h0, [sp, #60]
698; NONEON-NOSVE-NEXT:    fcvt s0, h0
699; NONEON-NOSVE-NEXT:    fcvtzu x8, s0
700; NONEON-NOSVE-NEXT:    ldr h0, [sp, #50]
701; NONEON-NOSVE-NEXT:    fcvt s0, h0
702; NONEON-NOSVE-NEXT:    stp x8, x9, [sp, #176]
703; NONEON-NOSVE-NEXT:    ldp q6, q7, [sp, #160]
704; NONEON-NOSVE-NEXT:    fcvtzu x9, s0
705; NONEON-NOSVE-NEXT:    ldr h0, [sp, #48]
706; NONEON-NOSVE-NEXT:    fcvt s0, h0
707; NONEON-NOSVE-NEXT:    fcvtzu x8, s0
708; NONEON-NOSVE-NEXT:    ldr h0, [sp, #54]
709; NONEON-NOSVE-NEXT:    fcvt s0, h0
710; NONEON-NOSVE-NEXT:    stp x8, x9, [sp, #128]
711; NONEON-NOSVE-NEXT:    fcvtzu x9, s0
712; NONEON-NOSVE-NEXT:    ldr h0, [sp, #52]
713; NONEON-NOSVE-NEXT:    fcvt s0, h0
714; NONEON-NOSVE-NEXT:    fcvtzu x8, s0
715; NONEON-NOSVE-NEXT:    ldp q0, q1, [sp, #96]
716; NONEON-NOSVE-NEXT:    stp x8, x9, [sp, #144]
717; NONEON-NOSVE-NEXT:    ldp q5, q2, [sp, #128]
718; NONEON-NOSVE-NEXT:    stp q0, q1, [x1]
719; NONEON-NOSVE-NEXT:    stp q3, q4, [x1, #32]
720; NONEON-NOSVE-NEXT:    stp q6, q7, [x1, #64]
721; NONEON-NOSVE-NEXT:    stp q5, q2, [x1, #96]
722; NONEON-NOSVE-NEXT:    add sp, sp, #192
723; NONEON-NOSVE-NEXT:    ret
724  %op1 = load <16 x half>, ptr %a
725  %res = fptoui <16 x half> %op1 to <16 x i64>
726  store <16 x i64> %res, ptr %b
727  ret void
728}
729
730;
731; FCVTZU S -> H
732;
733
734define <2 x i16> @fcvtzu_v2f32_v2i16(<2 x float> %op1) {
735; CHECK-LABEL: fcvtzu_v2f32_v2i16:
736; CHECK:       // %bb.0:
737; CHECK-NEXT:    ptrue p0.s, vl2
738; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
739; CHECK-NEXT:    fcvtzs z0.s, p0/m, z0.s
740; CHECK-NEXT:    // kill: def $d0 killed $d0 killed $z0
741; CHECK-NEXT:    ret
742;
743; NONEON-NOSVE-LABEL: fcvtzu_v2f32_v2i16:
744; NONEON-NOSVE:       // %bb.0:
745; NONEON-NOSVE-NEXT:    str d0, [sp, #-16]!
746; NONEON-NOSVE-NEXT:    .cfi_def_cfa_offset 16
747; NONEON-NOSVE-NEXT:    ldp s0, s1, [sp]
748; NONEON-NOSVE-NEXT:    fcvtzu w9, s1
749; NONEON-NOSVE-NEXT:    fcvtzu w8, s0
750; NONEON-NOSVE-NEXT:    stp w8, w9, [sp, #8]
751; NONEON-NOSVE-NEXT:    ldr d0, [sp, #8]
752; NONEON-NOSVE-NEXT:    add sp, sp, #16
753; NONEON-NOSVE-NEXT:    ret
754  %res = fptoui <2 x float> %op1 to <2 x i16>
755  ret <2 x i16> %res
756}
757
758define <4 x i16> @fcvtzu_v4f32_v4i16(<4 x float> %op1) {
759; CHECK-LABEL: fcvtzu_v4f32_v4i16:
760; CHECK:       // %bb.0:
761; CHECK-NEXT:    ptrue p0.s, vl4
762; CHECK-NEXT:    // kill: def $q0 killed $q0 def $z0
763; CHECK-NEXT:    fcvtzu z0.s, p0/m, z0.s
764; CHECK-NEXT:    uzp1 z0.h, z0.h, z0.h
765; CHECK-NEXT:    // kill: def $d0 killed $d0 killed $z0
766; CHECK-NEXT:    ret
767;
768; NONEON-NOSVE-LABEL: fcvtzu_v4f32_v4i16:
769; NONEON-NOSVE:       // %bb.0:
770; NONEON-NOSVE-NEXT:    str q0, [sp, #-32]!
771; NONEON-NOSVE-NEXT:    .cfi_def_cfa_offset 32
772; NONEON-NOSVE-NEXT:    ldp s0, s1, [sp, #8]
773; NONEON-NOSVE-NEXT:    fcvtzs w8, s1
774; NONEON-NOSVE-NEXT:    strh w8, [sp, #30]
775; NONEON-NOSVE-NEXT:    fcvtzs w8, s0
776; NONEON-NOSVE-NEXT:    ldp s0, s1, [sp]
777; NONEON-NOSVE-NEXT:    strh w8, [sp, #28]
778; NONEON-NOSVE-NEXT:    fcvtzs w8, s1
779; NONEON-NOSVE-NEXT:    strh w8, [sp, #26]
780; NONEON-NOSVE-NEXT:    fcvtzs w8, s0
781; NONEON-NOSVE-NEXT:    strh w8, [sp, #24]
782; NONEON-NOSVE-NEXT:    ldr d0, [sp, #24]
783; NONEON-NOSVE-NEXT:    add sp, sp, #32
784; NONEON-NOSVE-NEXT:    ret
785  %res = fptoui <4 x float> %op1 to <4 x i16>
786  ret <4 x i16> %res
787}
788
789define <8 x i16> @fcvtzu_v8f32_v8i16(ptr %a) {
790; CHECK-LABEL: fcvtzu_v8f32_v8i16:
791; CHECK:       // %bb.0:
792; CHECK-NEXT:    ldp q0, q1, [x0]
793; CHECK-NEXT:    ptrue p0.s, vl4
794; CHECK-NEXT:    fcvtzu z1.s, p0/m, z1.s
795; CHECK-NEXT:    fcvtzu z0.s, p0/m, z0.s
796; CHECK-NEXT:    ptrue p0.h, vl4
797; CHECK-NEXT:    uzp1 z1.h, z1.h, z1.h
798; CHECK-NEXT:    uzp1 z0.h, z0.h, z0.h
799; CHECK-NEXT:    splice z0.h, p0, z0.h, z1.h
800; CHECK-NEXT:    // kill: def $q0 killed $q0 killed $z0
801; CHECK-NEXT:    ret
802;
803; NONEON-NOSVE-LABEL: fcvtzu_v8f32_v8i16:
804; NONEON-NOSVE:       // %bb.0:
805; NONEON-NOSVE-NEXT:    ldp q1, q0, [x0]
806; NONEON-NOSVE-NEXT:    stp q1, q0, [sp, #-48]!
807; NONEON-NOSVE-NEXT:    .cfi_def_cfa_offset 48
808; NONEON-NOSVE-NEXT:    ldp s0, s1, [sp, #24]
809; NONEON-NOSVE-NEXT:    fcvtzs w8, s1
810; NONEON-NOSVE-NEXT:    strh w8, [sp, #46]
811; NONEON-NOSVE-NEXT:    fcvtzs w8, s0
812; NONEON-NOSVE-NEXT:    ldp s0, s1, [sp, #16]
813; NONEON-NOSVE-NEXT:    strh w8, [sp, #44]
814; NONEON-NOSVE-NEXT:    fcvtzs w8, s1
815; NONEON-NOSVE-NEXT:    strh w8, [sp, #42]
816; NONEON-NOSVE-NEXT:    fcvtzs w8, s0
817; NONEON-NOSVE-NEXT:    ldp s0, s1, [sp, #8]
818; NONEON-NOSVE-NEXT:    strh w8, [sp, #40]
819; NONEON-NOSVE-NEXT:    fcvtzs w8, s1
820; NONEON-NOSVE-NEXT:    strh w8, [sp, #38]
821; NONEON-NOSVE-NEXT:    fcvtzs w8, s0
822; NONEON-NOSVE-NEXT:    ldp s0, s1, [sp]
823; NONEON-NOSVE-NEXT:    strh w8, [sp, #36]
824; NONEON-NOSVE-NEXT:    fcvtzs w8, s1
825; NONEON-NOSVE-NEXT:    strh w8, [sp, #34]
826; NONEON-NOSVE-NEXT:    fcvtzs w8, s0
827; NONEON-NOSVE-NEXT:    strh w8, [sp, #32]
828; NONEON-NOSVE-NEXT:    ldr q0, [sp, #32]
829; NONEON-NOSVE-NEXT:    add sp, sp, #48
830; NONEON-NOSVE-NEXT:    ret
831  %op1 = load <8 x float>, ptr %a
832  %res = fptoui <8 x float> %op1 to <8 x i16>
833  ret <8 x i16> %res
834}
835
836define void @fcvtzu_v16f32_v16i16(ptr %a, ptr %b) {
837; CHECK-LABEL: fcvtzu_v16f32_v16i16:
838; CHECK:       // %bb.0:
839; CHECK-NEXT:    ldp q0, q1, [x0, #32]
840; CHECK-NEXT:    ptrue p0.s, vl4
841; CHECK-NEXT:    ldp q2, q3, [x0]
842; CHECK-NEXT:    fcvtzu z1.s, p0/m, z1.s
843; CHECK-NEXT:    fcvtzu z0.s, p0/m, z0.s
844; CHECK-NEXT:    fcvtzu z3.s, p0/m, z3.s
845; CHECK-NEXT:    fcvtzu z2.s, p0/m, z2.s
846; CHECK-NEXT:    ptrue p0.h, vl4
847; CHECK-NEXT:    uzp1 z1.h, z1.h, z1.h
848; CHECK-NEXT:    uzp1 z0.h, z0.h, z0.h
849; CHECK-NEXT:    uzp1 z3.h, z3.h, z3.h
850; CHECK-NEXT:    uzp1 z2.h, z2.h, z2.h
851; CHECK-NEXT:    splice z0.h, p0, z0.h, z1.h
852; CHECK-NEXT:    splice z2.h, p0, z2.h, z3.h
853; CHECK-NEXT:    stp q2, q0, [x1]
854; CHECK-NEXT:    ret
855;
856; NONEON-NOSVE-LABEL: fcvtzu_v16f32_v16i16:
857; NONEON-NOSVE:       // %bb.0:
858; NONEON-NOSVE-NEXT:    sub sp, sp, #96
859; NONEON-NOSVE-NEXT:    .cfi_def_cfa_offset 96
860; NONEON-NOSVE-NEXT:    ldp q1, q0, [x0]
861; NONEON-NOSVE-NEXT:    ldp q2, q3, [x0, #32]
862; NONEON-NOSVE-NEXT:    str q1, [sp]
863; NONEON-NOSVE-NEXT:    stp q3, q0, [sp, #16]
864; NONEON-NOSVE-NEXT:    ldp s0, s1, [sp, #40]
865; NONEON-NOSVE-NEXT:    str q2, [sp, #48]
866; NONEON-NOSVE-NEXT:    fcvtzs w8, s1
867; NONEON-NOSVE-NEXT:    strh w8, [sp, #78]
868; NONEON-NOSVE-NEXT:    fcvtzs w8, s0
869; NONEON-NOSVE-NEXT:    ldp s0, s1, [sp, #32]
870; NONEON-NOSVE-NEXT:    strh w8, [sp, #76]
871; NONEON-NOSVE-NEXT:    fcvtzs w8, s1
872; NONEON-NOSVE-NEXT:    strh w8, [sp, #74]
873; NONEON-NOSVE-NEXT:    fcvtzs w8, s0
874; NONEON-NOSVE-NEXT:    ldp s0, s1, [sp, #8]
875; NONEON-NOSVE-NEXT:    strh w8, [sp, #72]
876; NONEON-NOSVE-NEXT:    fcvtzs w8, s1
877; NONEON-NOSVE-NEXT:    strh w8, [sp, #70]
878; NONEON-NOSVE-NEXT:    fcvtzs w8, s0
879; NONEON-NOSVE-NEXT:    ldp s0, s1, [sp]
880; NONEON-NOSVE-NEXT:    strh w8, [sp, #68]
881; NONEON-NOSVE-NEXT:    fcvtzs w8, s1
882; NONEON-NOSVE-NEXT:    strh w8, [sp, #66]
883; NONEON-NOSVE-NEXT:    fcvtzs w8, s0
884; NONEON-NOSVE-NEXT:    ldp s0, s1, [sp, #24]
885; NONEON-NOSVE-NEXT:    strh w8, [sp, #64]
886; NONEON-NOSVE-NEXT:    fcvtzs w8, s1
887; NONEON-NOSVE-NEXT:    strh w8, [sp, #94]
888; NONEON-NOSVE-NEXT:    fcvtzs w8, s0
889; NONEON-NOSVE-NEXT:    ldp s0, s1, [sp, #16]
890; NONEON-NOSVE-NEXT:    strh w8, [sp, #92]
891; NONEON-NOSVE-NEXT:    fcvtzs w8, s1
892; NONEON-NOSVE-NEXT:    strh w8, [sp, #90]
893; NONEON-NOSVE-NEXT:    fcvtzs w8, s0
894; NONEON-NOSVE-NEXT:    ldp s0, s1, [sp, #56]
895; NONEON-NOSVE-NEXT:    strh w8, [sp, #88]
896; NONEON-NOSVE-NEXT:    fcvtzs w8, s1
897; NONEON-NOSVE-NEXT:    strh w8, [sp, #86]
898; NONEON-NOSVE-NEXT:    fcvtzs w8, s0
899; NONEON-NOSVE-NEXT:    ldp s0, s1, [sp, #48]
900; NONEON-NOSVE-NEXT:    strh w8, [sp, #84]
901; NONEON-NOSVE-NEXT:    fcvtzs w8, s1
902; NONEON-NOSVE-NEXT:    strh w8, [sp, #82]
903; NONEON-NOSVE-NEXT:    fcvtzs w8, s0
904; NONEON-NOSVE-NEXT:    strh w8, [sp, #80]
905; NONEON-NOSVE-NEXT:    ldp q1, q0, [sp, #64]
906; NONEON-NOSVE-NEXT:    stp q1, q0, [x1]
907; NONEON-NOSVE-NEXT:    add sp, sp, #96
908; NONEON-NOSVE-NEXT:    ret
909  %op1 = load <16 x float>, ptr %a
910  %res = fptoui <16 x float> %op1 to <16 x i16>
911  store <16 x i16> %res, ptr %b
912  ret void
913}
914
915;
916; FCVTZU S -> S
917;
918
919define <2 x i32> @fcvtzu_v2f32_v2i32(<2 x float> %op1) {
920; CHECK-LABEL: fcvtzu_v2f32_v2i32:
921; CHECK:       // %bb.0:
922; CHECK-NEXT:    ptrue p0.s, vl2
923; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
924; CHECK-NEXT:    fcvtzu z0.s, p0/m, z0.s
925; CHECK-NEXT:    // kill: def $d0 killed $d0 killed $z0
926; CHECK-NEXT:    ret
927;
928; NONEON-NOSVE-LABEL: fcvtzu_v2f32_v2i32:
929; NONEON-NOSVE:       // %bb.0:
930; NONEON-NOSVE-NEXT:    str d0, [sp, #-16]!
931; NONEON-NOSVE-NEXT:    .cfi_def_cfa_offset 16
932; NONEON-NOSVE-NEXT:    ldp s0, s1, [sp]
933; NONEON-NOSVE-NEXT:    fcvtzu w9, s1
934; NONEON-NOSVE-NEXT:    fcvtzu w8, s0
935; NONEON-NOSVE-NEXT:    stp w8, w9, [sp, #8]
936; NONEON-NOSVE-NEXT:    ldr d0, [sp, #8]
937; NONEON-NOSVE-NEXT:    add sp, sp, #16
938; NONEON-NOSVE-NEXT:    ret
939  %res = fptoui <2 x float> %op1 to <2 x i32>
940  ret <2 x i32> %res
941}
942
943define <4 x i32> @fcvtzu_v4f32_v4i32(<4 x float> %op1) {
944; CHECK-LABEL: fcvtzu_v4f32_v4i32:
945; CHECK:       // %bb.0:
946; CHECK-NEXT:    ptrue p0.s, vl4
947; CHECK-NEXT:    // kill: def $q0 killed $q0 def $z0
948; CHECK-NEXT:    fcvtzu z0.s, p0/m, z0.s
949; CHECK-NEXT:    // kill: def $q0 killed $q0 killed $z0
950; CHECK-NEXT:    ret
951;
952; NONEON-NOSVE-LABEL: fcvtzu_v4f32_v4i32:
953; NONEON-NOSVE:       // %bb.0:
954; NONEON-NOSVE-NEXT:    str q0, [sp, #-32]!
955; NONEON-NOSVE-NEXT:    .cfi_def_cfa_offset 32
956; NONEON-NOSVE-NEXT:    ldp s0, s1, [sp, #8]
957; NONEON-NOSVE-NEXT:    fcvtzu w9, s1
958; NONEON-NOSVE-NEXT:    fcvtzu w8, s0
959; NONEON-NOSVE-NEXT:    ldp s0, s1, [sp]
960; NONEON-NOSVE-NEXT:    stp w8, w9, [sp, #24]
961; NONEON-NOSVE-NEXT:    fcvtzu w9, s1
962; NONEON-NOSVE-NEXT:    fcvtzu w8, s0
963; NONEON-NOSVE-NEXT:    stp w8, w9, [sp, #16]
964; NONEON-NOSVE-NEXT:    ldr q0, [sp, #16]
965; NONEON-NOSVE-NEXT:    add sp, sp, #32
966; NONEON-NOSVE-NEXT:    ret
967  %res = fptoui <4 x float> %op1 to <4 x i32>
968  ret <4 x i32> %res
969}
970
971define void @fcvtzu_v8f32_v8i32(ptr %a, ptr %b) {
972; CHECK-LABEL: fcvtzu_v8f32_v8i32:
973; CHECK:       // %bb.0:
974; CHECK-NEXT:    ldp q0, q1, [x0]
975; CHECK-NEXT:    ptrue p0.s, vl4
976; CHECK-NEXT:    fcvtzu z0.s, p0/m, z0.s
977; CHECK-NEXT:    fcvtzu z1.s, p0/m, z1.s
978; CHECK-NEXT:    stp q0, q1, [x1]
979; CHECK-NEXT:    ret
980;
981; NONEON-NOSVE-LABEL: fcvtzu_v8f32_v8i32:
982; NONEON-NOSVE:       // %bb.0:
983; NONEON-NOSVE-NEXT:    ldp q1, q0, [x0]
984; NONEON-NOSVE-NEXT:    stp q1, q0, [sp, #-64]!
985; NONEON-NOSVE-NEXT:    .cfi_def_cfa_offset 64
986; NONEON-NOSVE-NEXT:    ldp s0, s1, [sp, #24]
987; NONEON-NOSVE-NEXT:    fcvtzu w9, s1
988; NONEON-NOSVE-NEXT:    fcvtzu w8, s0
989; NONEON-NOSVE-NEXT:    ldp s0, s1, [sp, #16]
990; NONEON-NOSVE-NEXT:    stp w8, w9, [sp, #56]
991; NONEON-NOSVE-NEXT:    fcvtzu w9, s1
992; NONEON-NOSVE-NEXT:    fcvtzu w8, s0
993; NONEON-NOSVE-NEXT:    ldp s0, s1, [sp, #8]
994; NONEON-NOSVE-NEXT:    stp w8, w9, [sp, #48]
995; NONEON-NOSVE-NEXT:    fcvtzu w9, s1
996; NONEON-NOSVE-NEXT:    fcvtzu w8, s0
997; NONEON-NOSVE-NEXT:    ldp s0, s1, [sp]
998; NONEON-NOSVE-NEXT:    stp w8, w9, [sp, #40]
999; NONEON-NOSVE-NEXT:    fcvtzu w9, s1
1000; NONEON-NOSVE-NEXT:    fcvtzu w8, s0
1001; NONEON-NOSVE-NEXT:    stp w8, w9, [sp, #32]
1002; NONEON-NOSVE-NEXT:    ldp q0, q1, [sp, #32]
1003; NONEON-NOSVE-NEXT:    stp q0, q1, [x1]
1004; NONEON-NOSVE-NEXT:    add sp, sp, #64
1005; NONEON-NOSVE-NEXT:    ret
1006  %op1 = load <8 x float>, ptr %a
1007  %res = fptoui <8 x float> %op1 to <8 x i32>
1008  store <8 x i32> %res, ptr %b
1009  ret void
1010}
1011
1012;
1013; FCVTZU S -> D
1014;
1015
1016define <1 x i64> @fcvtzu_v1f32_v1i64(<1 x float> %op1) {
1017; CHECK-LABEL: fcvtzu_v1f32_v1i64:
1018; CHECK:       // %bb.0:
1019; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
1020; CHECK-NEXT:    ptrue p0.d, vl2
1021; CHECK-NEXT:    uunpklo z0.d, z0.s
1022; CHECK-NEXT:    fcvtzu z0.d, p0/m, z0.s
1023; CHECK-NEXT:    // kill: def $d0 killed $d0 killed $z0
1024; CHECK-NEXT:    ret
1025;
1026; NONEON-NOSVE-LABEL: fcvtzu_v1f32_v1i64:
1027; NONEON-NOSVE:       // %bb.0:
1028; NONEON-NOSVE-NEXT:    sub sp, sp, #16
1029; NONEON-NOSVE-NEXT:    .cfi_def_cfa_offset 16
1030; NONEON-NOSVE-NEXT:    str d0, [sp, #8]
1031; NONEON-NOSVE-NEXT:    ldr s0, [sp, #8]
1032; NONEON-NOSVE-NEXT:    fcvtzu x8, s0
1033; NONEON-NOSVE-NEXT:    fmov d0, x8
1034; NONEON-NOSVE-NEXT:    add sp, sp, #16
1035; NONEON-NOSVE-NEXT:    ret
1036  %res = fptoui <1 x float> %op1 to <1 x i64>
1037  ret <1 x i64> %res
1038}
1039
1040define <2 x i64> @fcvtzu_v2f32_v2i64(<2 x float> %op1) {
1041; CHECK-LABEL: fcvtzu_v2f32_v2i64:
1042; CHECK:       // %bb.0:
1043; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
1044; CHECK-NEXT:    ptrue p0.d, vl2
1045; CHECK-NEXT:    uunpklo z0.d, z0.s
1046; CHECK-NEXT:    fcvtzu z0.d, p0/m, z0.s
1047; CHECK-NEXT:    // kill: def $q0 killed $q0 killed $z0
1048; CHECK-NEXT:    ret
1049;
1050; NONEON-NOSVE-LABEL: fcvtzu_v2f32_v2i64:
1051; NONEON-NOSVE:       // %bb.0:
1052; NONEON-NOSVE-NEXT:    sub sp, sp, #32
1053; NONEON-NOSVE-NEXT:    .cfi_def_cfa_offset 32
1054; NONEON-NOSVE-NEXT:    str d0, [sp, #8]
1055; NONEON-NOSVE-NEXT:    ldp s0, s1, [sp, #8]
1056; NONEON-NOSVE-NEXT:    fcvtzu x9, s1
1057; NONEON-NOSVE-NEXT:    fcvtzu x8, s0
1058; NONEON-NOSVE-NEXT:    stp x8, x9, [sp, #16]
1059; NONEON-NOSVE-NEXT:    ldr q0, [sp, #16]
1060; NONEON-NOSVE-NEXT:    add sp, sp, #32
1061; NONEON-NOSVE-NEXT:    ret
1062  %res = fptoui <2 x float> %op1 to <2 x i64>
1063  ret <2 x i64> %res
1064}
1065
1066define void @fcvtzu_v4f32_v4i64(ptr %a, ptr %b) {
1067; CHECK-LABEL: fcvtzu_v4f32_v4i64:
1068; CHECK:       // %bb.0:
1069; CHECK-NEXT:    ldr q0, [x0]
1070; CHECK-NEXT:    ptrue p0.d, vl2
1071; CHECK-NEXT:    uunpklo z1.d, z0.s
1072; CHECK-NEXT:    ext z0.b, z0.b, z0.b, #8
1073; CHECK-NEXT:    uunpklo z0.d, z0.s
1074; CHECK-NEXT:    fcvtzu z1.d, p0/m, z1.s
1075; CHECK-NEXT:    fcvtzu z0.d, p0/m, z0.s
1076; CHECK-NEXT:    stp q1, q0, [x1]
1077; CHECK-NEXT:    ret
1078;
1079; NONEON-NOSVE-LABEL: fcvtzu_v4f32_v4i64:
1080; NONEON-NOSVE:       // %bb.0:
1081; NONEON-NOSVE-NEXT:    ldr q0, [x0]
1082; NONEON-NOSVE-NEXT:    str q0, [sp, #-64]!
1083; NONEON-NOSVE-NEXT:    .cfi_def_cfa_offset 64
1084; NONEON-NOSVE-NEXT:    ldp d1, d0, [sp]
1085; NONEON-NOSVE-NEXT:    stp d0, d1, [sp, #16]
1086; NONEON-NOSVE-NEXT:    ldp s0, s1, [sp, #24]
1087; NONEON-NOSVE-NEXT:    fcvtzu x9, s1
1088; NONEON-NOSVE-NEXT:    fcvtzu x8, s0
1089; NONEON-NOSVE-NEXT:    ldp s0, s1, [sp, #16]
1090; NONEON-NOSVE-NEXT:    stp x8, x9, [sp, #48]
1091; NONEON-NOSVE-NEXT:    fcvtzu x9, s1
1092; NONEON-NOSVE-NEXT:    fcvtzu x8, s0
1093; NONEON-NOSVE-NEXT:    stp x8, x9, [sp, #32]
1094; NONEON-NOSVE-NEXT:    ldp q0, q1, [sp, #32]
1095; NONEON-NOSVE-NEXT:    stp q1, q0, [x1]
1096; NONEON-NOSVE-NEXT:    add sp, sp, #64
1097; NONEON-NOSVE-NEXT:    ret
1098  %op1 = load <4 x float>, ptr %a
1099  %res = fptoui <4 x float> %op1 to <4 x i64>
1100  store <4 x i64> %res, ptr %b
1101  ret void
1102}
1103
1104define void @fcvtzu_v8f32_v8i64(ptr %a, ptr %b) {
1105; CHECK-LABEL: fcvtzu_v8f32_v8i64:
1106; CHECK:       // %bb.0:
1107; CHECK-NEXT:    ldp q1, q0, [x0]
1108; CHECK-NEXT:    ptrue p0.d, vl2
1109; CHECK-NEXT:    uunpklo z2.d, z0.s
1110; CHECK-NEXT:    ext z0.b, z0.b, z0.b, #8
1111; CHECK-NEXT:    uunpklo z3.d, z1.s
1112; CHECK-NEXT:    ext z1.b, z1.b, z1.b, #8
1113; CHECK-NEXT:    uunpklo z0.d, z0.s
1114; CHECK-NEXT:    uunpklo z1.d, z1.s
1115; CHECK-NEXT:    fcvtzu z2.d, p0/m, z2.s
1116; CHECK-NEXT:    fcvtzu z3.d, p0/m, z3.s
1117; CHECK-NEXT:    fcvtzu z0.d, p0/m, z0.s
1118; CHECK-NEXT:    fcvtzu z1.d, p0/m, z1.s
1119; CHECK-NEXT:    stp q2, q0, [x1, #32]
1120; CHECK-NEXT:    stp q3, q1, [x1]
1121; CHECK-NEXT:    ret
1122;
1123; NONEON-NOSVE-LABEL: fcvtzu_v8f32_v8i64:
1124; NONEON-NOSVE:       // %bb.0:
1125; NONEON-NOSVE-NEXT:    ldp q0, q1, [x0]
1126; NONEON-NOSVE-NEXT:    stp q0, q1, [sp, #-128]!
1127; NONEON-NOSVE-NEXT:    .cfi_def_cfa_offset 128
1128; NONEON-NOSVE-NEXT:    ldp d1, d0, [sp]
1129; NONEON-NOSVE-NEXT:    stp d0, d1, [sp, #32]
1130; NONEON-NOSVE-NEXT:    ldp d1, d0, [sp, #16]
1131; NONEON-NOSVE-NEXT:    stp d0, d1, [sp, #48]
1132; NONEON-NOSVE-NEXT:    ldp s0, s1, [sp, #40]
1133; NONEON-NOSVE-NEXT:    fcvtzu x9, s1
1134; NONEON-NOSVE-NEXT:    fcvtzu x8, s0
1135; NONEON-NOSVE-NEXT:    ldp s0, s1, [sp, #32]
1136; NONEON-NOSVE-NEXT:    stp x8, x9, [sp, #80]
1137; NONEON-NOSVE-NEXT:    fcvtzu x9, s1
1138; NONEON-NOSVE-NEXT:    fcvtzu x8, s0
1139; NONEON-NOSVE-NEXT:    ldp s0, s1, [sp, #56]
1140; NONEON-NOSVE-NEXT:    stp x8, x9, [sp, #64]
1141; NONEON-NOSVE-NEXT:    fcvtzu x9, s1
1142; NONEON-NOSVE-NEXT:    fcvtzu x8, s0
1143; NONEON-NOSVE-NEXT:    ldp s0, s1, [sp, #48]
1144; NONEON-NOSVE-NEXT:    ldp q3, q2, [sp, #64]
1145; NONEON-NOSVE-NEXT:    stp x8, x9, [sp, #112]
1146; NONEON-NOSVE-NEXT:    fcvtzu x9, s1
1147; NONEON-NOSVE-NEXT:    fcvtzu x8, s0
1148; NONEON-NOSVE-NEXT:    stp x8, x9, [sp, #96]
1149; NONEON-NOSVE-NEXT:    ldp q0, q1, [sp, #96]
1150; NONEON-NOSVE-NEXT:    stp q2, q3, [x1]
1151; NONEON-NOSVE-NEXT:    stp q1, q0, [x1, #32]
1152; NONEON-NOSVE-NEXT:    add sp, sp, #128
1153; NONEON-NOSVE-NEXT:    ret
1154  %op1 = load <8 x float>, ptr %a
1155  %res = fptoui <8 x float> %op1 to <8 x i64>
1156  store <8 x i64> %res, ptr %b
1157  ret void
1158}
1159
1160;
1161; FCVTZU D -> H
1162;
1163
1164define <1 x i16> @fcvtzu_v1f64_v1i16(<1 x double> %op1) {
1165; CHECK-LABEL: fcvtzu_v1f64_v1i16:
1166; CHECK:       // %bb.0:
1167; CHECK-NEXT:    fcvtzs w8, d0
1168; CHECK-NEXT:    mov z0.h, w8
1169; CHECK-NEXT:    // kill: def $d0 killed $d0 killed $z0
1170; CHECK-NEXT:    ret
1171;
1172; NONEON-NOSVE-LABEL: fcvtzu_v1f64_v1i16:
1173; NONEON-NOSVE:       // %bb.0:
1174; NONEON-NOSVE-NEXT:    sub sp, sp, #16
1175; NONEON-NOSVE-NEXT:    .cfi_def_cfa_offset 16
1176; NONEON-NOSVE-NEXT:    fcvtzs w8, d0
1177; NONEON-NOSVE-NEXT:    strh w8, [sp, #8]
1178; NONEON-NOSVE-NEXT:    ldr d0, [sp, #8]
1179; NONEON-NOSVE-NEXT:    add sp, sp, #16
1180; NONEON-NOSVE-NEXT:    ret
1181  %res = fptoui <1 x double> %op1 to <1 x i16>
1182  ret <1 x i16> %res
1183}
1184
1185define <2 x i16> @fcvtzu_v2f64_v2i16(<2 x double> %op1) {
1186; CHECK-LABEL: fcvtzu_v2f64_v2i16:
1187; CHECK:       // %bb.0:
1188; CHECK-NEXT:    ptrue p0.d, vl2
1189; CHECK-NEXT:    // kill: def $q0 killed $q0 def $z0
1190; CHECK-NEXT:    fcvtzs z0.d, p0/m, z0.d
1191; CHECK-NEXT:    uzp1 z0.s, z0.s, z0.s
1192; CHECK-NEXT:    // kill: def $d0 killed $d0 killed $z0
1193; CHECK-NEXT:    ret
1194;
1195; NONEON-NOSVE-LABEL: fcvtzu_v2f64_v2i16:
1196; NONEON-NOSVE:       // %bb.0:
1197; NONEON-NOSVE-NEXT:    str q0, [sp, #-32]!
1198; NONEON-NOSVE-NEXT:    .cfi_def_cfa_offset 32
1199; NONEON-NOSVE-NEXT:    ldp d0, d1, [sp]
1200; NONEON-NOSVE-NEXT:    fcvtzu w9, d1
1201; NONEON-NOSVE-NEXT:    fcvtzu w8, d0
1202; NONEON-NOSVE-NEXT:    stp w8, w9, [sp, #24]
1203; NONEON-NOSVE-NEXT:    ldr d0, [sp, #24]
1204; NONEON-NOSVE-NEXT:    add sp, sp, #32
1205; NONEON-NOSVE-NEXT:    ret
1206  %res = fptoui <2 x double> %op1 to <2 x i16>
1207  ret <2 x i16> %res
1208}
1209
1210define <4 x i16> @fcvtzu_v4f64_v4i16(ptr %a) {
1211; CHECK-LABEL: fcvtzu_v4f64_v4i16:
1212; CHECK:       // %bb.0:
1213; CHECK-NEXT:    ldp q0, q1, [x0]
1214; CHECK-NEXT:    ptrue p0.d, vl2
1215; CHECK-NEXT:    fcvtzs z1.d, p0/m, z1.d
1216; CHECK-NEXT:    fcvtzs z0.d, p0/m, z0.d
1217; CHECK-NEXT:    uzp1 z1.s, z1.s, z1.s
1218; CHECK-NEXT:    uzp1 z0.s, z0.s, z0.s
1219; CHECK-NEXT:    mov z2.s, z1.s[1]
1220; CHECK-NEXT:    mov z3.s, z0.s[1]
1221; CHECK-NEXT:    zip1 z1.h, z1.h, z2.h
1222; CHECK-NEXT:    zip1 z0.h, z0.h, z3.h
1223; CHECK-NEXT:    zip1 z0.s, z0.s, z1.s
1224; CHECK-NEXT:    // kill: def $d0 killed $d0 killed $z0
1225; CHECK-NEXT:    ret
1226;
1227; NONEON-NOSVE-LABEL: fcvtzu_v4f64_v4i16:
1228; NONEON-NOSVE:       // %bb.0:
1229; NONEON-NOSVE-NEXT:    ldp q1, q0, [x0]
1230; NONEON-NOSVE-NEXT:    stp q1, q0, [sp, #-80]!
1231; NONEON-NOSVE-NEXT:    .cfi_def_cfa_offset 80
1232; NONEON-NOSVE-NEXT:    ldp d0, d1, [sp, #16]
1233; NONEON-NOSVE-NEXT:    fcvtzu w9, d1
1234; NONEON-NOSVE-NEXT:    fcvtzu w8, d0
1235; NONEON-NOSVE-NEXT:    ldp d0, d1, [sp]
1236; NONEON-NOSVE-NEXT:    stp w8, w9, [sp, #48]
1237; NONEON-NOSVE-NEXT:    fcvtzu w9, d1
1238; NONEON-NOSVE-NEXT:    fcvtzu w8, d0
1239; NONEON-NOSVE-NEXT:    stp w8, w9, [sp, #40]
1240; NONEON-NOSVE-NEXT:    ldp d0, d1, [sp, #40]
1241; NONEON-NOSVE-NEXT:    stp d0, d1, [sp, #56]
1242; NONEON-NOSVE-NEXT:    ldp w8, w9, [sp, #64]
1243; NONEON-NOSVE-NEXT:    strh w9, [sp, #78]
1244; NONEON-NOSVE-NEXT:    strh w8, [sp, #76]
1245; NONEON-NOSVE-NEXT:    ldp w8, w9, [sp, #56]
1246; NONEON-NOSVE-NEXT:    strh w9, [sp, #74]
1247; NONEON-NOSVE-NEXT:    strh w8, [sp, #72]
1248; NONEON-NOSVE-NEXT:    ldr d0, [sp, #72]
1249; NONEON-NOSVE-NEXT:    add sp, sp, #80
1250; NONEON-NOSVE-NEXT:    ret
1251  %op1 = load <4 x double>, ptr %a
1252  %res = fptoui <4 x double> %op1 to <4 x i16>
1253  ret <4 x i16> %res
1254}
1255
1256define <8 x i16> @fcvtzu_v8f64_v8i16(ptr %a) {
1257; CHECK-LABEL: fcvtzu_v8f64_v8i16:
1258; CHECK:       // %bb.0:
1259; CHECK-NEXT:    ldp q1, q0, [x0, #32]
1260; CHECK-NEXT:    ptrue p0.d, vl2
1261; CHECK-NEXT:    ldp q2, q3, [x0]
1262; CHECK-NEXT:    fcvtzs z0.d, p0/m, z0.d
1263; CHECK-NEXT:    fcvtzs z1.d, p0/m, z1.d
1264; CHECK-NEXT:    fcvtzs z3.d, p0/m, z3.d
1265; CHECK-NEXT:    fcvtzs z2.d, p0/m, z2.d
1266; CHECK-NEXT:    uzp1 z0.s, z0.s, z0.s
1267; CHECK-NEXT:    uzp1 z1.s, z1.s, z1.s
1268; CHECK-NEXT:    uzp1 z3.s, z3.s, z3.s
1269; CHECK-NEXT:    uzp1 z2.s, z2.s, z2.s
1270; CHECK-NEXT:    mov z4.s, z0.s[1]
1271; CHECK-NEXT:    mov z5.s, z1.s[1]
1272; CHECK-NEXT:    mov z6.s, z3.s[1]
1273; CHECK-NEXT:    mov z7.s, z2.s[1]
1274; CHECK-NEXT:    zip1 z0.h, z0.h, z4.h
1275; CHECK-NEXT:    zip1 z1.h, z1.h, z5.h
1276; CHECK-NEXT:    zip1 z3.h, z3.h, z6.h
1277; CHECK-NEXT:    zip1 z2.h, z2.h, z7.h
1278; CHECK-NEXT:    zip1 z0.s, z1.s, z0.s
1279; CHECK-NEXT:    zip1 z1.s, z2.s, z3.s
1280; CHECK-NEXT:    zip1 z0.d, z1.d, z0.d
1281; CHECK-NEXT:    // kill: def $q0 killed $q0 killed $z0
1282; CHECK-NEXT:    ret
1283;
1284; NONEON-NOSVE-LABEL: fcvtzu_v8f64_v8i16:
1285; NONEON-NOSVE:       // %bb.0:
1286; NONEON-NOSVE-NEXT:    sub sp, sp, #144
1287; NONEON-NOSVE-NEXT:    .cfi_def_cfa_offset 144
1288; NONEON-NOSVE-NEXT:    ldp q1, q0, [x0, #32]
1289; NONEON-NOSVE-NEXT:    ldp q2, q3, [x0]
1290; NONEON-NOSVE-NEXT:    str q1, [sp, #48]
1291; NONEON-NOSVE-NEXT:    stp q0, q3, [sp, #16]
1292; NONEON-NOSVE-NEXT:    ldp d0, d1, [sp, #16]
1293; NONEON-NOSVE-NEXT:    str q2, [sp]
1294; NONEON-NOSVE-NEXT:    fcvtzu w9, d1
1295; NONEON-NOSVE-NEXT:    fcvtzu w8, d0
1296; NONEON-NOSVE-NEXT:    ldp d0, d1, [sp, #48]
1297; NONEON-NOSVE-NEXT:    stp w8, w9, [sp, #72]
1298; NONEON-NOSVE-NEXT:    fcvtzu w9, d1
1299; NONEON-NOSVE-NEXT:    fcvtzu w8, d0
1300; NONEON-NOSVE-NEXT:    ldp d0, d1, [sp, #32]
1301; NONEON-NOSVE-NEXT:    stp w8, w9, [sp, #88]
1302; NONEON-NOSVE-NEXT:    fcvtzu w9, d1
1303; NONEON-NOSVE-NEXT:    fcvtzu w8, d0
1304; NONEON-NOSVE-NEXT:    ldp d0, d1, [sp]
1305; NONEON-NOSVE-NEXT:    stp w8, w9, [sp, #80]
1306; NONEON-NOSVE-NEXT:    fcvtzu w9, d1
1307; NONEON-NOSVE-NEXT:    fcvtzu w8, d0
1308; NONEON-NOSVE-NEXT:    ldp d0, d2, [sp, #80]
1309; NONEON-NOSVE-NEXT:    ldr d1, [sp, #72]
1310; NONEON-NOSVE-NEXT:    stp d1, d0, [sp, #104]
1311; NONEON-NOSVE-NEXT:    stp w8, w9, [sp, #64]
1312; NONEON-NOSVE-NEXT:    ldp w8, w9, [sp, #104]
1313; NONEON-NOSVE-NEXT:    str d2, [sp, #120]
1314; NONEON-NOSVE-NEXT:    ldr d0, [sp, #64]
1315; NONEON-NOSVE-NEXT:    strh w9, [sp, #142]
1316; NONEON-NOSVE-NEXT:    strh w8, [sp, #140]
1317; NONEON-NOSVE-NEXT:    ldp w8, w9, [sp, #120]
1318; NONEON-NOSVE-NEXT:    str d0, [sp, #96]
1319; NONEON-NOSVE-NEXT:    strh w9, [sp, #138]
1320; NONEON-NOSVE-NEXT:    strh w8, [sp, #136]
1321; NONEON-NOSVE-NEXT:    ldp w8, w9, [sp, #112]
1322; NONEON-NOSVE-NEXT:    strh w9, [sp, #134]
1323; NONEON-NOSVE-NEXT:    strh w8, [sp, #132]
1324; NONEON-NOSVE-NEXT:    ldp w8, w9, [sp, #96]
1325; NONEON-NOSVE-NEXT:    strh w9, [sp, #130]
1326; NONEON-NOSVE-NEXT:    strh w8, [sp, #128]
1327; NONEON-NOSVE-NEXT:    ldr q0, [sp, #128]
1328; NONEON-NOSVE-NEXT:    add sp, sp, #144
1329; NONEON-NOSVE-NEXT:    ret
1330  %op1 = load <8 x double>, ptr %a
1331  %res = fptoui <8 x double> %op1 to <8 x i16>
1332  ret <8 x i16> %res
1333}
1334
1335define void @fcvtzu_v16f64_v16i16(ptr %a, ptr %b) {
1336; CHECK-LABEL: fcvtzu_v16f64_v16i16:
1337; CHECK:       // %bb.0:
1338; CHECK-NEXT:    ldp q5, q6, [x0, #96]
1339; CHECK-NEXT:    ptrue p0.d, vl2
1340; CHECK-NEXT:    ldp q0, q4, [x0, #32]
1341; CHECK-NEXT:    ldp q2, q7, [x0, #64]
1342; CHECK-NEXT:    ldp q1, q3, [x0]
1343; CHECK-NEXT:    fcvtzs z6.d, p0/m, z6.d
1344; CHECK-NEXT:    fcvtzs z4.d, p0/m, z4.d
1345; CHECK-NEXT:    fcvtzs z5.d, p0/m, z5.d
1346; CHECK-NEXT:    fcvtzs z0.d, p0/m, z0.d
1347; CHECK-NEXT:    fcvtzs z7.d, p0/m, z7.d
1348; CHECK-NEXT:    fcvtzs z2.d, p0/m, z2.d
1349; CHECK-NEXT:    fcvtzs z3.d, p0/m, z3.d
1350; CHECK-NEXT:    fcvtzs z1.d, p0/m, z1.d
1351; CHECK-NEXT:    uzp1 z6.s, z6.s, z6.s
1352; CHECK-NEXT:    uzp1 z4.s, z4.s, z4.s
1353; CHECK-NEXT:    uzp1 z5.s, z5.s, z5.s
1354; CHECK-NEXT:    uzp1 z0.s, z0.s, z0.s
1355; CHECK-NEXT:    uzp1 z7.s, z7.s, z7.s
1356; CHECK-NEXT:    uzp1 z2.s, z2.s, z2.s
1357; CHECK-NEXT:    uzp1 z3.s, z3.s, z3.s
1358; CHECK-NEXT:    uzp1 z1.s, z1.s, z1.s
1359; CHECK-NEXT:    mov z17.s, z6.s[1]
1360; CHECK-NEXT:    mov z16.s, z4.s[1]
1361; CHECK-NEXT:    mov z18.s, z5.s[1]
1362; CHECK-NEXT:    mov z21.s, z0.s[1]
1363; CHECK-NEXT:    mov z19.s, z7.s[1]
1364; CHECK-NEXT:    mov z20.s, z2.s[1]
1365; CHECK-NEXT:    mov z22.s, z3.s[1]
1366; CHECK-NEXT:    mov z23.s, z1.s[1]
1367; CHECK-NEXT:    zip1 z6.h, z6.h, z17.h
1368; CHECK-NEXT:    zip1 z4.h, z4.h, z16.h
1369; CHECK-NEXT:    zip1 z5.h, z5.h, z18.h
1370; CHECK-NEXT:    zip1 z0.h, z0.h, z21.h
1371; CHECK-NEXT:    zip1 z7.h, z7.h, z19.h
1372; CHECK-NEXT:    zip1 z2.h, z2.h, z20.h
1373; CHECK-NEXT:    zip1 z3.h, z3.h, z22.h
1374; CHECK-NEXT:    zip1 z1.h, z1.h, z23.h
1375; CHECK-NEXT:    zip1 z5.s, z5.s, z6.s
1376; CHECK-NEXT:    zip1 z0.s, z0.s, z4.s
1377; CHECK-NEXT:    zip1 z2.s, z2.s, z7.s
1378; CHECK-NEXT:    zip1 z1.s, z1.s, z3.s
1379; CHECK-NEXT:    zip1 z2.d, z2.d, z5.d
1380; CHECK-NEXT:    zip1 z0.d, z1.d, z0.d
1381; CHECK-NEXT:    stp q0, q2, [x1]
1382; CHECK-NEXT:    ret
1383;
1384; NONEON-NOSVE-LABEL: fcvtzu_v16f64_v16i16:
1385; NONEON-NOSVE:       // %bb.0:
1386; NONEON-NOSVE-NEXT:    sub sp, sp, #304
1387; NONEON-NOSVE-NEXT:    str x29, [sp, #288] // 8-byte Folded Spill
1388; NONEON-NOSVE-NEXT:    .cfi_def_cfa_offset 304
1389; NONEON-NOSVE-NEXT:    .cfi_offset w29, -16
1390; NONEON-NOSVE-NEXT:    ldp q0, q1, [x0, #32]
1391; NONEON-NOSVE-NEXT:    ldr x29, [sp, #288] // 8-byte Folded Reload
1392; NONEON-NOSVE-NEXT:    ldp q6, q7, [x0]
1393; NONEON-NOSVE-NEXT:    ldp q2, q3, [x0, #64]
1394; NONEON-NOSVE-NEXT:    ldp q4, q5, [x0, #96]
1395; NONEON-NOSVE-NEXT:    stp q1, q7, [sp, #64]
1396; NONEON-NOSVE-NEXT:    stp q0, q2, [sp, #96]
1397; NONEON-NOSVE-NEXT:    ldp d0, d1, [sp, #64]
1398; NONEON-NOSVE-NEXT:    stp q6, q4, [sp]
1399; NONEON-NOSVE-NEXT:    stp q5, q3, [sp, #32]
1400; NONEON-NOSVE-NEXT:    fcvtzu w9, d1
1401; NONEON-NOSVE-NEXT:    fcvtzu w8, d0
1402; NONEON-NOSVE-NEXT:    ldp d0, d1, [sp, #96]
1403; NONEON-NOSVE-NEXT:    stp w8, w9, [sp, #168]
1404; NONEON-NOSVE-NEXT:    fcvtzu w9, d1
1405; NONEON-NOSVE-NEXT:    fcvtzu w8, d0
1406; NONEON-NOSVE-NEXT:    ldp d0, d1, [sp, #80]
1407; NONEON-NOSVE-NEXT:    stp w8, w9, [sp, #184]
1408; NONEON-NOSVE-NEXT:    fcvtzu w9, d1
1409; NONEON-NOSVE-NEXT:    fcvtzu w8, d0
1410; NONEON-NOSVE-NEXT:    ldp d0, d1, [sp]
1411; NONEON-NOSVE-NEXT:    stp w8, w9, [sp, #176]
1412; NONEON-NOSVE-NEXT:    fcvtzu w9, d1
1413; NONEON-NOSVE-NEXT:    fcvtzu w8, d0
1414; NONEON-NOSVE-NEXT:    ldp d0, d1, [sp, #32]
1415; NONEON-NOSVE-NEXT:    stp w8, w9, [sp, #136]
1416; NONEON-NOSVE-NEXT:    fcvtzu w9, d1
1417; NONEON-NOSVE-NEXT:    fcvtzu w8, d0
1418; NONEON-NOSVE-NEXT:    ldp d0, d1, [sp, #16]
1419; NONEON-NOSVE-NEXT:    stp w8, w9, [sp, #152]
1420; NONEON-NOSVE-NEXT:    fcvtzu w9, d1
1421; NONEON-NOSVE-NEXT:    fcvtzu w8, d0
1422; NONEON-NOSVE-NEXT:    ldp d0, d1, [sp, #48]
1423; NONEON-NOSVE-NEXT:    stp w8, w9, [sp, #144]
1424; NONEON-NOSVE-NEXT:    fcvtzu w9, d1
1425; NONEON-NOSVE-NEXT:    fcvtzu w8, d0
1426; NONEON-NOSVE-NEXT:    ldp d0, d1, [sp, #112]
1427; NONEON-NOSVE-NEXT:    stp w8, w9, [sp, #160]
1428; NONEON-NOSVE-NEXT:    fcvtzu w9, d1
1429; NONEON-NOSVE-NEXT:    fcvtzu w8, d0
1430; NONEON-NOSVE-NEXT:    ldp d0, d2, [sp, #176]
1431; NONEON-NOSVE-NEXT:    ldr d1, [sp, #168]
1432; NONEON-NOSVE-NEXT:    stp d1, d0, [sp, #232]
1433; NONEON-NOSVE-NEXT:    ldr d1, [sp, #136]
1434; NONEON-NOSVE-NEXT:    stp w8, w9, [sp, #192]
1435; NONEON-NOSVE-NEXT:    ldp w8, w9, [sp, #232]
1436; NONEON-NOSVE-NEXT:    str d2, [sp, #248]
1437; NONEON-NOSVE-NEXT:    ldp d0, d2, [sp, #144]
1438; NONEON-NOSVE-NEXT:    strh w9, [sp, #270]
1439; NONEON-NOSVE-NEXT:    strh w8, [sp, #268]
1440; NONEON-NOSVE-NEXT:    ldp w8, w9, [sp, #248]
1441; NONEON-NOSVE-NEXT:    stp d1, d0, [sp, #200]
1442; NONEON-NOSVE-NEXT:    ldr d0, [sp, #160]
1443; NONEON-NOSVE-NEXT:    strh w9, [sp, #266]
1444; NONEON-NOSVE-NEXT:    strh w8, [sp, #264]
1445; NONEON-NOSVE-NEXT:    ldp w8, w9, [sp, #240]
1446; NONEON-NOSVE-NEXT:    stp d2, d0, [sp, #216]
1447; NONEON-NOSVE-NEXT:    ldr d0, [sp, #192]
1448; NONEON-NOSVE-NEXT:    strh w9, [sp, #262]
1449; NONEON-NOSVE-NEXT:    strh w8, [sp, #260]
1450; NONEON-NOSVE-NEXT:    ldp w8, w9, [sp, #200]
1451; NONEON-NOSVE-NEXT:    str d0, [sp, #296]
1452; NONEON-NOSVE-NEXT:    strh w9, [sp, #258]
1453; NONEON-NOSVE-NEXT:    strh w8, [sp, #256]
1454; NONEON-NOSVE-NEXT:    ldp w8, w9, [sp, #216]
1455; NONEON-NOSVE-NEXT:    strh w9, [sp, #286]
1456; NONEON-NOSVE-NEXT:    strh w8, [sp, #284]
1457; NONEON-NOSVE-NEXT:    ldp w8, w9, [sp, #208]
1458; NONEON-NOSVE-NEXT:    strh w9, [sp, #282]
1459; NONEON-NOSVE-NEXT:    strh w8, [sp, #280]
1460; NONEON-NOSVE-NEXT:    ldp w8, w9, [sp, #224]
1461; NONEON-NOSVE-NEXT:    strh w8, [sp, #276]
1462; NONEON-NOSVE-NEXT:    ldr w8, [sp, #300]
1463; NONEON-NOSVE-NEXT:    strh w9, [sp, #278]
1464; NONEON-NOSVE-NEXT:    strh w8, [sp, #274]
1465; NONEON-NOSVE-NEXT:    ldr w8, [sp, #296]
1466; NONEON-NOSVE-NEXT:    strh w8, [sp, #272]
1467; NONEON-NOSVE-NEXT:    ldp q1, q0, [sp, #256]
1468; NONEON-NOSVE-NEXT:    stp q1, q0, [x1]
1469; NONEON-NOSVE-NEXT:    add sp, sp, #304
1470; NONEON-NOSVE-NEXT:    ret
1471  %op1 = load <16 x double>, ptr %a
1472  %res = fptoui <16 x double> %op1 to <16 x i16>
1473  store <16 x i16> %res, ptr %b
1474  ret void
1475}
1476
1477;
1478; FCVTZU D -> S
1479;
1480
1481define <1 x i32> @fcvtzu_v1f64_v1i32(<1 x double> %op1) {
1482; CHECK-LABEL: fcvtzu_v1f64_v1i32:
1483; CHECK:       // %bb.0:
1484; CHECK-NEXT:    ptrue p0.d, vl2
1485; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
1486; CHECK-NEXT:    fcvtzu z0.d, p0/m, z0.d
1487; CHECK-NEXT:    uzp1 z0.s, z0.s, z0.s
1488; CHECK-NEXT:    // kill: def $d0 killed $d0 killed $z0
1489; CHECK-NEXT:    ret
1490;
1491; NONEON-NOSVE-LABEL: fcvtzu_v1f64_v1i32:
1492; NONEON-NOSVE:       // %bb.0:
1493; NONEON-NOSVE-NEXT:    sub sp, sp, #16
1494; NONEON-NOSVE-NEXT:    .cfi_def_cfa_offset 16
1495; NONEON-NOSVE-NEXT:    fcvtzu w8, d0
1496; NONEON-NOSVE-NEXT:    str w8, [sp, #8]
1497; NONEON-NOSVE-NEXT:    ldr d0, [sp, #8]
1498; NONEON-NOSVE-NEXT:    add sp, sp, #16
1499; NONEON-NOSVE-NEXT:    ret
1500  %res = fptoui <1 x double> %op1 to <1 x i32>
1501  ret <1 x i32> %res
1502}
1503
1504define <2 x i32> @fcvtzu_v2f64_v2i32(<2 x double> %op1) {
1505; CHECK-LABEL: fcvtzu_v2f64_v2i32:
1506; CHECK:       // %bb.0:
1507; CHECK-NEXT:    ptrue p0.d, vl2
1508; CHECK-NEXT:    // kill: def $q0 killed $q0 def $z0
1509; CHECK-NEXT:    fcvtzu z0.d, p0/m, z0.d
1510; CHECK-NEXT:    uzp1 z0.s, z0.s, z0.s
1511; CHECK-NEXT:    // kill: def $d0 killed $d0 killed $z0
1512; CHECK-NEXT:    ret
1513;
1514; NONEON-NOSVE-LABEL: fcvtzu_v2f64_v2i32:
1515; NONEON-NOSVE:       // %bb.0:
1516; NONEON-NOSVE-NEXT:    str q0, [sp, #-32]!
1517; NONEON-NOSVE-NEXT:    .cfi_def_cfa_offset 32
1518; NONEON-NOSVE-NEXT:    ldp d0, d1, [sp]
1519; NONEON-NOSVE-NEXT:    fcvtzu w9, d1
1520; NONEON-NOSVE-NEXT:    fcvtzu w8, d0
1521; NONEON-NOSVE-NEXT:    stp w8, w9, [sp, #24]
1522; NONEON-NOSVE-NEXT:    ldr d0, [sp, #24]
1523; NONEON-NOSVE-NEXT:    add sp, sp, #32
1524; NONEON-NOSVE-NEXT:    ret
1525  %res = fptoui <2 x double> %op1 to <2 x i32>
1526  ret <2 x i32> %res
1527}
1528
1529define <4 x i32> @fcvtzu_v4f64_v4i32(ptr %a) {
1530; CHECK-LABEL: fcvtzu_v4f64_v4i32:
1531; CHECK:       // %bb.0:
1532; CHECK-NEXT:    ldp q0, q1, [x0]
1533; CHECK-NEXT:    ptrue p0.d, vl2
1534; CHECK-NEXT:    fcvtzu z1.d, p0/m, z1.d
1535; CHECK-NEXT:    fcvtzu z0.d, p0/m, z0.d
1536; CHECK-NEXT:    ptrue p0.s, vl2
1537; CHECK-NEXT:    uzp1 z1.s, z1.s, z1.s
1538; CHECK-NEXT:    uzp1 z0.s, z0.s, z0.s
1539; CHECK-NEXT:    splice z0.s, p0, z0.s, z1.s
1540; CHECK-NEXT:    // kill: def $q0 killed $q0 killed $z0
1541; CHECK-NEXT:    ret
1542;
1543; NONEON-NOSVE-LABEL: fcvtzu_v4f64_v4i32:
1544; NONEON-NOSVE:       // %bb.0:
1545; NONEON-NOSVE-NEXT:    ldp q1, q0, [x0]
1546; NONEON-NOSVE-NEXT:    stp q1, q0, [sp, #-48]!
1547; NONEON-NOSVE-NEXT:    .cfi_def_cfa_offset 48
1548; NONEON-NOSVE-NEXT:    ldp d0, d1, [sp, #16]
1549; NONEON-NOSVE-NEXT:    fcvtzu w9, d1
1550; NONEON-NOSVE-NEXT:    fcvtzu w8, d0
1551; NONEON-NOSVE-NEXT:    ldp d0, d1, [sp]
1552; NONEON-NOSVE-NEXT:    stp w8, w9, [sp, #40]
1553; NONEON-NOSVE-NEXT:    fcvtzu w9, d1
1554; NONEON-NOSVE-NEXT:    fcvtzu w8, d0
1555; NONEON-NOSVE-NEXT:    stp w8, w9, [sp, #32]
1556; NONEON-NOSVE-NEXT:    ldr q0, [sp, #32]
1557; NONEON-NOSVE-NEXT:    add sp, sp, #48
1558; NONEON-NOSVE-NEXT:    ret
1559  %op1 = load <4 x double>, ptr %a
1560  %res = fptoui <4 x double> %op1 to <4 x i32>
1561  ret <4 x i32> %res
1562}
1563
1564define void @fcvtzu_v8f64_v8i32(ptr %a, ptr %b) {
1565; CHECK-LABEL: fcvtzu_v8f64_v8i32:
1566; CHECK:       // %bb.0:
1567; CHECK-NEXT:    ldp q0, q1, [x0, #32]
1568; CHECK-NEXT:    ptrue p0.d, vl2
1569; CHECK-NEXT:    ldp q2, q3, [x0]
1570; CHECK-NEXT:    fcvtzu z1.d, p0/m, z1.d
1571; CHECK-NEXT:    fcvtzu z0.d, p0/m, z0.d
1572; CHECK-NEXT:    fcvtzu z3.d, p0/m, z3.d
1573; CHECK-NEXT:    fcvtzu z2.d, p0/m, z2.d
1574; CHECK-NEXT:    ptrue p0.s, vl2
1575; CHECK-NEXT:    uzp1 z1.s, z1.s, z1.s
1576; CHECK-NEXT:    uzp1 z0.s, z0.s, z0.s
1577; CHECK-NEXT:    uzp1 z3.s, z3.s, z3.s
1578; CHECK-NEXT:    uzp1 z2.s, z2.s, z2.s
1579; CHECK-NEXT:    splice z0.s, p0, z0.s, z1.s
1580; CHECK-NEXT:    splice z2.s, p0, z2.s, z3.s
1581; CHECK-NEXT:    stp q2, q0, [x1]
1582; CHECK-NEXT:    ret
1583;
1584; NONEON-NOSVE-LABEL: fcvtzu_v8f64_v8i32:
1585; NONEON-NOSVE:       // %bb.0:
1586; NONEON-NOSVE-NEXT:    sub sp, sp, #96
1587; NONEON-NOSVE-NEXT:    .cfi_def_cfa_offset 96
1588; NONEON-NOSVE-NEXT:    ldp q1, q0, [x0]
1589; NONEON-NOSVE-NEXT:    ldp q2, q3, [x0, #32]
1590; NONEON-NOSVE-NEXT:    str q1, [sp]
1591; NONEON-NOSVE-NEXT:    stp q3, q0, [sp, #16]
1592; NONEON-NOSVE-NEXT:    ldp d0, d1, [sp, #32]
1593; NONEON-NOSVE-NEXT:    str q2, [sp, #48]
1594; NONEON-NOSVE-NEXT:    fcvtzu w9, d1
1595; NONEON-NOSVE-NEXT:    fcvtzu w8, d0
1596; NONEON-NOSVE-NEXT:    ldp d0, d1, [sp]
1597; NONEON-NOSVE-NEXT:    stp w8, w9, [sp, #72]
1598; NONEON-NOSVE-NEXT:    fcvtzu w9, d1
1599; NONEON-NOSVE-NEXT:    fcvtzu w8, d0
1600; NONEON-NOSVE-NEXT:    ldp d0, d1, [sp, #16]
1601; NONEON-NOSVE-NEXT:    stp w8, w9, [sp, #64]
1602; NONEON-NOSVE-NEXT:    fcvtzu w9, d1
1603; NONEON-NOSVE-NEXT:    fcvtzu w8, d0
1604; NONEON-NOSVE-NEXT:    ldp d0, d1, [sp, #48]
1605; NONEON-NOSVE-NEXT:    stp w8, w9, [sp, #88]
1606; NONEON-NOSVE-NEXT:    fcvtzu w9, d1
1607; NONEON-NOSVE-NEXT:    fcvtzu w8, d0
1608; NONEON-NOSVE-NEXT:    stp w8, w9, [sp, #80]
1609; NONEON-NOSVE-NEXT:    ldp q1, q0, [sp, #64]
1610; NONEON-NOSVE-NEXT:    stp q1, q0, [x1]
1611; NONEON-NOSVE-NEXT:    add sp, sp, #96
1612; NONEON-NOSVE-NEXT:    ret
1613  %op1 = load <8 x double>, ptr %a
1614  %res = fptoui <8 x double> %op1 to <8 x i32>
1615  store <8 x i32> %res, ptr %b
1616  ret void
1617}
1618
1619;
1620; FCVTZU D -> D
1621;
1622
1623define <1 x i64> @fcvtzu_v1f64_v1i64(<1 x double> %op1) {
1624; CHECK-LABEL: fcvtzu_v1f64_v1i64:
1625; CHECK:       // %bb.0:
1626; CHECK-NEXT:    ptrue p0.d, vl1
1627; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
1628; CHECK-NEXT:    fcvtzu z0.d, p0/m, z0.d
1629; CHECK-NEXT:    // kill: def $d0 killed $d0 killed $z0
1630; CHECK-NEXT:    ret
1631;
1632; NONEON-NOSVE-LABEL: fcvtzu_v1f64_v1i64:
1633; NONEON-NOSVE:       // %bb.0:
1634; NONEON-NOSVE-NEXT:    sub sp, sp, #16
1635; NONEON-NOSVE-NEXT:    .cfi_def_cfa_offset 16
1636; NONEON-NOSVE-NEXT:    fcvtzu x8, d0
1637; NONEON-NOSVE-NEXT:    str x8, [sp, #8]
1638; NONEON-NOSVE-NEXT:    ldr d0, [sp, #8]
1639; NONEON-NOSVE-NEXT:    add sp, sp, #16
1640; NONEON-NOSVE-NEXT:    ret
1641  %res = fptoui <1 x double> %op1 to <1 x i64>
1642  ret <1 x i64> %res
1643}
1644
1645define <2 x i64> @fcvtzu_v2f64_v2i64(<2 x double> %op1) {
1646; CHECK-LABEL: fcvtzu_v2f64_v2i64:
1647; CHECK:       // %bb.0:
1648; CHECK-NEXT:    ptrue p0.d, vl2
1649; CHECK-NEXT:    // kill: def $q0 killed $q0 def $z0
1650; CHECK-NEXT:    fcvtzu z0.d, p0/m, z0.d
1651; CHECK-NEXT:    // kill: def $q0 killed $q0 killed $z0
1652; CHECK-NEXT:    ret
1653;
1654; NONEON-NOSVE-LABEL: fcvtzu_v2f64_v2i64:
1655; NONEON-NOSVE:       // %bb.0:
1656; NONEON-NOSVE-NEXT:    str q0, [sp, #-32]!
1657; NONEON-NOSVE-NEXT:    .cfi_def_cfa_offset 32
1658; NONEON-NOSVE-NEXT:    ldp d0, d1, [sp]
1659; NONEON-NOSVE-NEXT:    fcvtzu x9, d1
1660; NONEON-NOSVE-NEXT:    fcvtzu x8, d0
1661; NONEON-NOSVE-NEXT:    stp x8, x9, [sp, #16]
1662; NONEON-NOSVE-NEXT:    ldr q0, [sp, #16]
1663; NONEON-NOSVE-NEXT:    add sp, sp, #32
1664; NONEON-NOSVE-NEXT:    ret
1665  %res = fptoui <2 x double> %op1 to <2 x i64>
1666  ret <2 x i64> %res
1667}
1668
1669define void @fcvtzu_v4f64_v4i64(ptr %a, ptr %b) {
1670; CHECK-LABEL: fcvtzu_v4f64_v4i64:
1671; CHECK:       // %bb.0:
1672; CHECK-NEXT:    ldp q0, q1, [x0]
1673; CHECK-NEXT:    ptrue p0.d, vl2
1674; CHECK-NEXT:    fcvtzu z0.d, p0/m, z0.d
1675; CHECK-NEXT:    fcvtzu z1.d, p0/m, z1.d
1676; CHECK-NEXT:    stp q0, q1, [x1]
1677; CHECK-NEXT:    ret
1678;
1679; NONEON-NOSVE-LABEL: fcvtzu_v4f64_v4i64:
1680; NONEON-NOSVE:       // %bb.0:
1681; NONEON-NOSVE-NEXT:    ldp q1, q0, [x0]
1682; NONEON-NOSVE-NEXT:    stp q1, q0, [sp, #-64]!
1683; NONEON-NOSVE-NEXT:    .cfi_def_cfa_offset 64
1684; NONEON-NOSVE-NEXT:    ldp d0, d1, [sp, #16]
1685; NONEON-NOSVE-NEXT:    fcvtzu x9, d1
1686; NONEON-NOSVE-NEXT:    fcvtzu x8, d0
1687; NONEON-NOSVE-NEXT:    ldp d0, d1, [sp]
1688; NONEON-NOSVE-NEXT:    stp x8, x9, [sp, #48]
1689; NONEON-NOSVE-NEXT:    fcvtzu x9, d1
1690; NONEON-NOSVE-NEXT:    fcvtzu x8, d0
1691; NONEON-NOSVE-NEXT:    stp x8, x9, [sp, #32]
1692; NONEON-NOSVE-NEXT:    ldp q0, q1, [sp, #32]
1693; NONEON-NOSVE-NEXT:    stp q0, q1, [x1]
1694; NONEON-NOSVE-NEXT:    add sp, sp, #64
1695; NONEON-NOSVE-NEXT:    ret
1696  %op1 = load <4 x double>, ptr %a
1697  %res = fptoui <4 x double> %op1 to <4 x i64>
1698  store <4 x i64> %res, ptr %b
1699  ret void
1700}
1701
1702;
1703; FCVTZS H -> H
1704;
1705
1706define <4 x i16> @fcvtzs_v4f16_v4i16(<4 x half> %op1) {
1707; CHECK-LABEL: fcvtzs_v4f16_v4i16:
1708; CHECK:       // %bb.0:
1709; CHECK-NEXT:    ptrue p0.h, vl4
1710; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
1711; CHECK-NEXT:    fcvtzs z0.h, p0/m, z0.h
1712; CHECK-NEXT:    // kill: def $d0 killed $d0 killed $z0
1713; CHECK-NEXT:    ret
1714;
1715; NONEON-NOSVE-LABEL: fcvtzs_v4f16_v4i16:
1716; NONEON-NOSVE:       // %bb.0:
1717; NONEON-NOSVE-NEXT:    str d0, [sp, #-16]!
1718; NONEON-NOSVE-NEXT:    .cfi_def_cfa_offset 16
1719; NONEON-NOSVE-NEXT:    ldr h0, [sp, #6]
1720; NONEON-NOSVE-NEXT:    fcvt s0, h0
1721; NONEON-NOSVE-NEXT:    fcvtzs w8, s0
1722; NONEON-NOSVE-NEXT:    ldr h0, [sp, #4]
1723; NONEON-NOSVE-NEXT:    fcvt s0, h0
1724; NONEON-NOSVE-NEXT:    strh w8, [sp, #14]
1725; NONEON-NOSVE-NEXT:    fcvtzs w8, s0
1726; NONEON-NOSVE-NEXT:    ldr h0, [sp, #2]
1727; NONEON-NOSVE-NEXT:    fcvt s0, h0
1728; NONEON-NOSVE-NEXT:    strh w8, [sp, #12]
1729; NONEON-NOSVE-NEXT:    fcvtzs w8, s0
1730; NONEON-NOSVE-NEXT:    ldr h0, [sp]
1731; NONEON-NOSVE-NEXT:    fcvt s0, h0
1732; NONEON-NOSVE-NEXT:    strh w8, [sp, #10]
1733; NONEON-NOSVE-NEXT:    fcvtzs w8, s0
1734; NONEON-NOSVE-NEXT:    strh w8, [sp, #8]
1735; NONEON-NOSVE-NEXT:    ldr d0, [sp, #8]
1736; NONEON-NOSVE-NEXT:    add sp, sp, #16
1737; NONEON-NOSVE-NEXT:    ret
1738  %res = fptosi <4 x half> %op1 to <4 x i16>
1739  ret <4 x i16> %res
1740}
1741
1742define void @fcvtzs_v8f16_v8i16(ptr %a, ptr %b) {
1743; CHECK-LABEL: fcvtzs_v8f16_v8i16:
1744; CHECK:       // %bb.0:
1745; CHECK-NEXT:    ptrue p0.h, vl8
1746; CHECK-NEXT:    ldr q0, [x0]
1747; CHECK-NEXT:    fcvtzs z0.h, p0/m, z0.h
1748; CHECK-NEXT:    str q0, [x1]
1749; CHECK-NEXT:    ret
1750;
1751; NONEON-NOSVE-LABEL: fcvtzs_v8f16_v8i16:
1752; NONEON-NOSVE:       // %bb.0:
1753; NONEON-NOSVE-NEXT:    ldr q0, [x0]
1754; NONEON-NOSVE-NEXT:    str q0, [sp, #-32]!
1755; NONEON-NOSVE-NEXT:    .cfi_def_cfa_offset 32
1756; NONEON-NOSVE-NEXT:    ldr h0, [sp, #14]
1757; NONEON-NOSVE-NEXT:    fcvt s0, h0
1758; NONEON-NOSVE-NEXT:    fcvtzs w8, s0
1759; NONEON-NOSVE-NEXT:    ldr h0, [sp, #12]
1760; NONEON-NOSVE-NEXT:    fcvt s0, h0
1761; NONEON-NOSVE-NEXT:    strh w8, [sp, #30]
1762; NONEON-NOSVE-NEXT:    fcvtzs w8, s0
1763; NONEON-NOSVE-NEXT:    ldr h0, [sp, #10]
1764; NONEON-NOSVE-NEXT:    fcvt s0, h0
1765; NONEON-NOSVE-NEXT:    strh w8, [sp, #28]
1766; NONEON-NOSVE-NEXT:    fcvtzs w8, s0
1767; NONEON-NOSVE-NEXT:    ldr h0, [sp, #8]
1768; NONEON-NOSVE-NEXT:    fcvt s0, h0
1769; NONEON-NOSVE-NEXT:    strh w8, [sp, #26]
1770; NONEON-NOSVE-NEXT:    fcvtzs w8, s0
1771; NONEON-NOSVE-NEXT:    ldr h0, [sp, #6]
1772; NONEON-NOSVE-NEXT:    fcvt s0, h0
1773; NONEON-NOSVE-NEXT:    strh w8, [sp, #24]
1774; NONEON-NOSVE-NEXT:    fcvtzs w8, s0
1775; NONEON-NOSVE-NEXT:    ldr h0, [sp, #4]
1776; NONEON-NOSVE-NEXT:    fcvt s0, h0
1777; NONEON-NOSVE-NEXT:    strh w8, [sp, #22]
1778; NONEON-NOSVE-NEXT:    fcvtzs w8, s0
1779; NONEON-NOSVE-NEXT:    ldr h0, [sp, #2]
1780; NONEON-NOSVE-NEXT:    fcvt s0, h0
1781; NONEON-NOSVE-NEXT:    strh w8, [sp, #20]
1782; NONEON-NOSVE-NEXT:    fcvtzs w8, s0
1783; NONEON-NOSVE-NEXT:    ldr h0, [sp]
1784; NONEON-NOSVE-NEXT:    fcvt s0, h0
1785; NONEON-NOSVE-NEXT:    strh w8, [sp, #18]
1786; NONEON-NOSVE-NEXT:    fcvtzs w8, s0
1787; NONEON-NOSVE-NEXT:    strh w8, [sp, #16]
1788; NONEON-NOSVE-NEXT:    ldr q0, [sp, #16]
1789; NONEON-NOSVE-NEXT:    str q0, [x1]
1790; NONEON-NOSVE-NEXT:    add sp, sp, #32
1791; NONEON-NOSVE-NEXT:    ret
1792  %op1 = load <8 x half>, ptr %a
1793  %res = fptosi <8 x half> %op1 to <8 x i16>
1794  store <8 x i16> %res, ptr %b
1795  ret void
1796}
1797
1798define void @fcvtzs_v16f16_v16i16(ptr %a, ptr %b) {
1799; CHECK-LABEL: fcvtzs_v16f16_v16i16:
1800; CHECK:       // %bb.0:
1801; CHECK-NEXT:    ldp q0, q1, [x0]
1802; CHECK-NEXT:    ptrue p0.h, vl8
1803; CHECK-NEXT:    fcvtzs z0.h, p0/m, z0.h
1804; CHECK-NEXT:    fcvtzs z1.h, p0/m, z1.h
1805; CHECK-NEXT:    stp q0, q1, [x1]
1806; CHECK-NEXT:    ret
1807;
1808; NONEON-NOSVE-LABEL: fcvtzs_v16f16_v16i16:
1809; NONEON-NOSVE:       // %bb.0:
1810; NONEON-NOSVE-NEXT:    ldp q1, q0, [x0]
1811; NONEON-NOSVE-NEXT:    stp q1, q0, [sp, #-64]!
1812; NONEON-NOSVE-NEXT:    .cfi_def_cfa_offset 64
1813; NONEON-NOSVE-NEXT:    ldr h0, [sp, #30]
1814; NONEON-NOSVE-NEXT:    fcvt s0, h0
1815; NONEON-NOSVE-NEXT:    fcvtzs w8, s0
1816; NONEON-NOSVE-NEXT:    ldr h0, [sp, #28]
1817; NONEON-NOSVE-NEXT:    fcvt s0, h0
1818; NONEON-NOSVE-NEXT:    strh w8, [sp, #62]
1819; NONEON-NOSVE-NEXT:    fcvtzs w8, s0
1820; NONEON-NOSVE-NEXT:    ldr h0, [sp, #26]
1821; NONEON-NOSVE-NEXT:    fcvt s0, h0
1822; NONEON-NOSVE-NEXT:    strh w8, [sp, #60]
1823; NONEON-NOSVE-NEXT:    fcvtzs w8, s0
1824; NONEON-NOSVE-NEXT:    ldr h0, [sp, #24]
1825; NONEON-NOSVE-NEXT:    fcvt s0, h0
1826; NONEON-NOSVE-NEXT:    strh w8, [sp, #58]
1827; NONEON-NOSVE-NEXT:    fcvtzs w8, s0
1828; NONEON-NOSVE-NEXT:    ldr h0, [sp, #22]
1829; NONEON-NOSVE-NEXT:    fcvt s0, h0
1830; NONEON-NOSVE-NEXT:    strh w8, [sp, #56]
1831; NONEON-NOSVE-NEXT:    fcvtzs w8, s0
1832; NONEON-NOSVE-NEXT:    ldr h0, [sp, #20]
1833; NONEON-NOSVE-NEXT:    fcvt s0, h0
1834; NONEON-NOSVE-NEXT:    strh w8, [sp, #54]
1835; NONEON-NOSVE-NEXT:    fcvtzs w8, s0
1836; NONEON-NOSVE-NEXT:    ldr h0, [sp, #18]
1837; NONEON-NOSVE-NEXT:    fcvt s0, h0
1838; NONEON-NOSVE-NEXT:    strh w8, [sp, #52]
1839; NONEON-NOSVE-NEXT:    fcvtzs w8, s0
1840; NONEON-NOSVE-NEXT:    ldr h0, [sp, #16]
1841; NONEON-NOSVE-NEXT:    fcvt s0, h0
1842; NONEON-NOSVE-NEXT:    strh w8, [sp, #50]
1843; NONEON-NOSVE-NEXT:    fcvtzs w8, s0
1844; NONEON-NOSVE-NEXT:    ldr h0, [sp, #14]
1845; NONEON-NOSVE-NEXT:    fcvt s0, h0
1846; NONEON-NOSVE-NEXT:    strh w8, [sp, #48]
1847; NONEON-NOSVE-NEXT:    fcvtzs w8, s0
1848; NONEON-NOSVE-NEXT:    ldr h0, [sp, #12]
1849; NONEON-NOSVE-NEXT:    fcvt s0, h0
1850; NONEON-NOSVE-NEXT:    strh w8, [sp, #46]
1851; NONEON-NOSVE-NEXT:    fcvtzs w8, s0
1852; NONEON-NOSVE-NEXT:    ldr h0, [sp, #10]
1853; NONEON-NOSVE-NEXT:    fcvt s0, h0
1854; NONEON-NOSVE-NEXT:    strh w8, [sp, #44]
1855; NONEON-NOSVE-NEXT:    fcvtzs w8, s0
1856; NONEON-NOSVE-NEXT:    ldr h0, [sp, #8]
1857; NONEON-NOSVE-NEXT:    fcvt s0, h0
1858; NONEON-NOSVE-NEXT:    strh w8, [sp, #42]
1859; NONEON-NOSVE-NEXT:    fcvtzs w8, s0
1860; NONEON-NOSVE-NEXT:    ldr h0, [sp, #6]
1861; NONEON-NOSVE-NEXT:    fcvt s0, h0
1862; NONEON-NOSVE-NEXT:    strh w8, [sp, #40]
1863; NONEON-NOSVE-NEXT:    fcvtzs w8, s0
1864; NONEON-NOSVE-NEXT:    ldr h0, [sp, #4]
1865; NONEON-NOSVE-NEXT:    fcvt s0, h0
1866; NONEON-NOSVE-NEXT:    strh w8, [sp, #38]
1867; NONEON-NOSVE-NEXT:    fcvtzs w8, s0
1868; NONEON-NOSVE-NEXT:    ldr h0, [sp, #2]
1869; NONEON-NOSVE-NEXT:    fcvt s0, h0
1870; NONEON-NOSVE-NEXT:    strh w8, [sp, #36]
1871; NONEON-NOSVE-NEXT:    fcvtzs w8, s0
1872; NONEON-NOSVE-NEXT:    ldr h0, [sp]
1873; NONEON-NOSVE-NEXT:    fcvt s0, h0
1874; NONEON-NOSVE-NEXT:    strh w8, [sp, #34]
1875; NONEON-NOSVE-NEXT:    fcvtzs w8, s0
1876; NONEON-NOSVE-NEXT:    strh w8, [sp, #32]
1877; NONEON-NOSVE-NEXT:    ldp q0, q1, [sp, #32]
1878; NONEON-NOSVE-NEXT:    stp q0, q1, [x1]
1879; NONEON-NOSVE-NEXT:    add sp, sp, #64
1880; NONEON-NOSVE-NEXT:    ret
1881  %op1 = load <16 x half>, ptr %a
1882  %res = fptosi <16 x half> %op1 to <16 x i16>
1883  store <16 x i16> %res, ptr %b
1884  ret void
1885}
1886
1887;
1888; FCVTZS H -> S
1889;
1890
1891define <2 x i32> @fcvtzs_v2f16_v2i32(<2 x half> %op1) {
1892; CHECK-LABEL: fcvtzs_v2f16_v2i32:
1893; CHECK:       // %bb.0:
1894; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
1895; CHECK-NEXT:    ptrue p0.s, vl4
1896; CHECK-NEXT:    uunpklo z0.s, z0.h
1897; CHECK-NEXT:    fcvtzs z0.s, p0/m, z0.h
1898; CHECK-NEXT:    // kill: def $d0 killed $d0 killed $z0
1899; CHECK-NEXT:    ret
1900;
1901; NONEON-NOSVE-LABEL: fcvtzs_v2f16_v2i32:
1902; NONEON-NOSVE:       // %bb.0:
1903; NONEON-NOSVE-NEXT:    str d0, [sp, #-16]!
1904; NONEON-NOSVE-NEXT:    .cfi_def_cfa_offset 16
1905; NONEON-NOSVE-NEXT:    ldr h0, [sp, #2]
1906; NONEON-NOSVE-NEXT:    fcvt s0, h0
1907; NONEON-NOSVE-NEXT:    fcvtzs w9, s0
1908; NONEON-NOSVE-NEXT:    ldr h0, [sp]
1909; NONEON-NOSVE-NEXT:    fcvt s0, h0
1910; NONEON-NOSVE-NEXT:    fcvtzs w8, s0
1911; NONEON-NOSVE-NEXT:    stp w8, w9, [sp, #8]
1912; NONEON-NOSVE-NEXT:    ldr d0, [sp, #8]
1913; NONEON-NOSVE-NEXT:    add sp, sp, #16
1914; NONEON-NOSVE-NEXT:    ret
1915  %res = fptosi <2 x half> %op1 to <2 x i32>
1916  ret <2 x i32> %res
1917}
1918
1919define <4 x i32> @fcvtzs_v4f16_v4i32(<4 x half> %op1) {
1920; CHECK-LABEL: fcvtzs_v4f16_v4i32:
1921; CHECK:       // %bb.0:
1922; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
1923; CHECK-NEXT:    ptrue p0.s, vl4
1924; CHECK-NEXT:    uunpklo z0.s, z0.h
1925; CHECK-NEXT:    fcvtzs z0.s, p0/m, z0.h
1926; CHECK-NEXT:    // kill: def $q0 killed $q0 killed $z0
1927; CHECK-NEXT:    ret
1928;
1929; NONEON-NOSVE-LABEL: fcvtzs_v4f16_v4i32:
1930; NONEON-NOSVE:       // %bb.0:
1931; NONEON-NOSVE-NEXT:    sub sp, sp, #32
1932; NONEON-NOSVE-NEXT:    .cfi_def_cfa_offset 32
1933; NONEON-NOSVE-NEXT:    str d0, [sp, #8]
1934; NONEON-NOSVE-NEXT:    ldr h0, [sp, #14]
1935; NONEON-NOSVE-NEXT:    fcvt s0, h0
1936; NONEON-NOSVE-NEXT:    fcvtzs w9, s0
1937; NONEON-NOSVE-NEXT:    ldr h0, [sp, #12]
1938; NONEON-NOSVE-NEXT:    fcvt s0, h0
1939; NONEON-NOSVE-NEXT:    fcvtzs w8, s0
1940; NONEON-NOSVE-NEXT:    ldr h0, [sp, #10]
1941; NONEON-NOSVE-NEXT:    fcvt s0, h0
1942; NONEON-NOSVE-NEXT:    stp w8, w9, [sp, #24]
1943; NONEON-NOSVE-NEXT:    fcvtzs w9, s0
1944; NONEON-NOSVE-NEXT:    ldr h0, [sp, #8]
1945; NONEON-NOSVE-NEXT:    fcvt s0, h0
1946; NONEON-NOSVE-NEXT:    fcvtzs w8, s0
1947; NONEON-NOSVE-NEXT:    stp w8, w9, [sp, #16]
1948; NONEON-NOSVE-NEXT:    ldr q0, [sp, #16]
1949; NONEON-NOSVE-NEXT:    add sp, sp, #32
1950; NONEON-NOSVE-NEXT:    ret
1951  %res = fptosi <4 x half> %op1 to <4 x i32>
1952  ret <4 x i32> %res
1953}
1954
1955define void @fcvtzs_v8f16_v8i32(ptr %a, ptr %b) {
1956; CHECK-LABEL: fcvtzs_v8f16_v8i32:
1957; CHECK:       // %bb.0:
1958; CHECK-NEXT:    ldr q0, [x0]
1959; CHECK-NEXT:    ptrue p0.s, vl4
1960; CHECK-NEXT:    uunpklo z1.s, z0.h
1961; CHECK-NEXT:    ext z0.b, z0.b, z0.b, #8
1962; CHECK-NEXT:    uunpklo z0.s, z0.h
1963; CHECK-NEXT:    fcvtzs z1.s, p0/m, z1.h
1964; CHECK-NEXT:    fcvtzs z0.s, p0/m, z0.h
1965; CHECK-NEXT:    stp q1, q0, [x1]
1966; CHECK-NEXT:    ret
1967;
1968; NONEON-NOSVE-LABEL: fcvtzs_v8f16_v8i32:
1969; NONEON-NOSVE:       // %bb.0:
1970; NONEON-NOSVE-NEXT:    ldr q0, [x0]
1971; NONEON-NOSVE-NEXT:    str q0, [sp, #-64]!
1972; NONEON-NOSVE-NEXT:    .cfi_def_cfa_offset 64
1973; NONEON-NOSVE-NEXT:    ldp d1, d0, [sp]
1974; NONEON-NOSVE-NEXT:    stp d0, d1, [sp, #16]
1975; NONEON-NOSVE-NEXT:    ldr h0, [sp, #30]
1976; NONEON-NOSVE-NEXT:    fcvt s0, h0
1977; NONEON-NOSVE-NEXT:    fcvtzs w9, s0
1978; NONEON-NOSVE-NEXT:    ldr h0, [sp, #28]
1979; NONEON-NOSVE-NEXT:    fcvt s0, h0
1980; NONEON-NOSVE-NEXT:    fcvtzs w8, s0
1981; NONEON-NOSVE-NEXT:    ldr h0, [sp, #26]
1982; NONEON-NOSVE-NEXT:    fcvt s0, h0
1983; NONEON-NOSVE-NEXT:    stp w8, w9, [sp, #56]
1984; NONEON-NOSVE-NEXT:    fcvtzs w9, s0
1985; NONEON-NOSVE-NEXT:    ldr h0, [sp, #24]
1986; NONEON-NOSVE-NEXT:    fcvt s0, h0
1987; NONEON-NOSVE-NEXT:    fcvtzs w8, s0
1988; NONEON-NOSVE-NEXT:    ldr h0, [sp, #22]
1989; NONEON-NOSVE-NEXT:    fcvt s0, h0
1990; NONEON-NOSVE-NEXT:    stp w8, w9, [sp, #48]
1991; NONEON-NOSVE-NEXT:    fcvtzs w9, s0
1992; NONEON-NOSVE-NEXT:    ldr h0, [sp, #20]
1993; NONEON-NOSVE-NEXT:    fcvt s0, h0
1994; NONEON-NOSVE-NEXT:    fcvtzs w8, s0
1995; NONEON-NOSVE-NEXT:    ldr h0, [sp, #18]
1996; NONEON-NOSVE-NEXT:    fcvt s0, h0
1997; NONEON-NOSVE-NEXT:    stp w8, w9, [sp, #40]
1998; NONEON-NOSVE-NEXT:    fcvtzs w9, s0
1999; NONEON-NOSVE-NEXT:    ldr h0, [sp, #16]
2000; NONEON-NOSVE-NEXT:    fcvt s0, h0
2001; NONEON-NOSVE-NEXT:    fcvtzs w8, s0
2002; NONEON-NOSVE-NEXT:    stp w8, w9, [sp, #32]
2003; NONEON-NOSVE-NEXT:    ldp q0, q1, [sp, #32]
2004; NONEON-NOSVE-NEXT:    stp q1, q0, [x1]
2005; NONEON-NOSVE-NEXT:    add sp, sp, #64
2006; NONEON-NOSVE-NEXT:    ret
2007  %op1 = load <8 x half>, ptr %a
2008  %res = fptosi <8 x half> %op1 to <8 x i32>
2009  store <8 x i32> %res, ptr %b
2010  ret void
2011}
2012
2013define void @fcvtzs_v16f16_v16i32(ptr %a, ptr %b) {
2014; CHECK-LABEL: fcvtzs_v16f16_v16i32:
2015; CHECK:       // %bb.0:
2016; CHECK-NEXT:    ldp q1, q0, [x0]
2017; CHECK-NEXT:    ptrue p0.s, vl4
2018; CHECK-NEXT:    uunpklo z2.s, z0.h
2019; CHECK-NEXT:    ext z0.b, z0.b, z0.b, #8
2020; CHECK-NEXT:    uunpklo z3.s, z1.h
2021; CHECK-NEXT:    ext z1.b, z1.b, z1.b, #8
2022; CHECK-NEXT:    uunpklo z0.s, z0.h
2023; CHECK-NEXT:    uunpklo z1.s, z1.h
2024; CHECK-NEXT:    fcvtzs z2.s, p0/m, z2.h
2025; CHECK-NEXT:    fcvtzs z3.s, p0/m, z3.h
2026; CHECK-NEXT:    fcvtzs z0.s, p0/m, z0.h
2027; CHECK-NEXT:    fcvtzs z1.s, p0/m, z1.h
2028; CHECK-NEXT:    stp q2, q0, [x1, #32]
2029; CHECK-NEXT:    stp q3, q1, [x1]
2030; CHECK-NEXT:    ret
2031;
2032; NONEON-NOSVE-LABEL: fcvtzs_v16f16_v16i32:
2033; NONEON-NOSVE:       // %bb.0:
2034; NONEON-NOSVE-NEXT:    ldp q0, q1, [x0]
2035; NONEON-NOSVE-NEXT:    stp q0, q1, [sp, #-128]!
2036; NONEON-NOSVE-NEXT:    .cfi_def_cfa_offset 128
2037; NONEON-NOSVE-NEXT:    ldp d1, d0, [sp]
2038; NONEON-NOSVE-NEXT:    stp d0, d1, [sp, #32]
2039; NONEON-NOSVE-NEXT:    ldp d1, d0, [sp, #16]
2040; NONEON-NOSVE-NEXT:    stp d0, d1, [sp, #48]
2041; NONEON-NOSVE-NEXT:    ldr h0, [sp, #46]
2042; NONEON-NOSVE-NEXT:    fcvt s0, h0
2043; NONEON-NOSVE-NEXT:    fcvtzs w9, s0
2044; NONEON-NOSVE-NEXT:    ldr h0, [sp, #44]
2045; NONEON-NOSVE-NEXT:    fcvt s0, h0
2046; NONEON-NOSVE-NEXT:    fcvtzs w8, s0
2047; NONEON-NOSVE-NEXT:    ldr h0, [sp, #42]
2048; NONEON-NOSVE-NEXT:    fcvt s0, h0
2049; NONEON-NOSVE-NEXT:    stp w8, w9, [sp, #88]
2050; NONEON-NOSVE-NEXT:    fcvtzs w9, s0
2051; NONEON-NOSVE-NEXT:    ldr h0, [sp, #40]
2052; NONEON-NOSVE-NEXT:    fcvt s0, h0
2053; NONEON-NOSVE-NEXT:    fcvtzs w8, s0
2054; NONEON-NOSVE-NEXT:    ldr h0, [sp, #38]
2055; NONEON-NOSVE-NEXT:    fcvt s0, h0
2056; NONEON-NOSVE-NEXT:    stp w8, w9, [sp, #80]
2057; NONEON-NOSVE-NEXT:    fcvtzs w9, s0
2058; NONEON-NOSVE-NEXT:    ldr h0, [sp, #36]
2059; NONEON-NOSVE-NEXT:    fcvt s0, h0
2060; NONEON-NOSVE-NEXT:    fcvtzs w8, s0
2061; NONEON-NOSVE-NEXT:    ldr h0, [sp, #34]
2062; NONEON-NOSVE-NEXT:    fcvt s0, h0
2063; NONEON-NOSVE-NEXT:    stp w8, w9, [sp, #72]
2064; NONEON-NOSVE-NEXT:    fcvtzs w9, s0
2065; NONEON-NOSVE-NEXT:    ldr h0, [sp, #32]
2066; NONEON-NOSVE-NEXT:    fcvt s0, h0
2067; NONEON-NOSVE-NEXT:    fcvtzs w8, s0
2068; NONEON-NOSVE-NEXT:    ldr h0, [sp, #62]
2069; NONEON-NOSVE-NEXT:    fcvt s0, h0
2070; NONEON-NOSVE-NEXT:    stp w8, w9, [sp, #64]
2071; NONEON-NOSVE-NEXT:    ldp q3, q2, [sp, #64]
2072; NONEON-NOSVE-NEXT:    fcvtzs w9, s0
2073; NONEON-NOSVE-NEXT:    ldr h0, [sp, #60]
2074; NONEON-NOSVE-NEXT:    fcvt s0, h0
2075; NONEON-NOSVE-NEXT:    fcvtzs w8, s0
2076; NONEON-NOSVE-NEXT:    ldr h0, [sp, #58]
2077; NONEON-NOSVE-NEXT:    fcvt s0, h0
2078; NONEON-NOSVE-NEXT:    stp w8, w9, [sp, #120]
2079; NONEON-NOSVE-NEXT:    fcvtzs w9, s0
2080; NONEON-NOSVE-NEXT:    ldr h0, [sp, #56]
2081; NONEON-NOSVE-NEXT:    fcvt s0, h0
2082; NONEON-NOSVE-NEXT:    fcvtzs w8, s0
2083; NONEON-NOSVE-NEXT:    ldr h0, [sp, #54]
2084; NONEON-NOSVE-NEXT:    fcvt s0, h0
2085; NONEON-NOSVE-NEXT:    stp w8, w9, [sp, #112]
2086; NONEON-NOSVE-NEXT:    fcvtzs w9, s0
2087; NONEON-NOSVE-NEXT:    ldr h0, [sp, #52]
2088; NONEON-NOSVE-NEXT:    fcvt s0, h0
2089; NONEON-NOSVE-NEXT:    fcvtzs w8, s0
2090; NONEON-NOSVE-NEXT:    ldr h0, [sp, #50]
2091; NONEON-NOSVE-NEXT:    fcvt s0, h0
2092; NONEON-NOSVE-NEXT:    stp w8, w9, [sp, #104]
2093; NONEON-NOSVE-NEXT:    fcvtzs w9, s0
2094; NONEON-NOSVE-NEXT:    ldr h0, [sp, #48]
2095; NONEON-NOSVE-NEXT:    fcvt s0, h0
2096; NONEON-NOSVE-NEXT:    fcvtzs w8, s0
2097; NONEON-NOSVE-NEXT:    stp w8, w9, [sp, #96]
2098; NONEON-NOSVE-NEXT:    ldp q0, q1, [sp, #96]
2099; NONEON-NOSVE-NEXT:    stp q2, q3, [x1]
2100; NONEON-NOSVE-NEXT:    stp q1, q0, [x1, #32]
2101; NONEON-NOSVE-NEXT:    add sp, sp, #128
2102; NONEON-NOSVE-NEXT:    ret
2103  %op1 = load <16 x half>, ptr %a
2104  %res = fptosi <16 x half> %op1 to <16 x i32>
2105  store <16 x i32> %res, ptr %b
2106  ret void
2107}
2108
2109;
2110; FCVTZS H -> D
2111;
2112
2113define <1 x i64> @fcvtzs_v1f16_v1i64(<1 x half> %op1) {
2114; CHECK-LABEL: fcvtzs_v1f16_v1i64:
2115; CHECK:       // %bb.0:
2116; CHECK-NEXT:    ptrue p0.d
2117; CHECK-NEXT:    // kill: def $h0 killed $h0 def $z0
2118; CHECK-NEXT:    fcvtzs z0.d, p0/m, z0.h
2119; CHECK-NEXT:    // kill: def $d0 killed $d0 killed $z0
2120; CHECK-NEXT:    ret
2121;
2122; NONEON-NOSVE-LABEL: fcvtzs_v1f16_v1i64:
2123; NONEON-NOSVE:       // %bb.0:
2124; NONEON-NOSVE-NEXT:    sub sp, sp, #16
2125; NONEON-NOSVE-NEXT:    .cfi_def_cfa_offset 16
2126; NONEON-NOSVE-NEXT:    fcvt s0, h0
2127; NONEON-NOSVE-NEXT:    fcvtzs x8, s0
2128; NONEON-NOSVE-NEXT:    str x8, [sp, #8]
2129; NONEON-NOSVE-NEXT:    ldr d0, [sp, #8]
2130; NONEON-NOSVE-NEXT:    add sp, sp, #16
2131; NONEON-NOSVE-NEXT:    ret
2132  %res = fptosi <1 x half> %op1 to <1 x i64>
2133  ret <1 x i64> %res
2134}
2135
2136; v2f16 is not legal for NEON, so use SVE
2137define <2 x i64> @fcvtzs_v2f16_v2i64(<2 x half> %op1) {
2138; CHECK-LABEL: fcvtzs_v2f16_v2i64:
2139; CHECK:       // %bb.0:
2140; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
2141; CHECK-NEXT:    mov z1.h, z0.h[1]
2142; CHECK-NEXT:    ptrue p0.d
2143; CHECK-NEXT:    fcvtzs z0.d, p0/m, z0.h
2144; CHECK-NEXT:    fcvtzs z1.d, p0/m, z1.h
2145; CHECK-NEXT:    zip1 z0.d, z0.d, z1.d
2146; CHECK-NEXT:    // kill: def $q0 killed $q0 killed $z0
2147; CHECK-NEXT:    ret
2148;
2149; NONEON-NOSVE-LABEL: fcvtzs_v2f16_v2i64:
2150; NONEON-NOSVE:       // %bb.0:
2151; NONEON-NOSVE-NEXT:    sub sp, sp, #32
2152; NONEON-NOSVE-NEXT:    .cfi_def_cfa_offset 32
2153; NONEON-NOSVE-NEXT:    str d0, [sp, #8]
2154; NONEON-NOSVE-NEXT:    ldr h0, [sp, #10]
2155; NONEON-NOSVE-NEXT:    fcvt s0, h0
2156; NONEON-NOSVE-NEXT:    fcvtzs x9, s0
2157; NONEON-NOSVE-NEXT:    ldr h0, [sp, #8]
2158; NONEON-NOSVE-NEXT:    fcvt s0, h0
2159; NONEON-NOSVE-NEXT:    fcvtzs x8, s0
2160; NONEON-NOSVE-NEXT:    stp x8, x9, [sp, #16]
2161; NONEON-NOSVE-NEXT:    ldr q0, [sp, #16]
2162; NONEON-NOSVE-NEXT:    add sp, sp, #32
2163; NONEON-NOSVE-NEXT:    ret
2164  %res = fptosi <2 x half> %op1 to <2 x i64>
2165  ret <2 x i64> %res
2166}
2167
2168define void @fcvtzs_v4f16_v4i64(ptr %a, ptr %b) {
2169; CHECK-LABEL: fcvtzs_v4f16_v4i64:
2170; CHECK:       // %bb.0:
2171; CHECK-NEXT:    ldr d0, [x0]
2172; CHECK-NEXT:    ptrue p0.d
2173; CHECK-NEXT:    mov z1.h, z0.h[3]
2174; CHECK-NEXT:    mov z2.h, z0.h[2]
2175; CHECK-NEXT:    mov z3.h, z0.h[1]
2176; CHECK-NEXT:    fcvtzs z0.d, p0/m, z0.h
2177; CHECK-NEXT:    fcvtzs z1.d, p0/m, z1.h
2178; CHECK-NEXT:    fcvtzs z2.d, p0/m, z2.h
2179; CHECK-NEXT:    fcvtzs z3.d, p0/m, z3.h
2180; CHECK-NEXT:    zip1 z1.d, z2.d, z1.d
2181; CHECK-NEXT:    zip1 z0.d, z0.d, z3.d
2182; CHECK-NEXT:    stp q0, q1, [x1]
2183; CHECK-NEXT:    ret
2184;
2185; NONEON-NOSVE-LABEL: fcvtzs_v4f16_v4i64:
2186; NONEON-NOSVE:       // %bb.0:
2187; NONEON-NOSVE-NEXT:    sub sp, sp, #48
2188; NONEON-NOSVE-NEXT:    .cfi_def_cfa_offset 48
2189; NONEON-NOSVE-NEXT:    ldr d0, [x0]
2190; NONEON-NOSVE-NEXT:    str d0, [sp, #8]
2191; NONEON-NOSVE-NEXT:    ldr h0, [sp, #10]
2192; NONEON-NOSVE-NEXT:    fcvt s0, h0
2193; NONEON-NOSVE-NEXT:    fcvtzs x9, s0
2194; NONEON-NOSVE-NEXT:    ldr h0, [sp, #8]
2195; NONEON-NOSVE-NEXT:    fcvt s0, h0
2196; NONEON-NOSVE-NEXT:    fcvtzs x8, s0
2197; NONEON-NOSVE-NEXT:    ldr h0, [sp, #14]
2198; NONEON-NOSVE-NEXT:    fcvt s0, h0
2199; NONEON-NOSVE-NEXT:    stp x8, x9, [sp, #16]
2200; NONEON-NOSVE-NEXT:    fcvtzs x9, s0
2201; NONEON-NOSVE-NEXT:    ldr h0, [sp, #12]
2202; NONEON-NOSVE-NEXT:    fcvt s0, h0
2203; NONEON-NOSVE-NEXT:    fcvtzs x8, s0
2204; NONEON-NOSVE-NEXT:    stp x8, x9, [sp, #32]
2205; NONEON-NOSVE-NEXT:    ldp q1, q0, [sp, #16]
2206; NONEON-NOSVE-NEXT:    stp q1, q0, [x1]
2207; NONEON-NOSVE-NEXT:    add sp, sp, #48
2208; NONEON-NOSVE-NEXT:    ret
2209  %op1 = load <4 x half>, ptr %a
2210  %res = fptosi <4 x half> %op1 to <4 x i64>
2211  store <4 x i64> %res, ptr %b
2212  ret void
2213}
2214
2215define void @fcvtzs_v8f16_v8i64(ptr %a, ptr %b) {
2216; CHECK-LABEL: fcvtzs_v8f16_v8i64:
2217; CHECK:       // %bb.0:
2218; CHECK-NEXT:    ldr q0, [x0]
2219; CHECK-NEXT:    ptrue p0.d
2220; CHECK-NEXT:    mov z1.d, z0.d
2221; CHECK-NEXT:    mov z2.h, z0.h[3]
2222; CHECK-NEXT:    mov z3.h, z0.h[2]
2223; CHECK-NEXT:    mov z4.h, z0.h[1]
2224; CHECK-NEXT:    ext z1.b, z1.b, z0.b, #8
2225; CHECK-NEXT:    fcvtzs z2.d, p0/m, z2.h
2226; CHECK-NEXT:    fcvtzs z3.d, p0/m, z3.h
2227; CHECK-NEXT:    fcvtzs z0.d, p0/m, z0.h
2228; CHECK-NEXT:    fcvtzs z4.d, p0/m, z4.h
2229; CHECK-NEXT:    mov z5.h, z1.h[3]
2230; CHECK-NEXT:    mov z6.h, z1.h[2]
2231; CHECK-NEXT:    mov z7.h, z1.h[1]
2232; CHECK-NEXT:    fcvtzs z1.d, p0/m, z1.h
2233; CHECK-NEXT:    zip1 z2.d, z3.d, z2.d
2234; CHECK-NEXT:    zip1 z0.d, z0.d, z4.d
2235; CHECK-NEXT:    fcvtzs z5.d, p0/m, z5.h
2236; CHECK-NEXT:    fcvtzs z6.d, p0/m, z6.h
2237; CHECK-NEXT:    fcvtzs z7.d, p0/m, z7.h
2238; CHECK-NEXT:    stp q0, q2, [x1]
2239; CHECK-NEXT:    zip1 z3.d, z6.d, z5.d
2240; CHECK-NEXT:    zip1 z1.d, z1.d, z7.d
2241; CHECK-NEXT:    stp q1, q3, [x1, #32]
2242; CHECK-NEXT:    ret
2243;
2244; NONEON-NOSVE-LABEL: fcvtzs_v8f16_v8i64:
2245; NONEON-NOSVE:       // %bb.0:
2246; NONEON-NOSVE-NEXT:    ldr q0, [x0]
2247; NONEON-NOSVE-NEXT:    str q0, [sp, #-96]!
2248; NONEON-NOSVE-NEXT:    .cfi_def_cfa_offset 96
2249; NONEON-NOSVE-NEXT:    ldp d1, d0, [sp]
2250; NONEON-NOSVE-NEXT:    stp d0, d1, [sp, #16]
2251; NONEON-NOSVE-NEXT:    ldr h0, [sp, #26]
2252; NONEON-NOSVE-NEXT:    fcvt s0, h0
2253; NONEON-NOSVE-NEXT:    fcvtzs x9, s0
2254; NONEON-NOSVE-NEXT:    ldr h0, [sp, #24]
2255; NONEON-NOSVE-NEXT:    fcvt s0, h0
2256; NONEON-NOSVE-NEXT:    fcvtzs x8, s0
2257; NONEON-NOSVE-NEXT:    ldr h0, [sp, #30]
2258; NONEON-NOSVE-NEXT:    fcvt s0, h0
2259; NONEON-NOSVE-NEXT:    stp x8, x9, [sp, #64]
2260; NONEON-NOSVE-NEXT:    fcvtzs x9, s0
2261; NONEON-NOSVE-NEXT:    ldr h0, [sp, #28]
2262; NONEON-NOSVE-NEXT:    fcvt s0, h0
2263; NONEON-NOSVE-NEXT:    fcvtzs x8, s0
2264; NONEON-NOSVE-NEXT:    ldr h0, [sp, #18]
2265; NONEON-NOSVE-NEXT:    fcvt s0, h0
2266; NONEON-NOSVE-NEXT:    stp x8, x9, [sp, #80]
2267; NONEON-NOSVE-NEXT:    ldp q2, q3, [sp, #64]
2268; NONEON-NOSVE-NEXT:    fcvtzs x9, s0
2269; NONEON-NOSVE-NEXT:    ldr h0, [sp, #16]
2270; NONEON-NOSVE-NEXT:    fcvt s0, h0
2271; NONEON-NOSVE-NEXT:    fcvtzs x8, s0
2272; NONEON-NOSVE-NEXT:    ldr h0, [sp, #22]
2273; NONEON-NOSVE-NEXT:    fcvt s0, h0
2274; NONEON-NOSVE-NEXT:    stp x8, x9, [sp, #32]
2275; NONEON-NOSVE-NEXT:    fcvtzs x9, s0
2276; NONEON-NOSVE-NEXT:    ldr h0, [sp, #20]
2277; NONEON-NOSVE-NEXT:    fcvt s0, h0
2278; NONEON-NOSVE-NEXT:    fcvtzs x8, s0
2279; NONEON-NOSVE-NEXT:    stp x8, x9, [sp, #48]
2280; NONEON-NOSVE-NEXT:    ldp q1, q0, [sp, #32]
2281; NONEON-NOSVE-NEXT:    stp q2, q3, [x1]
2282; NONEON-NOSVE-NEXT:    stp q1, q0, [x1, #32]
2283; NONEON-NOSVE-NEXT:    add sp, sp, #96
2284; NONEON-NOSVE-NEXT:    ret
2285  %op1 = load <8 x half>, ptr %a
2286  %res = fptosi <8 x half> %op1 to <8 x i64>
2287  store <8 x i64> %res, ptr %b
2288  ret void
2289}
2290
2291define void @fcvtzs_v16f16_v16i64(ptr %a, ptr %b) {
2292; CHECK-LABEL: fcvtzs_v16f16_v16i64:
2293; CHECK:       // %bb.0:
2294; CHECK-NEXT:    ldp q1, q0, [x0]
2295; CHECK-NEXT:    ptrue p0.d
2296; CHECK-NEXT:    mov z3.h, z1.h[1]
2297; CHECK-NEXT:    mov z5.h, z0.h[3]
2298; CHECK-NEXT:    mov z6.h, z0.h[2]
2299; CHECK-NEXT:    mov z16.d, z0.d
2300; CHECK-NEXT:    movprfx z2, z1
2301; CHECK-NEXT:    fcvtzs z2.d, p0/m, z1.h
2302; CHECK-NEXT:    mov z4.h, z1.h[3]
2303; CHECK-NEXT:    mov z7.h, z1.h[2]
2304; CHECK-NEXT:    mov z17.h, z0.h[1]
2305; CHECK-NEXT:    ext z1.b, z1.b, z1.b, #8
2306; CHECK-NEXT:    fcvtzs z3.d, p0/m, z3.h
2307; CHECK-NEXT:    fcvtzs z5.d, p0/m, z5.h
2308; CHECK-NEXT:    fcvtzs z6.d, p0/m, z6.h
2309; CHECK-NEXT:    ext z16.b, z16.b, z0.b, #8
2310; CHECK-NEXT:    fcvtzs z0.d, p0/m, z0.h
2311; CHECK-NEXT:    fcvtzs z4.d, p0/m, z4.h
2312; CHECK-NEXT:    fcvtzs z17.d, p0/m, z17.h
2313; CHECK-NEXT:    fcvtzs z7.d, p0/m, z7.h
2314; CHECK-NEXT:    mov z20.h, z1.h[3]
2315; CHECK-NEXT:    mov z18.h, z16.h[3]
2316; CHECK-NEXT:    mov z19.h, z16.h[2]
2317; CHECK-NEXT:    mov z21.h, z16.h[1]
2318; CHECK-NEXT:    zip1 z2.d, z2.d, z3.d
2319; CHECK-NEXT:    mov z3.h, z1.h[2]
2320; CHECK-NEXT:    zip1 z5.d, z6.d, z5.d
2321; CHECK-NEXT:    mov z6.h, z1.h[1]
2322; CHECK-NEXT:    zip1 z0.d, z0.d, z17.d
2323; CHECK-NEXT:    fcvtzs z16.d, p0/m, z16.h
2324; CHECK-NEXT:    fcvtzs z18.d, p0/m, z18.h
2325; CHECK-NEXT:    movprfx z17, z21
2326; CHECK-NEXT:    fcvtzs z17.d, p0/m, z21.h
2327; CHECK-NEXT:    fcvtzs z19.d, p0/m, z19.h
2328; CHECK-NEXT:    zip1 z4.d, z7.d, z4.d
2329; CHECK-NEXT:    movprfx z7, z20
2330; CHECK-NEXT:    fcvtzs z7.d, p0/m, z20.h
2331; CHECK-NEXT:    fcvtzs z3.d, p0/m, z3.h
2332; CHECK-NEXT:    fcvtzs z1.d, p0/m, z1.h
2333; CHECK-NEXT:    stp q0, q5, [x1, #64]
2334; CHECK-NEXT:    fcvtzs z6.d, p0/m, z6.h
2335; CHECK-NEXT:    zip1 z0.d, z19.d, z18.d
2336; CHECK-NEXT:    zip1 z5.d, z16.d, z17.d
2337; CHECK-NEXT:    stp q2, q4, [x1]
2338; CHECK-NEXT:    zip1 z2.d, z3.d, z7.d
2339; CHECK-NEXT:    zip1 z1.d, z1.d, z6.d
2340; CHECK-NEXT:    stp q5, q0, [x1, #96]
2341; CHECK-NEXT:    stp q1, q2, [x1, #32]
2342; CHECK-NEXT:    ret
2343;
2344; NONEON-NOSVE-LABEL: fcvtzs_v16f16_v16i64:
2345; NONEON-NOSVE:       // %bb.0:
2346; NONEON-NOSVE-NEXT:    sub sp, sp, #192
2347; NONEON-NOSVE-NEXT:    .cfi_def_cfa_offset 192
2348; NONEON-NOSVE-NEXT:    ldp q0, q1, [x0]
2349; NONEON-NOSVE-NEXT:    stp q0, q1, [sp]
2350; NONEON-NOSVE-NEXT:    ldp d1, d0, [sp]
2351; NONEON-NOSVE-NEXT:    stp d0, d1, [sp, #32]
2352; NONEON-NOSVE-NEXT:    ldp d1, d0, [sp, #16]
2353; NONEON-NOSVE-NEXT:    stp d0, d1, [sp, #48]
2354; NONEON-NOSVE-NEXT:    ldr h0, [sp, #42]
2355; NONEON-NOSVE-NEXT:    fcvt s0, h0
2356; NONEON-NOSVE-NEXT:    fcvtzs x9, s0
2357; NONEON-NOSVE-NEXT:    ldr h0, [sp, #40]
2358; NONEON-NOSVE-NEXT:    fcvt s0, h0
2359; NONEON-NOSVE-NEXT:    fcvtzs x8, s0
2360; NONEON-NOSVE-NEXT:    ldr h0, [sp, #46]
2361; NONEON-NOSVE-NEXT:    fcvt s0, h0
2362; NONEON-NOSVE-NEXT:    stp x8, x9, [sp, #96]
2363; NONEON-NOSVE-NEXT:    fcvtzs x9, s0
2364; NONEON-NOSVE-NEXT:    ldr h0, [sp, #44]
2365; NONEON-NOSVE-NEXT:    fcvt s0, h0
2366; NONEON-NOSVE-NEXT:    fcvtzs x8, s0
2367; NONEON-NOSVE-NEXT:    ldr h0, [sp, #34]
2368; NONEON-NOSVE-NEXT:    fcvt s0, h0
2369; NONEON-NOSVE-NEXT:    stp x8, x9, [sp, #112]
2370; NONEON-NOSVE-NEXT:    fcvtzs x9, s0
2371; NONEON-NOSVE-NEXT:    ldr h0, [sp, #32]
2372; NONEON-NOSVE-NEXT:    fcvt s0, h0
2373; NONEON-NOSVE-NEXT:    fcvtzs x8, s0
2374; NONEON-NOSVE-NEXT:    ldr h0, [sp, #38]
2375; NONEON-NOSVE-NEXT:    fcvt s0, h0
2376; NONEON-NOSVE-NEXT:    stp x8, x9, [sp, #64]
2377; NONEON-NOSVE-NEXT:    fcvtzs x9, s0
2378; NONEON-NOSVE-NEXT:    ldr h0, [sp, #36]
2379; NONEON-NOSVE-NEXT:    fcvt s0, h0
2380; NONEON-NOSVE-NEXT:    fcvtzs x8, s0
2381; NONEON-NOSVE-NEXT:    ldr h0, [sp, #58]
2382; NONEON-NOSVE-NEXT:    fcvt s0, h0
2383; NONEON-NOSVE-NEXT:    stp x8, x9, [sp, #80]
2384; NONEON-NOSVE-NEXT:    ldp q3, q4, [sp, #64]
2385; NONEON-NOSVE-NEXT:    fcvtzs x9, s0
2386; NONEON-NOSVE-NEXT:    ldr h0, [sp, #56]
2387; NONEON-NOSVE-NEXT:    fcvt s0, h0
2388; NONEON-NOSVE-NEXT:    fcvtzs x8, s0
2389; NONEON-NOSVE-NEXT:    ldr h0, [sp, #62]
2390; NONEON-NOSVE-NEXT:    fcvt s0, h0
2391; NONEON-NOSVE-NEXT:    stp x8, x9, [sp, #160]
2392; NONEON-NOSVE-NEXT:    fcvtzs x9, s0
2393; NONEON-NOSVE-NEXT:    ldr h0, [sp, #60]
2394; NONEON-NOSVE-NEXT:    fcvt s0, h0
2395; NONEON-NOSVE-NEXT:    fcvtzs x8, s0
2396; NONEON-NOSVE-NEXT:    ldr h0, [sp, #50]
2397; NONEON-NOSVE-NEXT:    fcvt s0, h0
2398; NONEON-NOSVE-NEXT:    stp x8, x9, [sp, #176]
2399; NONEON-NOSVE-NEXT:    ldp q6, q7, [sp, #160]
2400; NONEON-NOSVE-NEXT:    fcvtzs x9, s0
2401; NONEON-NOSVE-NEXT:    ldr h0, [sp, #48]
2402; NONEON-NOSVE-NEXT:    fcvt s0, h0
2403; NONEON-NOSVE-NEXT:    fcvtzs x8, s0
2404; NONEON-NOSVE-NEXT:    ldr h0, [sp, #54]
2405; NONEON-NOSVE-NEXT:    fcvt s0, h0
2406; NONEON-NOSVE-NEXT:    stp x8, x9, [sp, #128]
2407; NONEON-NOSVE-NEXT:    fcvtzs x9, s0
2408; NONEON-NOSVE-NEXT:    ldr h0, [sp, #52]
2409; NONEON-NOSVE-NEXT:    fcvt s0, h0
2410; NONEON-NOSVE-NEXT:    fcvtzs x8, s0
2411; NONEON-NOSVE-NEXT:    ldp q0, q1, [sp, #96]
2412; NONEON-NOSVE-NEXT:    stp x8, x9, [sp, #144]
2413; NONEON-NOSVE-NEXT:    ldp q5, q2, [sp, #128]
2414; NONEON-NOSVE-NEXT:    stp q0, q1, [x1]
2415; NONEON-NOSVE-NEXT:    stp q3, q4, [x1, #32]
2416; NONEON-NOSVE-NEXT:    stp q6, q7, [x1, #64]
2417; NONEON-NOSVE-NEXT:    stp q5, q2, [x1, #96]
2418; NONEON-NOSVE-NEXT:    add sp, sp, #192
2419; NONEON-NOSVE-NEXT:    ret
2420  %op1 = load <16 x half>, ptr %a
2421  %res = fptosi <16 x half> %op1 to <16 x i64>
2422  store <16 x i64> %res, ptr %b
2423  ret void
2424}
2425
2426;
2427; FCVTZS S -> H
2428;
2429
2430define <2 x i16> @fcvtzs_v2f32_v2i16(<2 x float> %op1) {
2431; CHECK-LABEL: fcvtzs_v2f32_v2i16:
2432; CHECK:       // %bb.0:
2433; CHECK-NEXT:    ptrue p0.s, vl2
2434; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
2435; CHECK-NEXT:    fcvtzs z0.s, p0/m, z0.s
2436; CHECK-NEXT:    // kill: def $d0 killed $d0 killed $z0
2437; CHECK-NEXT:    ret
2438;
2439; NONEON-NOSVE-LABEL: fcvtzs_v2f32_v2i16:
2440; NONEON-NOSVE:       // %bb.0:
2441; NONEON-NOSVE-NEXT:    str d0, [sp, #-16]!
2442; NONEON-NOSVE-NEXT:    .cfi_def_cfa_offset 16
2443; NONEON-NOSVE-NEXT:    ldp s0, s1, [sp]
2444; NONEON-NOSVE-NEXT:    fcvtzs w9, s1
2445; NONEON-NOSVE-NEXT:    fcvtzs w8, s0
2446; NONEON-NOSVE-NEXT:    stp w8, w9, [sp, #8]
2447; NONEON-NOSVE-NEXT:    ldr d0, [sp, #8]
2448; NONEON-NOSVE-NEXT:    add sp, sp, #16
2449; NONEON-NOSVE-NEXT:    ret
2450  %res = fptosi <2 x float> %op1 to <2 x i16>
2451  ret <2 x i16> %res
2452}
2453
2454define <4 x i16> @fcvtzs_v4f32_v4i16(<4 x float> %op1) {
2455; CHECK-LABEL: fcvtzs_v4f32_v4i16:
2456; CHECK:       // %bb.0:
2457; CHECK-NEXT:    ptrue p0.s, vl4
2458; CHECK-NEXT:    // kill: def $q0 killed $q0 def $z0
2459; CHECK-NEXT:    fcvtzs z0.s, p0/m, z0.s
2460; CHECK-NEXT:    uzp1 z0.h, z0.h, z0.h
2461; CHECK-NEXT:    // kill: def $d0 killed $d0 killed $z0
2462; CHECK-NEXT:    ret
2463;
2464; NONEON-NOSVE-LABEL: fcvtzs_v4f32_v4i16:
2465; NONEON-NOSVE:       // %bb.0:
2466; NONEON-NOSVE-NEXT:    str q0, [sp, #-32]!
2467; NONEON-NOSVE-NEXT:    .cfi_def_cfa_offset 32
2468; NONEON-NOSVE-NEXT:    ldp s0, s1, [sp, #8]
2469; NONEON-NOSVE-NEXT:    fcvtzs w8, s1
2470; NONEON-NOSVE-NEXT:    strh w8, [sp, #30]
2471; NONEON-NOSVE-NEXT:    fcvtzs w8, s0
2472; NONEON-NOSVE-NEXT:    ldp s0, s1, [sp]
2473; NONEON-NOSVE-NEXT:    strh w8, [sp, #28]
2474; NONEON-NOSVE-NEXT:    fcvtzs w8, s1
2475; NONEON-NOSVE-NEXT:    strh w8, [sp, #26]
2476; NONEON-NOSVE-NEXT:    fcvtzs w8, s0
2477; NONEON-NOSVE-NEXT:    strh w8, [sp, #24]
2478; NONEON-NOSVE-NEXT:    ldr d0, [sp, #24]
2479; NONEON-NOSVE-NEXT:    add sp, sp, #32
2480; NONEON-NOSVE-NEXT:    ret
2481  %res = fptosi <4 x float> %op1 to <4 x i16>
2482  ret <4 x i16> %res
2483}
2484
2485define <8 x i16> @fcvtzs_v8f32_v8i16(ptr %a) {
2486; CHECK-LABEL: fcvtzs_v8f32_v8i16:
2487; CHECK:       // %bb.0:
2488; CHECK-NEXT:    ldp q0, q1, [x0]
2489; CHECK-NEXT:    ptrue p0.s, vl4
2490; CHECK-NEXT:    fcvtzs z1.s, p0/m, z1.s
2491; CHECK-NEXT:    fcvtzs z0.s, p0/m, z0.s
2492; CHECK-NEXT:    ptrue p0.h, vl4
2493; CHECK-NEXT:    uzp1 z1.h, z1.h, z1.h
2494; CHECK-NEXT:    uzp1 z0.h, z0.h, z0.h
2495; CHECK-NEXT:    splice z0.h, p0, z0.h, z1.h
2496; CHECK-NEXT:    // kill: def $q0 killed $q0 killed $z0
2497; CHECK-NEXT:    ret
2498;
2499; NONEON-NOSVE-LABEL: fcvtzs_v8f32_v8i16:
2500; NONEON-NOSVE:       // %bb.0:
2501; NONEON-NOSVE-NEXT:    ldp q1, q0, [x0]
2502; NONEON-NOSVE-NEXT:    stp q1, q0, [sp, #-48]!
2503; NONEON-NOSVE-NEXT:    .cfi_def_cfa_offset 48
2504; NONEON-NOSVE-NEXT:    ldp s0, s1, [sp, #24]
2505; NONEON-NOSVE-NEXT:    fcvtzs w8, s1
2506; NONEON-NOSVE-NEXT:    strh w8, [sp, #46]
2507; NONEON-NOSVE-NEXT:    fcvtzs w8, s0
2508; NONEON-NOSVE-NEXT:    ldp s0, s1, [sp, #16]
2509; NONEON-NOSVE-NEXT:    strh w8, [sp, #44]
2510; NONEON-NOSVE-NEXT:    fcvtzs w8, s1
2511; NONEON-NOSVE-NEXT:    strh w8, [sp, #42]
2512; NONEON-NOSVE-NEXT:    fcvtzs w8, s0
2513; NONEON-NOSVE-NEXT:    ldp s0, s1, [sp, #8]
2514; NONEON-NOSVE-NEXT:    strh w8, [sp, #40]
2515; NONEON-NOSVE-NEXT:    fcvtzs w8, s1
2516; NONEON-NOSVE-NEXT:    strh w8, [sp, #38]
2517; NONEON-NOSVE-NEXT:    fcvtzs w8, s0
2518; NONEON-NOSVE-NEXT:    ldp s0, s1, [sp]
2519; NONEON-NOSVE-NEXT:    strh w8, [sp, #36]
2520; NONEON-NOSVE-NEXT:    fcvtzs w8, s1
2521; NONEON-NOSVE-NEXT:    strh w8, [sp, #34]
2522; NONEON-NOSVE-NEXT:    fcvtzs w8, s0
2523; NONEON-NOSVE-NEXT:    strh w8, [sp, #32]
2524; NONEON-NOSVE-NEXT:    ldr q0, [sp, #32]
2525; NONEON-NOSVE-NEXT:    add sp, sp, #48
2526; NONEON-NOSVE-NEXT:    ret
2527  %op1 = load <8 x float>, ptr %a
2528  %res = fptosi <8 x float> %op1 to <8 x i16>
2529  ret <8 x i16> %res
2530}
2531
2532define void @fcvtzs_v16f32_v16i16(ptr %a, ptr %b) {
2533; CHECK-LABEL: fcvtzs_v16f32_v16i16:
2534; CHECK:       // %bb.0:
2535; CHECK-NEXT:    ldp q0, q1, [x0, #32]
2536; CHECK-NEXT:    ptrue p0.s, vl4
2537; CHECK-NEXT:    ldp q2, q3, [x0]
2538; CHECK-NEXT:    fcvtzs z1.s, p0/m, z1.s
2539; CHECK-NEXT:    fcvtzs z0.s, p0/m, z0.s
2540; CHECK-NEXT:    fcvtzs z3.s, p0/m, z3.s
2541; CHECK-NEXT:    fcvtzs z2.s, p0/m, z2.s
2542; CHECK-NEXT:    ptrue p0.h, vl4
2543; CHECK-NEXT:    uzp1 z1.h, z1.h, z1.h
2544; CHECK-NEXT:    uzp1 z0.h, z0.h, z0.h
2545; CHECK-NEXT:    uzp1 z3.h, z3.h, z3.h
2546; CHECK-NEXT:    uzp1 z2.h, z2.h, z2.h
2547; CHECK-NEXT:    splice z0.h, p0, z0.h, z1.h
2548; CHECK-NEXT:    splice z2.h, p0, z2.h, z3.h
2549; CHECK-NEXT:    stp q2, q0, [x1]
2550; CHECK-NEXT:    ret
2551;
2552; NONEON-NOSVE-LABEL: fcvtzs_v16f32_v16i16:
2553; NONEON-NOSVE:       // %bb.0:
2554; NONEON-NOSVE-NEXT:    sub sp, sp, #96
2555; NONEON-NOSVE-NEXT:    .cfi_def_cfa_offset 96
2556; NONEON-NOSVE-NEXT:    ldp q1, q0, [x0]
2557; NONEON-NOSVE-NEXT:    ldp q2, q3, [x0, #32]
2558; NONEON-NOSVE-NEXT:    str q1, [sp]
2559; NONEON-NOSVE-NEXT:    stp q3, q0, [sp, #16]
2560; NONEON-NOSVE-NEXT:    ldp s0, s1, [sp, #40]
2561; NONEON-NOSVE-NEXT:    str q2, [sp, #48]
2562; NONEON-NOSVE-NEXT:    fcvtzs w8, s1
2563; NONEON-NOSVE-NEXT:    strh w8, [sp, #78]
2564; NONEON-NOSVE-NEXT:    fcvtzs w8, s0
2565; NONEON-NOSVE-NEXT:    ldp s0, s1, [sp, #32]
2566; NONEON-NOSVE-NEXT:    strh w8, [sp, #76]
2567; NONEON-NOSVE-NEXT:    fcvtzs w8, s1
2568; NONEON-NOSVE-NEXT:    strh w8, [sp, #74]
2569; NONEON-NOSVE-NEXT:    fcvtzs w8, s0
2570; NONEON-NOSVE-NEXT:    ldp s0, s1, [sp, #8]
2571; NONEON-NOSVE-NEXT:    strh w8, [sp, #72]
2572; NONEON-NOSVE-NEXT:    fcvtzs w8, s1
2573; NONEON-NOSVE-NEXT:    strh w8, [sp, #70]
2574; NONEON-NOSVE-NEXT:    fcvtzs w8, s0
2575; NONEON-NOSVE-NEXT:    ldp s0, s1, [sp]
2576; NONEON-NOSVE-NEXT:    strh w8, [sp, #68]
2577; NONEON-NOSVE-NEXT:    fcvtzs w8, s1
2578; NONEON-NOSVE-NEXT:    strh w8, [sp, #66]
2579; NONEON-NOSVE-NEXT:    fcvtzs w8, s0
2580; NONEON-NOSVE-NEXT:    ldp s0, s1, [sp, #24]
2581; NONEON-NOSVE-NEXT:    strh w8, [sp, #64]
2582; NONEON-NOSVE-NEXT:    fcvtzs w8, s1
2583; NONEON-NOSVE-NEXT:    strh w8, [sp, #94]
2584; NONEON-NOSVE-NEXT:    fcvtzs w8, s0
2585; NONEON-NOSVE-NEXT:    ldp s0, s1, [sp, #16]
2586; NONEON-NOSVE-NEXT:    strh w8, [sp, #92]
2587; NONEON-NOSVE-NEXT:    fcvtzs w8, s1
2588; NONEON-NOSVE-NEXT:    strh w8, [sp, #90]
2589; NONEON-NOSVE-NEXT:    fcvtzs w8, s0
2590; NONEON-NOSVE-NEXT:    ldp s0, s1, [sp, #56]
2591; NONEON-NOSVE-NEXT:    strh w8, [sp, #88]
2592; NONEON-NOSVE-NEXT:    fcvtzs w8, s1
2593; NONEON-NOSVE-NEXT:    strh w8, [sp, #86]
2594; NONEON-NOSVE-NEXT:    fcvtzs w8, s0
2595; NONEON-NOSVE-NEXT:    ldp s0, s1, [sp, #48]
2596; NONEON-NOSVE-NEXT:    strh w8, [sp, #84]
2597; NONEON-NOSVE-NEXT:    fcvtzs w8, s1
2598; NONEON-NOSVE-NEXT:    strh w8, [sp, #82]
2599; NONEON-NOSVE-NEXT:    fcvtzs w8, s0
2600; NONEON-NOSVE-NEXT:    strh w8, [sp, #80]
2601; NONEON-NOSVE-NEXT:    ldp q1, q0, [sp, #64]
2602; NONEON-NOSVE-NEXT:    stp q1, q0, [x1]
2603; NONEON-NOSVE-NEXT:    add sp, sp, #96
2604; NONEON-NOSVE-NEXT:    ret
2605  %op1 = load <16 x float>, ptr %a
2606  %res = fptosi <16 x float> %op1 to <16 x i16>
2607  store <16 x i16> %res, ptr %b
2608  ret void
2609}
2610
2611;
2612; FCVTZS S -> S
2613;
2614
2615define <2 x i32> @fcvtzs_v2f32_v2i32(<2 x float> %op1) {
2616; CHECK-LABEL: fcvtzs_v2f32_v2i32:
2617; CHECK:       // %bb.0:
2618; CHECK-NEXT:    ptrue p0.s, vl2
2619; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
2620; CHECK-NEXT:    fcvtzs z0.s, p0/m, z0.s
2621; CHECK-NEXT:    // kill: def $d0 killed $d0 killed $z0
2622; CHECK-NEXT:    ret
2623;
2624; NONEON-NOSVE-LABEL: fcvtzs_v2f32_v2i32:
2625; NONEON-NOSVE:       // %bb.0:
2626; NONEON-NOSVE-NEXT:    str d0, [sp, #-16]!
2627; NONEON-NOSVE-NEXT:    .cfi_def_cfa_offset 16
2628; NONEON-NOSVE-NEXT:    ldp s0, s1, [sp]
2629; NONEON-NOSVE-NEXT:    fcvtzs w9, s1
2630; NONEON-NOSVE-NEXT:    fcvtzs w8, s0
2631; NONEON-NOSVE-NEXT:    stp w8, w9, [sp, #8]
2632; NONEON-NOSVE-NEXT:    ldr d0, [sp, #8]
2633; NONEON-NOSVE-NEXT:    add sp, sp, #16
2634; NONEON-NOSVE-NEXT:    ret
2635  %res = fptosi <2 x float> %op1 to <2 x i32>
2636  ret <2 x i32> %res
2637}
2638
2639define <4 x i32> @fcvtzs_v4f32_v4i32(<4 x float> %op1) {
2640; CHECK-LABEL: fcvtzs_v4f32_v4i32:
2641; CHECK:       // %bb.0:
2642; CHECK-NEXT:    ptrue p0.s, vl4
2643; CHECK-NEXT:    // kill: def $q0 killed $q0 def $z0
2644; CHECK-NEXT:    fcvtzs z0.s, p0/m, z0.s
2645; CHECK-NEXT:    // kill: def $q0 killed $q0 killed $z0
2646; CHECK-NEXT:    ret
2647;
2648; NONEON-NOSVE-LABEL: fcvtzs_v4f32_v4i32:
2649; NONEON-NOSVE:       // %bb.0:
2650; NONEON-NOSVE-NEXT:    str q0, [sp, #-32]!
2651; NONEON-NOSVE-NEXT:    .cfi_def_cfa_offset 32
2652; NONEON-NOSVE-NEXT:    ldp s0, s1, [sp, #8]
2653; NONEON-NOSVE-NEXT:    fcvtzs w9, s1
2654; NONEON-NOSVE-NEXT:    fcvtzs w8, s0
2655; NONEON-NOSVE-NEXT:    ldp s0, s1, [sp]
2656; NONEON-NOSVE-NEXT:    stp w8, w9, [sp, #24]
2657; NONEON-NOSVE-NEXT:    fcvtzs w9, s1
2658; NONEON-NOSVE-NEXT:    fcvtzs w8, s0
2659; NONEON-NOSVE-NEXT:    stp w8, w9, [sp, #16]
2660; NONEON-NOSVE-NEXT:    ldr q0, [sp, #16]
2661; NONEON-NOSVE-NEXT:    add sp, sp, #32
2662; NONEON-NOSVE-NEXT:    ret
2663  %res = fptosi <4 x float> %op1 to <4 x i32>
2664  ret <4 x i32> %res
2665}
2666
2667define void @fcvtzs_v8f32_v8i32(ptr %a, ptr %b) {
2668; CHECK-LABEL: fcvtzs_v8f32_v8i32:
2669; CHECK:       // %bb.0:
2670; CHECK-NEXT:    ldp q0, q1, [x0]
2671; CHECK-NEXT:    ptrue p0.s, vl4
2672; CHECK-NEXT:    fcvtzs z0.s, p0/m, z0.s
2673; CHECK-NEXT:    fcvtzs z1.s, p0/m, z1.s
2674; CHECK-NEXT:    stp q0, q1, [x1]
2675; CHECK-NEXT:    ret
2676;
2677; NONEON-NOSVE-LABEL: fcvtzs_v8f32_v8i32:
2678; NONEON-NOSVE:       // %bb.0:
2679; NONEON-NOSVE-NEXT:    ldp q1, q0, [x0]
2680; NONEON-NOSVE-NEXT:    stp q1, q0, [sp, #-64]!
2681; NONEON-NOSVE-NEXT:    .cfi_def_cfa_offset 64
2682; NONEON-NOSVE-NEXT:    ldp s0, s1, [sp, #24]
2683; NONEON-NOSVE-NEXT:    fcvtzs w9, s1
2684; NONEON-NOSVE-NEXT:    fcvtzs w8, s0
2685; NONEON-NOSVE-NEXT:    ldp s0, s1, [sp, #16]
2686; NONEON-NOSVE-NEXT:    stp w8, w9, [sp, #56]
2687; NONEON-NOSVE-NEXT:    fcvtzs w9, s1
2688; NONEON-NOSVE-NEXT:    fcvtzs w8, s0
2689; NONEON-NOSVE-NEXT:    ldp s0, s1, [sp, #8]
2690; NONEON-NOSVE-NEXT:    stp w8, w9, [sp, #48]
2691; NONEON-NOSVE-NEXT:    fcvtzs w9, s1
2692; NONEON-NOSVE-NEXT:    fcvtzs w8, s0
2693; NONEON-NOSVE-NEXT:    ldp s0, s1, [sp]
2694; NONEON-NOSVE-NEXT:    stp w8, w9, [sp, #40]
2695; NONEON-NOSVE-NEXT:    fcvtzs w9, s1
2696; NONEON-NOSVE-NEXT:    fcvtzs w8, s0
2697; NONEON-NOSVE-NEXT:    stp w8, w9, [sp, #32]
2698; NONEON-NOSVE-NEXT:    ldp q0, q1, [sp, #32]
2699; NONEON-NOSVE-NEXT:    stp q0, q1, [x1]
2700; NONEON-NOSVE-NEXT:    add sp, sp, #64
2701; NONEON-NOSVE-NEXT:    ret
2702  %op1 = load <8 x float>, ptr %a
2703  %res = fptosi <8 x float> %op1 to <8 x i32>
2704  store <8 x i32> %res, ptr %b
2705  ret void
2706}
2707
2708;
2709; FCVTZS S -> D
2710;
2711
2712define <1 x i64> @fcvtzs_v1f32_v1i64(<1 x float> %op1) {
2713; CHECK-LABEL: fcvtzs_v1f32_v1i64:
2714; CHECK:       // %bb.0:
2715; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
2716; CHECK-NEXT:    ptrue p0.d, vl2
2717; CHECK-NEXT:    uunpklo z0.d, z0.s
2718; CHECK-NEXT:    fcvtzs z0.d, p0/m, z0.s
2719; CHECK-NEXT:    // kill: def $d0 killed $d0 killed $z0
2720; CHECK-NEXT:    ret
2721;
2722; NONEON-NOSVE-LABEL: fcvtzs_v1f32_v1i64:
2723; NONEON-NOSVE:       // %bb.0:
2724; NONEON-NOSVE-NEXT:    sub sp, sp, #16
2725; NONEON-NOSVE-NEXT:    .cfi_def_cfa_offset 16
2726; NONEON-NOSVE-NEXT:    str d0, [sp, #8]
2727; NONEON-NOSVE-NEXT:    ldr s0, [sp, #8]
2728; NONEON-NOSVE-NEXT:    fcvtzs x8, s0
2729; NONEON-NOSVE-NEXT:    fmov d0, x8
2730; NONEON-NOSVE-NEXT:    add sp, sp, #16
2731; NONEON-NOSVE-NEXT:    ret
2732  %res = fptosi <1 x float> %op1 to <1 x i64>
2733  ret <1 x i64> %res
2734}
2735
2736define <2 x i64> @fcvtzs_v2f32_v2i64(<2 x float> %op1) {
2737; CHECK-LABEL: fcvtzs_v2f32_v2i64:
2738; CHECK:       // %bb.0:
2739; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
2740; CHECK-NEXT:    ptrue p0.d, vl2
2741; CHECK-NEXT:    uunpklo z0.d, z0.s
2742; CHECK-NEXT:    fcvtzs z0.d, p0/m, z0.s
2743; CHECK-NEXT:    // kill: def $q0 killed $q0 killed $z0
2744; CHECK-NEXT:    ret
2745;
2746; NONEON-NOSVE-LABEL: fcvtzs_v2f32_v2i64:
2747; NONEON-NOSVE:       // %bb.0:
2748; NONEON-NOSVE-NEXT:    sub sp, sp, #32
2749; NONEON-NOSVE-NEXT:    .cfi_def_cfa_offset 32
2750; NONEON-NOSVE-NEXT:    str d0, [sp, #8]
2751; NONEON-NOSVE-NEXT:    ldp s0, s1, [sp, #8]
2752; NONEON-NOSVE-NEXT:    fcvtzs x9, s1
2753; NONEON-NOSVE-NEXT:    fcvtzs x8, s0
2754; NONEON-NOSVE-NEXT:    stp x8, x9, [sp, #16]
2755; NONEON-NOSVE-NEXT:    ldr q0, [sp, #16]
2756; NONEON-NOSVE-NEXT:    add sp, sp, #32
2757; NONEON-NOSVE-NEXT:    ret
2758  %res = fptosi <2 x float> %op1 to <2 x i64>
2759  ret <2 x i64> %res
2760}
2761
2762define void @fcvtzs_v4f32_v4i64(ptr %a, ptr %b) {
2763; CHECK-LABEL: fcvtzs_v4f32_v4i64:
2764; CHECK:       // %bb.0:
2765; CHECK-NEXT:    ldr q0, [x0]
2766; CHECK-NEXT:    ptrue p0.d, vl2
2767; CHECK-NEXT:    uunpklo z1.d, z0.s
2768; CHECK-NEXT:    ext z0.b, z0.b, z0.b, #8
2769; CHECK-NEXT:    uunpklo z0.d, z0.s
2770; CHECK-NEXT:    fcvtzs z1.d, p0/m, z1.s
2771; CHECK-NEXT:    fcvtzs z0.d, p0/m, z0.s
2772; CHECK-NEXT:    stp q1, q0, [x1]
2773; CHECK-NEXT:    ret
2774;
2775; NONEON-NOSVE-LABEL: fcvtzs_v4f32_v4i64:
2776; NONEON-NOSVE:       // %bb.0:
2777; NONEON-NOSVE-NEXT:    ldr q0, [x0]
2778; NONEON-NOSVE-NEXT:    str q0, [sp, #-64]!
2779; NONEON-NOSVE-NEXT:    .cfi_def_cfa_offset 64
2780; NONEON-NOSVE-NEXT:    ldp d1, d0, [sp]
2781; NONEON-NOSVE-NEXT:    stp d0, d1, [sp, #16]
2782; NONEON-NOSVE-NEXT:    ldp s0, s1, [sp, #24]
2783; NONEON-NOSVE-NEXT:    fcvtzs x9, s1
2784; NONEON-NOSVE-NEXT:    fcvtzs x8, s0
2785; NONEON-NOSVE-NEXT:    ldp s0, s1, [sp, #16]
2786; NONEON-NOSVE-NEXT:    stp x8, x9, [sp, #48]
2787; NONEON-NOSVE-NEXT:    fcvtzs x9, s1
2788; NONEON-NOSVE-NEXT:    fcvtzs x8, s0
2789; NONEON-NOSVE-NEXT:    stp x8, x9, [sp, #32]
2790; NONEON-NOSVE-NEXT:    ldp q0, q1, [sp, #32]
2791; NONEON-NOSVE-NEXT:    stp q1, q0, [x1]
2792; NONEON-NOSVE-NEXT:    add sp, sp, #64
2793; NONEON-NOSVE-NEXT:    ret
2794  %op1 = load <4 x float>, ptr %a
2795  %res = fptosi <4 x float> %op1 to <4 x i64>
2796  store <4 x i64> %res, ptr %b
2797  ret void
2798}
2799
2800define void @fcvtzs_v8f32_v8i64(ptr %a, ptr %b) {
2801; CHECK-LABEL: fcvtzs_v8f32_v8i64:
2802; CHECK:       // %bb.0:
2803; CHECK-NEXT:    ldp q1, q0, [x0]
2804; CHECK-NEXT:    ptrue p0.d, vl2
2805; CHECK-NEXT:    uunpklo z2.d, z0.s
2806; CHECK-NEXT:    ext z0.b, z0.b, z0.b, #8
2807; CHECK-NEXT:    uunpklo z3.d, z1.s
2808; CHECK-NEXT:    ext z1.b, z1.b, z1.b, #8
2809; CHECK-NEXT:    uunpklo z0.d, z0.s
2810; CHECK-NEXT:    uunpklo z1.d, z1.s
2811; CHECK-NEXT:    fcvtzs z2.d, p0/m, z2.s
2812; CHECK-NEXT:    fcvtzs z3.d, p0/m, z3.s
2813; CHECK-NEXT:    fcvtzs z0.d, p0/m, z0.s
2814; CHECK-NEXT:    fcvtzs z1.d, p0/m, z1.s
2815; CHECK-NEXT:    stp q2, q0, [x1, #32]
2816; CHECK-NEXT:    stp q3, q1, [x1]
2817; CHECK-NEXT:    ret
2818;
2819; NONEON-NOSVE-LABEL: fcvtzs_v8f32_v8i64:
2820; NONEON-NOSVE:       // %bb.0:
2821; NONEON-NOSVE-NEXT:    ldp q0, q1, [x0]
2822; NONEON-NOSVE-NEXT:    stp q0, q1, [sp, #-128]!
2823; NONEON-NOSVE-NEXT:    .cfi_def_cfa_offset 128
2824; NONEON-NOSVE-NEXT:    ldp d1, d0, [sp]
2825; NONEON-NOSVE-NEXT:    stp d0, d1, [sp, #32]
2826; NONEON-NOSVE-NEXT:    ldp d1, d0, [sp, #16]
2827; NONEON-NOSVE-NEXT:    stp d0, d1, [sp, #48]
2828; NONEON-NOSVE-NEXT:    ldp s0, s1, [sp, #40]
2829; NONEON-NOSVE-NEXT:    fcvtzs x9, s1
2830; NONEON-NOSVE-NEXT:    fcvtzs x8, s0
2831; NONEON-NOSVE-NEXT:    ldp s0, s1, [sp, #32]
2832; NONEON-NOSVE-NEXT:    stp x8, x9, [sp, #80]
2833; NONEON-NOSVE-NEXT:    fcvtzs x9, s1
2834; NONEON-NOSVE-NEXT:    fcvtzs x8, s0
2835; NONEON-NOSVE-NEXT:    ldp s0, s1, [sp, #56]
2836; NONEON-NOSVE-NEXT:    stp x8, x9, [sp, #64]
2837; NONEON-NOSVE-NEXT:    fcvtzs x9, s1
2838; NONEON-NOSVE-NEXT:    fcvtzs x8, s0
2839; NONEON-NOSVE-NEXT:    ldp s0, s1, [sp, #48]
2840; NONEON-NOSVE-NEXT:    ldp q3, q2, [sp, #64]
2841; NONEON-NOSVE-NEXT:    stp x8, x9, [sp, #112]
2842; NONEON-NOSVE-NEXT:    fcvtzs x9, s1
2843; NONEON-NOSVE-NEXT:    fcvtzs x8, s0
2844; NONEON-NOSVE-NEXT:    stp x8, x9, [sp, #96]
2845; NONEON-NOSVE-NEXT:    ldp q0, q1, [sp, #96]
2846; NONEON-NOSVE-NEXT:    stp q2, q3, [x1]
2847; NONEON-NOSVE-NEXT:    stp q1, q0, [x1, #32]
2848; NONEON-NOSVE-NEXT:    add sp, sp, #128
2849; NONEON-NOSVE-NEXT:    ret
2850  %op1 = load <8 x float>, ptr %a
2851  %res = fptosi <8 x float> %op1 to <8 x i64>
2852  store <8 x i64> %res, ptr %b
2853  ret void
2854}
2855
2856
2857;
2858; FCVTZS D -> H
2859;
2860
2861; v1f64 is perfered to be widened to v4f64, so use SVE
2862define <1 x i16> @fcvtzs_v1f64_v1i16(<1 x double> %op1) {
2863; CHECK-LABEL: fcvtzs_v1f64_v1i16:
2864; CHECK:       // %bb.0:
2865; CHECK-NEXT:    fcvtzs w8, d0
2866; CHECK-NEXT:    mov z0.h, w8
2867; CHECK-NEXT:    // kill: def $d0 killed $d0 killed $z0
2868; CHECK-NEXT:    ret
2869;
2870; NONEON-NOSVE-LABEL: fcvtzs_v1f64_v1i16:
2871; NONEON-NOSVE:       // %bb.0:
2872; NONEON-NOSVE-NEXT:    sub sp, sp, #16
2873; NONEON-NOSVE-NEXT:    .cfi_def_cfa_offset 16
2874; NONEON-NOSVE-NEXT:    fcvtzs w8, d0
2875; NONEON-NOSVE-NEXT:    strh w8, [sp, #8]
2876; NONEON-NOSVE-NEXT:    ldr d0, [sp, #8]
2877; NONEON-NOSVE-NEXT:    add sp, sp, #16
2878; NONEON-NOSVE-NEXT:    ret
2879  %res = fptosi <1 x double> %op1 to <1 x i16>
2880  ret <1 x i16> %res
2881}
2882
2883define <2 x i16> @fcvtzs_v2f64_v2i16(<2 x double> %op1) {
2884; CHECK-LABEL: fcvtzs_v2f64_v2i16:
2885; CHECK:       // %bb.0:
2886; CHECK-NEXT:    ptrue p0.d, vl2
2887; CHECK-NEXT:    // kill: def $q0 killed $q0 def $z0
2888; CHECK-NEXT:    fcvtzs z0.d, p0/m, z0.d
2889; CHECK-NEXT:    uzp1 z0.s, z0.s, z0.s
2890; CHECK-NEXT:    // kill: def $d0 killed $d0 killed $z0
2891; CHECK-NEXT:    ret
2892;
2893; NONEON-NOSVE-LABEL: fcvtzs_v2f64_v2i16:
2894; NONEON-NOSVE:       // %bb.0:
2895; NONEON-NOSVE-NEXT:    str q0, [sp, #-32]!
2896; NONEON-NOSVE-NEXT:    .cfi_def_cfa_offset 32
2897; NONEON-NOSVE-NEXT:    ldp d0, d1, [sp]
2898; NONEON-NOSVE-NEXT:    fcvtzs w9, d1
2899; NONEON-NOSVE-NEXT:    fcvtzs w8, d0
2900; NONEON-NOSVE-NEXT:    stp w8, w9, [sp, #24]
2901; NONEON-NOSVE-NEXT:    ldr d0, [sp, #24]
2902; NONEON-NOSVE-NEXT:    add sp, sp, #32
2903; NONEON-NOSVE-NEXT:    ret
2904  %res = fptosi <2 x double> %op1 to <2 x i16>
2905  ret <2 x i16> %res
2906}
2907
2908define <4 x i16> @fcvtzs_v4f64_v4i16(ptr %a) {
2909; CHECK-LABEL: fcvtzs_v4f64_v4i16:
2910; CHECK:       // %bb.0:
2911; CHECK-NEXT:    ldp q0, q1, [x0]
2912; CHECK-NEXT:    ptrue p0.d, vl2
2913; CHECK-NEXT:    fcvtzs z1.d, p0/m, z1.d
2914; CHECK-NEXT:    fcvtzs z0.d, p0/m, z0.d
2915; CHECK-NEXT:    uzp1 z1.s, z1.s, z1.s
2916; CHECK-NEXT:    uzp1 z0.s, z0.s, z0.s
2917; CHECK-NEXT:    mov z2.s, z1.s[1]
2918; CHECK-NEXT:    mov z3.s, z0.s[1]
2919; CHECK-NEXT:    zip1 z1.h, z1.h, z2.h
2920; CHECK-NEXT:    zip1 z0.h, z0.h, z3.h
2921; CHECK-NEXT:    zip1 z0.s, z0.s, z1.s
2922; CHECK-NEXT:    // kill: def $d0 killed $d0 killed $z0
2923; CHECK-NEXT:    ret
2924;
2925; NONEON-NOSVE-LABEL: fcvtzs_v4f64_v4i16:
2926; NONEON-NOSVE:       // %bb.0:
2927; NONEON-NOSVE-NEXT:    ldp q1, q0, [x0]
2928; NONEON-NOSVE-NEXT:    stp q1, q0, [sp, #-80]!
2929; NONEON-NOSVE-NEXT:    .cfi_def_cfa_offset 80
2930; NONEON-NOSVE-NEXT:    ldp d0, d1, [sp, #16]
2931; NONEON-NOSVE-NEXT:    fcvtzs w9, d1
2932; NONEON-NOSVE-NEXT:    fcvtzs w8, d0
2933; NONEON-NOSVE-NEXT:    ldp d0, d1, [sp]
2934; NONEON-NOSVE-NEXT:    stp w8, w9, [sp, #48]
2935; NONEON-NOSVE-NEXT:    fcvtzs w9, d1
2936; NONEON-NOSVE-NEXT:    fcvtzs w8, d0
2937; NONEON-NOSVE-NEXT:    stp w8, w9, [sp, #40]
2938; NONEON-NOSVE-NEXT:    ldp d0, d1, [sp, #40]
2939; NONEON-NOSVE-NEXT:    stp d0, d1, [sp, #56]
2940; NONEON-NOSVE-NEXT:    ldp w8, w9, [sp, #64]
2941; NONEON-NOSVE-NEXT:    strh w9, [sp, #78]
2942; NONEON-NOSVE-NEXT:    strh w8, [sp, #76]
2943; NONEON-NOSVE-NEXT:    ldp w8, w9, [sp, #56]
2944; NONEON-NOSVE-NEXT:    strh w9, [sp, #74]
2945; NONEON-NOSVE-NEXT:    strh w8, [sp, #72]
2946; NONEON-NOSVE-NEXT:    ldr d0, [sp, #72]
2947; NONEON-NOSVE-NEXT:    add sp, sp, #80
2948; NONEON-NOSVE-NEXT:    ret
2949  %op1 = load <4 x double>, ptr %a
2950  %res = fptosi <4 x double> %op1 to <4 x i16>
2951  ret <4 x i16> %res
2952}
2953
2954define <8 x i16> @fcvtzs_v8f64_v8i16(ptr %a) {
2955; CHECK-LABEL: fcvtzs_v8f64_v8i16:
2956; CHECK:       // %bb.0:
2957; CHECK-NEXT:    ldp q1, q0, [x0, #32]
2958; CHECK-NEXT:    ptrue p0.d, vl2
2959; CHECK-NEXT:    ldp q2, q3, [x0]
2960; CHECK-NEXT:    fcvtzs z0.d, p0/m, z0.d
2961; CHECK-NEXT:    fcvtzs z1.d, p0/m, z1.d
2962; CHECK-NEXT:    fcvtzs z3.d, p0/m, z3.d
2963; CHECK-NEXT:    fcvtzs z2.d, p0/m, z2.d
2964; CHECK-NEXT:    uzp1 z0.s, z0.s, z0.s
2965; CHECK-NEXT:    uzp1 z1.s, z1.s, z1.s
2966; CHECK-NEXT:    uzp1 z3.s, z3.s, z3.s
2967; CHECK-NEXT:    uzp1 z2.s, z2.s, z2.s
2968; CHECK-NEXT:    mov z4.s, z0.s[1]
2969; CHECK-NEXT:    mov z5.s, z1.s[1]
2970; CHECK-NEXT:    mov z6.s, z3.s[1]
2971; CHECK-NEXT:    mov z7.s, z2.s[1]
2972; CHECK-NEXT:    zip1 z0.h, z0.h, z4.h
2973; CHECK-NEXT:    zip1 z1.h, z1.h, z5.h
2974; CHECK-NEXT:    zip1 z3.h, z3.h, z6.h
2975; CHECK-NEXT:    zip1 z2.h, z2.h, z7.h
2976; CHECK-NEXT:    zip1 z0.s, z1.s, z0.s
2977; CHECK-NEXT:    zip1 z1.s, z2.s, z3.s
2978; CHECK-NEXT:    zip1 z0.d, z1.d, z0.d
2979; CHECK-NEXT:    // kill: def $q0 killed $q0 killed $z0
2980; CHECK-NEXT:    ret
2981;
2982; NONEON-NOSVE-LABEL: fcvtzs_v8f64_v8i16:
2983; NONEON-NOSVE:       // %bb.0:
2984; NONEON-NOSVE-NEXT:    sub sp, sp, #144
2985; NONEON-NOSVE-NEXT:    .cfi_def_cfa_offset 144
2986; NONEON-NOSVE-NEXT:    ldp q1, q0, [x0, #32]
2987; NONEON-NOSVE-NEXT:    ldp q2, q3, [x0]
2988; NONEON-NOSVE-NEXT:    str q1, [sp, #48]
2989; NONEON-NOSVE-NEXT:    stp q0, q3, [sp, #16]
2990; NONEON-NOSVE-NEXT:    ldp d0, d1, [sp, #16]
2991; NONEON-NOSVE-NEXT:    str q2, [sp]
2992; NONEON-NOSVE-NEXT:    fcvtzs w9, d1
2993; NONEON-NOSVE-NEXT:    fcvtzs w8, d0
2994; NONEON-NOSVE-NEXT:    ldp d0, d1, [sp, #48]
2995; NONEON-NOSVE-NEXT:    stp w8, w9, [sp, #72]
2996; NONEON-NOSVE-NEXT:    fcvtzs w9, d1
2997; NONEON-NOSVE-NEXT:    fcvtzs w8, d0
2998; NONEON-NOSVE-NEXT:    ldp d0, d1, [sp, #32]
2999; NONEON-NOSVE-NEXT:    stp w8, w9, [sp, #88]
3000; NONEON-NOSVE-NEXT:    fcvtzs w9, d1
3001; NONEON-NOSVE-NEXT:    fcvtzs w8, d0
3002; NONEON-NOSVE-NEXT:    ldp d0, d1, [sp]
3003; NONEON-NOSVE-NEXT:    stp w8, w9, [sp, #80]
3004; NONEON-NOSVE-NEXT:    fcvtzs w9, d1
3005; NONEON-NOSVE-NEXT:    fcvtzs w8, d0
3006; NONEON-NOSVE-NEXT:    ldp d0, d2, [sp, #80]
3007; NONEON-NOSVE-NEXT:    ldr d1, [sp, #72]
3008; NONEON-NOSVE-NEXT:    stp d1, d0, [sp, #104]
3009; NONEON-NOSVE-NEXT:    stp w8, w9, [sp, #64]
3010; NONEON-NOSVE-NEXT:    ldp w8, w9, [sp, #104]
3011; NONEON-NOSVE-NEXT:    str d2, [sp, #120]
3012; NONEON-NOSVE-NEXT:    ldr d0, [sp, #64]
3013; NONEON-NOSVE-NEXT:    strh w9, [sp, #142]
3014; NONEON-NOSVE-NEXT:    strh w8, [sp, #140]
3015; NONEON-NOSVE-NEXT:    ldp w8, w9, [sp, #120]
3016; NONEON-NOSVE-NEXT:    str d0, [sp, #96]
3017; NONEON-NOSVE-NEXT:    strh w9, [sp, #138]
3018; NONEON-NOSVE-NEXT:    strh w8, [sp, #136]
3019; NONEON-NOSVE-NEXT:    ldp w8, w9, [sp, #112]
3020; NONEON-NOSVE-NEXT:    strh w9, [sp, #134]
3021; NONEON-NOSVE-NEXT:    strh w8, [sp, #132]
3022; NONEON-NOSVE-NEXT:    ldp w8, w9, [sp, #96]
3023; NONEON-NOSVE-NEXT:    strh w9, [sp, #130]
3024; NONEON-NOSVE-NEXT:    strh w8, [sp, #128]
3025; NONEON-NOSVE-NEXT:    ldr q0, [sp, #128]
3026; NONEON-NOSVE-NEXT:    add sp, sp, #144
3027; NONEON-NOSVE-NEXT:    ret
3028  %op1 = load <8 x double>, ptr %a
3029  %res = fptosi <8 x double> %op1 to <8 x i16>
3030  ret <8 x i16> %res
3031}
3032
3033define void @fcvtzs_v16f64_v16i16(ptr %a, ptr %b) {
3034; CHECK-LABEL: fcvtzs_v16f64_v16i16:
3035; CHECK:       // %bb.0:
3036; CHECK-NEXT:    ldp q5, q6, [x0, #96]
3037; CHECK-NEXT:    ptrue p0.d, vl2
3038; CHECK-NEXT:    ldp q0, q4, [x0, #32]
3039; CHECK-NEXT:    ldp q2, q7, [x0, #64]
3040; CHECK-NEXT:    ldp q1, q3, [x0]
3041; CHECK-NEXT:    fcvtzs z6.d, p0/m, z6.d
3042; CHECK-NEXT:    fcvtzs z4.d, p0/m, z4.d
3043; CHECK-NEXT:    fcvtzs z5.d, p0/m, z5.d
3044; CHECK-NEXT:    fcvtzs z0.d, p0/m, z0.d
3045; CHECK-NEXT:    fcvtzs z7.d, p0/m, z7.d
3046; CHECK-NEXT:    fcvtzs z2.d, p0/m, z2.d
3047; CHECK-NEXT:    fcvtzs z3.d, p0/m, z3.d
3048; CHECK-NEXT:    fcvtzs z1.d, p0/m, z1.d
3049; CHECK-NEXT:    uzp1 z6.s, z6.s, z6.s
3050; CHECK-NEXT:    uzp1 z4.s, z4.s, z4.s
3051; CHECK-NEXT:    uzp1 z5.s, z5.s, z5.s
3052; CHECK-NEXT:    uzp1 z0.s, z0.s, z0.s
3053; CHECK-NEXT:    uzp1 z7.s, z7.s, z7.s
3054; CHECK-NEXT:    uzp1 z2.s, z2.s, z2.s
3055; CHECK-NEXT:    uzp1 z3.s, z3.s, z3.s
3056; CHECK-NEXT:    uzp1 z1.s, z1.s, z1.s
3057; CHECK-NEXT:    mov z17.s, z6.s[1]
3058; CHECK-NEXT:    mov z16.s, z4.s[1]
3059; CHECK-NEXT:    mov z18.s, z5.s[1]
3060; CHECK-NEXT:    mov z21.s, z0.s[1]
3061; CHECK-NEXT:    mov z19.s, z7.s[1]
3062; CHECK-NEXT:    mov z20.s, z2.s[1]
3063; CHECK-NEXT:    mov z22.s, z3.s[1]
3064; CHECK-NEXT:    mov z23.s, z1.s[1]
3065; CHECK-NEXT:    zip1 z6.h, z6.h, z17.h
3066; CHECK-NEXT:    zip1 z4.h, z4.h, z16.h
3067; CHECK-NEXT:    zip1 z5.h, z5.h, z18.h
3068; CHECK-NEXT:    zip1 z0.h, z0.h, z21.h
3069; CHECK-NEXT:    zip1 z7.h, z7.h, z19.h
3070; CHECK-NEXT:    zip1 z2.h, z2.h, z20.h
3071; CHECK-NEXT:    zip1 z3.h, z3.h, z22.h
3072; CHECK-NEXT:    zip1 z1.h, z1.h, z23.h
3073; CHECK-NEXT:    zip1 z5.s, z5.s, z6.s
3074; CHECK-NEXT:    zip1 z0.s, z0.s, z4.s
3075; CHECK-NEXT:    zip1 z2.s, z2.s, z7.s
3076; CHECK-NEXT:    zip1 z1.s, z1.s, z3.s
3077; CHECK-NEXT:    zip1 z2.d, z2.d, z5.d
3078; CHECK-NEXT:    zip1 z0.d, z1.d, z0.d
3079; CHECK-NEXT:    stp q0, q2, [x1]
3080; CHECK-NEXT:    ret
3081;
3082; NONEON-NOSVE-LABEL: fcvtzs_v16f64_v16i16:
3083; NONEON-NOSVE:       // %bb.0:
3084; NONEON-NOSVE-NEXT:    sub sp, sp, #304
3085; NONEON-NOSVE-NEXT:    str x29, [sp, #288] // 8-byte Folded Spill
3086; NONEON-NOSVE-NEXT:    .cfi_def_cfa_offset 304
3087; NONEON-NOSVE-NEXT:    .cfi_offset w29, -16
3088; NONEON-NOSVE-NEXT:    ldp q0, q1, [x0, #32]
3089; NONEON-NOSVE-NEXT:    ldr x29, [sp, #288] // 8-byte Folded Reload
3090; NONEON-NOSVE-NEXT:    ldp q6, q7, [x0]
3091; NONEON-NOSVE-NEXT:    ldp q2, q3, [x0, #64]
3092; NONEON-NOSVE-NEXT:    ldp q4, q5, [x0, #96]
3093; NONEON-NOSVE-NEXT:    stp q1, q7, [sp, #64]
3094; NONEON-NOSVE-NEXT:    stp q0, q2, [sp, #96]
3095; NONEON-NOSVE-NEXT:    ldp d0, d1, [sp, #64]
3096; NONEON-NOSVE-NEXT:    stp q6, q4, [sp]
3097; NONEON-NOSVE-NEXT:    stp q5, q3, [sp, #32]
3098; NONEON-NOSVE-NEXT:    fcvtzs w9, d1
3099; NONEON-NOSVE-NEXT:    fcvtzs w8, d0
3100; NONEON-NOSVE-NEXT:    ldp d0, d1, [sp, #96]
3101; NONEON-NOSVE-NEXT:    stp w8, w9, [sp, #168]
3102; NONEON-NOSVE-NEXT:    fcvtzs w9, d1
3103; NONEON-NOSVE-NEXT:    fcvtzs w8, d0
3104; NONEON-NOSVE-NEXT:    ldp d0, d1, [sp, #80]
3105; NONEON-NOSVE-NEXT:    stp w8, w9, [sp, #184]
3106; NONEON-NOSVE-NEXT:    fcvtzs w9, d1
3107; NONEON-NOSVE-NEXT:    fcvtzs w8, d0
3108; NONEON-NOSVE-NEXT:    ldp d0, d1, [sp]
3109; NONEON-NOSVE-NEXT:    stp w8, w9, [sp, #176]
3110; NONEON-NOSVE-NEXT:    fcvtzs w9, d1
3111; NONEON-NOSVE-NEXT:    fcvtzs w8, d0
3112; NONEON-NOSVE-NEXT:    ldp d0, d1, [sp, #32]
3113; NONEON-NOSVE-NEXT:    stp w8, w9, [sp, #136]
3114; NONEON-NOSVE-NEXT:    fcvtzs w9, d1
3115; NONEON-NOSVE-NEXT:    fcvtzs w8, d0
3116; NONEON-NOSVE-NEXT:    ldp d0, d1, [sp, #16]
3117; NONEON-NOSVE-NEXT:    stp w8, w9, [sp, #152]
3118; NONEON-NOSVE-NEXT:    fcvtzs w9, d1
3119; NONEON-NOSVE-NEXT:    fcvtzs w8, d0
3120; NONEON-NOSVE-NEXT:    ldp d0, d1, [sp, #48]
3121; NONEON-NOSVE-NEXT:    stp w8, w9, [sp, #144]
3122; NONEON-NOSVE-NEXT:    fcvtzs w9, d1
3123; NONEON-NOSVE-NEXT:    fcvtzs w8, d0
3124; NONEON-NOSVE-NEXT:    ldp d0, d1, [sp, #112]
3125; NONEON-NOSVE-NEXT:    stp w8, w9, [sp, #160]
3126; NONEON-NOSVE-NEXT:    fcvtzs w9, d1
3127; NONEON-NOSVE-NEXT:    fcvtzs w8, d0
3128; NONEON-NOSVE-NEXT:    ldp d0, d2, [sp, #176]
3129; NONEON-NOSVE-NEXT:    ldr d1, [sp, #168]
3130; NONEON-NOSVE-NEXT:    stp d1, d0, [sp, #232]
3131; NONEON-NOSVE-NEXT:    ldr d1, [sp, #136]
3132; NONEON-NOSVE-NEXT:    stp w8, w9, [sp, #192]
3133; NONEON-NOSVE-NEXT:    ldp w8, w9, [sp, #232]
3134; NONEON-NOSVE-NEXT:    str d2, [sp, #248]
3135; NONEON-NOSVE-NEXT:    ldp d0, d2, [sp, #144]
3136; NONEON-NOSVE-NEXT:    strh w9, [sp, #270]
3137; NONEON-NOSVE-NEXT:    strh w8, [sp, #268]
3138; NONEON-NOSVE-NEXT:    ldp w8, w9, [sp, #248]
3139; NONEON-NOSVE-NEXT:    stp d1, d0, [sp, #200]
3140; NONEON-NOSVE-NEXT:    ldr d0, [sp, #160]
3141; NONEON-NOSVE-NEXT:    strh w9, [sp, #266]
3142; NONEON-NOSVE-NEXT:    strh w8, [sp, #264]
3143; NONEON-NOSVE-NEXT:    ldp w8, w9, [sp, #240]
3144; NONEON-NOSVE-NEXT:    stp d2, d0, [sp, #216]
3145; NONEON-NOSVE-NEXT:    ldr d0, [sp, #192]
3146; NONEON-NOSVE-NEXT:    strh w9, [sp, #262]
3147; NONEON-NOSVE-NEXT:    strh w8, [sp, #260]
3148; NONEON-NOSVE-NEXT:    ldp w8, w9, [sp, #200]
3149; NONEON-NOSVE-NEXT:    str d0, [sp, #296]
3150; NONEON-NOSVE-NEXT:    strh w9, [sp, #258]
3151; NONEON-NOSVE-NEXT:    strh w8, [sp, #256]
3152; NONEON-NOSVE-NEXT:    ldp w8, w9, [sp, #216]
3153; NONEON-NOSVE-NEXT:    strh w9, [sp, #286]
3154; NONEON-NOSVE-NEXT:    strh w8, [sp, #284]
3155; NONEON-NOSVE-NEXT:    ldp w8, w9, [sp, #208]
3156; NONEON-NOSVE-NEXT:    strh w9, [sp, #282]
3157; NONEON-NOSVE-NEXT:    strh w8, [sp, #280]
3158; NONEON-NOSVE-NEXT:    ldp w8, w9, [sp, #224]
3159; NONEON-NOSVE-NEXT:    strh w8, [sp, #276]
3160; NONEON-NOSVE-NEXT:    ldr w8, [sp, #300]
3161; NONEON-NOSVE-NEXT:    strh w9, [sp, #278]
3162; NONEON-NOSVE-NEXT:    strh w8, [sp, #274]
3163; NONEON-NOSVE-NEXT:    ldr w8, [sp, #296]
3164; NONEON-NOSVE-NEXT:    strh w8, [sp, #272]
3165; NONEON-NOSVE-NEXT:    ldp q1, q0, [sp, #256]
3166; NONEON-NOSVE-NEXT:    stp q1, q0, [x1]
3167; NONEON-NOSVE-NEXT:    add sp, sp, #304
3168; NONEON-NOSVE-NEXT:    ret
3169  %op1 = load <16 x double>, ptr %a
3170  %res = fptosi <16 x double> %op1 to <16 x i16>
3171  store <16 x i16> %res, ptr %b
3172  ret void
3173}
3174
3175;
3176; FCVTZS D -> S
3177;
3178
3179define <1 x i32> @fcvtzs_v1f64_v1i32(<1 x double> %op1) {
3180; CHECK-LABEL: fcvtzs_v1f64_v1i32:
3181; CHECK:       // %bb.0:
3182; CHECK-NEXT:    ptrue p0.d, vl2
3183; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
3184; CHECK-NEXT:    fcvtzs z0.d, p0/m, z0.d
3185; CHECK-NEXT:    uzp1 z0.s, z0.s, z0.s
3186; CHECK-NEXT:    // kill: def $d0 killed $d0 killed $z0
3187; CHECK-NEXT:    ret
3188;
3189; NONEON-NOSVE-LABEL: fcvtzs_v1f64_v1i32:
3190; NONEON-NOSVE:       // %bb.0:
3191; NONEON-NOSVE-NEXT:    sub sp, sp, #16
3192; NONEON-NOSVE-NEXT:    .cfi_def_cfa_offset 16
3193; NONEON-NOSVE-NEXT:    fcvtzs w8, d0
3194; NONEON-NOSVE-NEXT:    str w8, [sp, #8]
3195; NONEON-NOSVE-NEXT:    ldr d0, [sp, #8]
3196; NONEON-NOSVE-NEXT:    add sp, sp, #16
3197; NONEON-NOSVE-NEXT:    ret
3198  %res = fptosi <1 x double> %op1 to <1 x i32>
3199  ret <1 x i32> %res
3200}
3201
3202define <2 x i32> @fcvtzs_v2f64_v2i32(<2 x double> %op1) {
3203; CHECK-LABEL: fcvtzs_v2f64_v2i32:
3204; CHECK:       // %bb.0:
3205; CHECK-NEXT:    ptrue p0.d, vl2
3206; CHECK-NEXT:    // kill: def $q0 killed $q0 def $z0
3207; CHECK-NEXT:    fcvtzs z0.d, p0/m, z0.d
3208; CHECK-NEXT:    uzp1 z0.s, z0.s, z0.s
3209; CHECK-NEXT:    // kill: def $d0 killed $d0 killed $z0
3210; CHECK-NEXT:    ret
3211;
3212; NONEON-NOSVE-LABEL: fcvtzs_v2f64_v2i32:
3213; NONEON-NOSVE:       // %bb.0:
3214; NONEON-NOSVE-NEXT:    str q0, [sp, #-32]!
3215; NONEON-NOSVE-NEXT:    .cfi_def_cfa_offset 32
3216; NONEON-NOSVE-NEXT:    ldp d0, d1, [sp]
3217; NONEON-NOSVE-NEXT:    fcvtzs w9, d1
3218; NONEON-NOSVE-NEXT:    fcvtzs w8, d0
3219; NONEON-NOSVE-NEXT:    stp w8, w9, [sp, #24]
3220; NONEON-NOSVE-NEXT:    ldr d0, [sp, #24]
3221; NONEON-NOSVE-NEXT:    add sp, sp, #32
3222; NONEON-NOSVE-NEXT:    ret
3223  %res = fptosi <2 x double> %op1 to <2 x i32>
3224  ret <2 x i32> %res
3225}
3226
3227define <4 x i32> @fcvtzs_v4f64_v4i32(ptr %a) {
3228; CHECK-LABEL: fcvtzs_v4f64_v4i32:
3229; CHECK:       // %bb.0:
3230; CHECK-NEXT:    ldp q0, q1, [x0]
3231; CHECK-NEXT:    ptrue p0.d, vl2
3232; CHECK-NEXT:    fcvtzs z1.d, p0/m, z1.d
3233; CHECK-NEXT:    fcvtzs z0.d, p0/m, z0.d
3234; CHECK-NEXT:    ptrue p0.s, vl2
3235; CHECK-NEXT:    uzp1 z1.s, z1.s, z1.s
3236; CHECK-NEXT:    uzp1 z0.s, z0.s, z0.s
3237; CHECK-NEXT:    splice z0.s, p0, z0.s, z1.s
3238; CHECK-NEXT:    // kill: def $q0 killed $q0 killed $z0
3239; CHECK-NEXT:    ret
3240;
3241; NONEON-NOSVE-LABEL: fcvtzs_v4f64_v4i32:
3242; NONEON-NOSVE:       // %bb.0:
3243; NONEON-NOSVE-NEXT:    ldp q1, q0, [x0]
3244; NONEON-NOSVE-NEXT:    stp q1, q0, [sp, #-48]!
3245; NONEON-NOSVE-NEXT:    .cfi_def_cfa_offset 48
3246; NONEON-NOSVE-NEXT:    ldp d0, d1, [sp, #16]
3247; NONEON-NOSVE-NEXT:    fcvtzs w9, d1
3248; NONEON-NOSVE-NEXT:    fcvtzs w8, d0
3249; NONEON-NOSVE-NEXT:    ldp d0, d1, [sp]
3250; NONEON-NOSVE-NEXT:    stp w8, w9, [sp, #40]
3251; NONEON-NOSVE-NEXT:    fcvtzs w9, d1
3252; NONEON-NOSVE-NEXT:    fcvtzs w8, d0
3253; NONEON-NOSVE-NEXT:    stp w8, w9, [sp, #32]
3254; NONEON-NOSVE-NEXT:    ldr q0, [sp, #32]
3255; NONEON-NOSVE-NEXT:    add sp, sp, #48
3256; NONEON-NOSVE-NEXT:    ret
3257  %op1 = load <4 x double>, ptr %a
3258  %res = fptosi <4 x double> %op1 to <4 x i32>
3259  ret <4 x i32> %res
3260}
3261
3262define void @fcvtzs_v8f64_v8i32(ptr %a, ptr %b) {
3263; CHECK-LABEL: fcvtzs_v8f64_v8i32:
3264; CHECK:       // %bb.0:
3265; CHECK-NEXT:    ldp q0, q1, [x0, #32]
3266; CHECK-NEXT:    ptrue p0.d, vl2
3267; CHECK-NEXT:    ldp q2, q3, [x0]
3268; CHECK-NEXT:    fcvtzs z1.d, p0/m, z1.d
3269; CHECK-NEXT:    fcvtzs z0.d, p0/m, z0.d
3270; CHECK-NEXT:    fcvtzs z3.d, p0/m, z3.d
3271; CHECK-NEXT:    fcvtzs z2.d, p0/m, z2.d
3272; CHECK-NEXT:    ptrue p0.s, vl2
3273; CHECK-NEXT:    uzp1 z1.s, z1.s, z1.s
3274; CHECK-NEXT:    uzp1 z0.s, z0.s, z0.s
3275; CHECK-NEXT:    uzp1 z3.s, z3.s, z3.s
3276; CHECK-NEXT:    uzp1 z2.s, z2.s, z2.s
3277; CHECK-NEXT:    splice z0.s, p0, z0.s, z1.s
3278; CHECK-NEXT:    splice z2.s, p0, z2.s, z3.s
3279; CHECK-NEXT:    stp q2, q0, [x1]
3280; CHECK-NEXT:    ret
3281;
3282; NONEON-NOSVE-LABEL: fcvtzs_v8f64_v8i32:
3283; NONEON-NOSVE:       // %bb.0:
3284; NONEON-NOSVE-NEXT:    sub sp, sp, #96
3285; NONEON-NOSVE-NEXT:    .cfi_def_cfa_offset 96
3286; NONEON-NOSVE-NEXT:    ldp q1, q0, [x0]
3287; NONEON-NOSVE-NEXT:    ldp q2, q3, [x0, #32]
3288; NONEON-NOSVE-NEXT:    str q1, [sp]
3289; NONEON-NOSVE-NEXT:    stp q3, q0, [sp, #16]
3290; NONEON-NOSVE-NEXT:    ldp d0, d1, [sp, #32]
3291; NONEON-NOSVE-NEXT:    str q2, [sp, #48]
3292; NONEON-NOSVE-NEXT:    fcvtzs w9, d1
3293; NONEON-NOSVE-NEXT:    fcvtzs w8, d0
3294; NONEON-NOSVE-NEXT:    ldp d0, d1, [sp]
3295; NONEON-NOSVE-NEXT:    stp w8, w9, [sp, #72]
3296; NONEON-NOSVE-NEXT:    fcvtzs w9, d1
3297; NONEON-NOSVE-NEXT:    fcvtzs w8, d0
3298; NONEON-NOSVE-NEXT:    ldp d0, d1, [sp, #16]
3299; NONEON-NOSVE-NEXT:    stp w8, w9, [sp, #64]
3300; NONEON-NOSVE-NEXT:    fcvtzs w9, d1
3301; NONEON-NOSVE-NEXT:    fcvtzs w8, d0
3302; NONEON-NOSVE-NEXT:    ldp d0, d1, [sp, #48]
3303; NONEON-NOSVE-NEXT:    stp w8, w9, [sp, #88]
3304; NONEON-NOSVE-NEXT:    fcvtzs w9, d1
3305; NONEON-NOSVE-NEXT:    fcvtzs w8, d0
3306; NONEON-NOSVE-NEXT:    stp w8, w9, [sp, #80]
3307; NONEON-NOSVE-NEXT:    ldp q1, q0, [sp, #64]
3308; NONEON-NOSVE-NEXT:    stp q1, q0, [x1]
3309; NONEON-NOSVE-NEXT:    add sp, sp, #96
3310; NONEON-NOSVE-NEXT:    ret
3311  %op1 = load <8 x double>, ptr %a
3312  %res = fptosi <8 x double> %op1 to <8 x i32>
3313  store <8 x i32> %res, ptr %b
3314  ret void
3315}
3316
3317;
3318; FCVTZS D -> D
3319;
3320
3321define <1 x i64> @fcvtzs_v1f64_v1i64(<1 x double> %op1) {
3322; CHECK-LABEL: fcvtzs_v1f64_v1i64:
3323; CHECK:       // %bb.0:
3324; CHECK-NEXT:    ptrue p0.d, vl1
3325; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
3326; CHECK-NEXT:    fcvtzs z0.d, p0/m, z0.d
3327; CHECK-NEXT:    // kill: def $d0 killed $d0 killed $z0
3328; CHECK-NEXT:    ret
3329;
3330; NONEON-NOSVE-LABEL: fcvtzs_v1f64_v1i64:
3331; NONEON-NOSVE:       // %bb.0:
3332; NONEON-NOSVE-NEXT:    sub sp, sp, #16
3333; NONEON-NOSVE-NEXT:    .cfi_def_cfa_offset 16
3334; NONEON-NOSVE-NEXT:    fcvtzs x8, d0
3335; NONEON-NOSVE-NEXT:    str x8, [sp, #8]
3336; NONEON-NOSVE-NEXT:    ldr d0, [sp, #8]
3337; NONEON-NOSVE-NEXT:    add sp, sp, #16
3338; NONEON-NOSVE-NEXT:    ret
3339  %res = fptosi <1 x double> %op1 to <1 x i64>
3340  ret <1 x i64> %res
3341}
3342
3343define <2 x i64> @fcvtzs_v2f64_v2i64(<2 x double> %op1) {
3344; CHECK-LABEL: fcvtzs_v2f64_v2i64:
3345; CHECK:       // %bb.0:
3346; CHECK-NEXT:    ptrue p0.d, vl2
3347; CHECK-NEXT:    // kill: def $q0 killed $q0 def $z0
3348; CHECK-NEXT:    fcvtzs z0.d, p0/m, z0.d
3349; CHECK-NEXT:    // kill: def $q0 killed $q0 killed $z0
3350; CHECK-NEXT:    ret
3351;
3352; NONEON-NOSVE-LABEL: fcvtzs_v2f64_v2i64:
3353; NONEON-NOSVE:       // %bb.0:
3354; NONEON-NOSVE-NEXT:    str q0, [sp, #-32]!
3355; NONEON-NOSVE-NEXT:    .cfi_def_cfa_offset 32
3356; NONEON-NOSVE-NEXT:    ldp d0, d1, [sp]
3357; NONEON-NOSVE-NEXT:    fcvtzs x9, d1
3358; NONEON-NOSVE-NEXT:    fcvtzs x8, d0
3359; NONEON-NOSVE-NEXT:    stp x8, x9, [sp, #16]
3360; NONEON-NOSVE-NEXT:    ldr q0, [sp, #16]
3361; NONEON-NOSVE-NEXT:    add sp, sp, #32
3362; NONEON-NOSVE-NEXT:    ret
3363  %res = fptosi <2 x double> %op1 to <2 x i64>
3364  ret <2 x i64> %res
3365}
3366
3367define void @fcvtzs_v4f64_v4i64(ptr %a, ptr %b) {
3368; CHECK-LABEL: fcvtzs_v4f64_v4i64:
3369; CHECK:       // %bb.0:
3370; CHECK-NEXT:    ldp q0, q1, [x0]
3371; CHECK-NEXT:    ptrue p0.d, vl2
3372; CHECK-NEXT:    fcvtzs z0.d, p0/m, z0.d
3373; CHECK-NEXT:    fcvtzs z1.d, p0/m, z1.d
3374; CHECK-NEXT:    stp q0, q1, [x1]
3375; CHECK-NEXT:    ret
3376;
3377; NONEON-NOSVE-LABEL: fcvtzs_v4f64_v4i64:
3378; NONEON-NOSVE:       // %bb.0:
3379; NONEON-NOSVE-NEXT:    ldp q1, q0, [x0]
3380; NONEON-NOSVE-NEXT:    stp q1, q0, [sp, #-64]!
3381; NONEON-NOSVE-NEXT:    .cfi_def_cfa_offset 64
3382; NONEON-NOSVE-NEXT:    ldp d0, d1, [sp, #16]
3383; NONEON-NOSVE-NEXT:    fcvtzs x9, d1
3384; NONEON-NOSVE-NEXT:    fcvtzs x8, d0
3385; NONEON-NOSVE-NEXT:    ldp d0, d1, [sp]
3386; NONEON-NOSVE-NEXT:    stp x8, x9, [sp, #48]
3387; NONEON-NOSVE-NEXT:    fcvtzs x9, d1
3388; NONEON-NOSVE-NEXT:    fcvtzs x8, d0
3389; NONEON-NOSVE-NEXT:    stp x8, x9, [sp, #32]
3390; NONEON-NOSVE-NEXT:    ldp q0, q1, [sp, #32]
3391; NONEON-NOSVE-NEXT:    stp q0, q1, [x1]
3392; NONEON-NOSVE-NEXT:    add sp, sp, #64
3393; NONEON-NOSVE-NEXT:    ret
3394  %op1 = load <4 x double>, ptr %a
3395  %res = fptosi <4 x double> %op1 to <4 x i64>
3396  store <4 x i64> %res, ptr %b
3397  ret void
3398}
3399