1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc -mattr=+sve -force-streaming-compatible < %s | FileCheck %s 3; RUN: llc -mattr=+sme -force-streaming < %s | FileCheck %s 4; RUN: llc -force-streaming-compatible < %s | FileCheck %s --check-prefix=NONEON-NOSVE 5 6target triple = "aarch64-unknown-linux-gnu" 7 8; 9; FCVT H -> S; Without load instr 10; 11 12define void @fcvt_v2f16_to_v2f32(<2 x half> %a, ptr %b) { 13; CHECK-LABEL: fcvt_v2f16_to_v2f32: 14; CHECK: // %bb.0: 15; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0 16; CHECK-NEXT: ptrue p0.s, vl4 17; CHECK-NEXT: uunpklo z0.s, z0.h 18; CHECK-NEXT: fcvt z0.s, p0/m, z0.h 19; CHECK-NEXT: str d0, [x0] 20; CHECK-NEXT: ret 21; 22; NONEON-NOSVE-LABEL: fcvt_v2f16_to_v2f32: 23; NONEON-NOSVE: // %bb.0: 24; NONEON-NOSVE-NEXT: str d0, [sp, #-16]! 25; NONEON-NOSVE-NEXT: .cfi_def_cfa_offset 16 26; NONEON-NOSVE-NEXT: ldr h0, [sp, #2] 27; NONEON-NOSVE-NEXT: fcvt s1, h0 28; NONEON-NOSVE-NEXT: ldr h0, [sp] 29; NONEON-NOSVE-NEXT: fcvt s0, h0 30; NONEON-NOSVE-NEXT: stp s0, s1, [sp, #8] 31; NONEON-NOSVE-NEXT: ldr d0, [sp, #8] 32; NONEON-NOSVE-NEXT: str d0, [x0] 33; NONEON-NOSVE-NEXT: add sp, sp, #16 34; NONEON-NOSVE-NEXT: ret 35 %res = fpext <2 x half> %a to <2 x float> 36 store <2 x float> %res, ptr %b 37 ret void 38} 39 40define void @fcvt_v4f16_to_v4f32(<4 x half> %a, ptr %b) { 41; CHECK-LABEL: fcvt_v4f16_to_v4f32: 42; CHECK: // %bb.0: 43; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0 44; CHECK-NEXT: ptrue p0.s, vl4 45; CHECK-NEXT: uunpklo z0.s, z0.h 46; CHECK-NEXT: fcvt z0.s, p0/m, z0.h 47; CHECK-NEXT: str q0, [x0] 48; CHECK-NEXT: ret 49; 50; NONEON-NOSVE-LABEL: fcvt_v4f16_to_v4f32: 51; NONEON-NOSVE: // %bb.0: 52; NONEON-NOSVE-NEXT: sub sp, sp, #32 53; NONEON-NOSVE-NEXT: .cfi_def_cfa_offset 32 54; NONEON-NOSVE-NEXT: str d0, [sp, #8] 55; NONEON-NOSVE-NEXT: ldr h0, [sp, #14] 56; NONEON-NOSVE-NEXT: fcvt s1, h0 57; NONEON-NOSVE-NEXT: ldr h0, [sp, #12] 58; NONEON-NOSVE-NEXT: fcvt s0, h0 59; NONEON-NOSVE-NEXT: stp s0, s1, [sp, #24] 60; NONEON-NOSVE-NEXT: ldr h0, [sp, #10] 61; NONEON-NOSVE-NEXT: fcvt s1, h0 62; NONEON-NOSVE-NEXT: ldr h0, [sp, #8] 63; NONEON-NOSVE-NEXT: fcvt s0, h0 64; NONEON-NOSVE-NEXT: stp s0, s1, [sp, #16] 65; NONEON-NOSVE-NEXT: ldr q0, [sp, #16] 66; NONEON-NOSVE-NEXT: str q0, [x0] 67; NONEON-NOSVE-NEXT: add sp, sp, #32 68; NONEON-NOSVE-NEXT: ret 69 %res = fpext <4 x half> %a to <4 x float> 70 store <4 x float> %res, ptr %b 71 ret void 72} 73 74define void @fcvt_v8f16_to_v8f32(<8 x half> %a, ptr %b) { 75; CHECK-LABEL: fcvt_v8f16_to_v8f32: 76; CHECK: // %bb.0: 77; CHECK-NEXT: // kill: def $q0 killed $q0 def $z0 78; CHECK-NEXT: uunpklo z1.s, z0.h 79; CHECK-NEXT: ptrue p0.s, vl4 80; CHECK-NEXT: ext z0.b, z0.b, z0.b, #8 81; CHECK-NEXT: uunpklo z0.s, z0.h 82; CHECK-NEXT: fcvt z1.s, p0/m, z1.h 83; CHECK-NEXT: fcvt z0.s, p0/m, z0.h 84; CHECK-NEXT: stp q1, q0, [x0] 85; CHECK-NEXT: ret 86; 87; NONEON-NOSVE-LABEL: fcvt_v8f16_to_v8f32: 88; NONEON-NOSVE: // %bb.0: 89; NONEON-NOSVE-NEXT: str q0, [sp, #-64]! 90; NONEON-NOSVE-NEXT: .cfi_def_cfa_offset 64 91; NONEON-NOSVE-NEXT: ldp d1, d0, [sp] 92; NONEON-NOSVE-NEXT: stp d0, d1, [sp, #16] 93; NONEON-NOSVE-NEXT: ldr h0, [sp, #30] 94; NONEON-NOSVE-NEXT: fcvt s1, h0 95; NONEON-NOSVE-NEXT: ldr h0, [sp, #28] 96; NONEON-NOSVE-NEXT: fcvt s0, h0 97; NONEON-NOSVE-NEXT: stp s0, s1, [sp, #56] 98; NONEON-NOSVE-NEXT: ldr h0, [sp, #26] 99; NONEON-NOSVE-NEXT: fcvt s1, h0 100; NONEON-NOSVE-NEXT: ldr h0, [sp, #24] 101; NONEON-NOSVE-NEXT: fcvt s0, h0 102; NONEON-NOSVE-NEXT: stp s0, s1, [sp, #48] 103; NONEON-NOSVE-NEXT: ldr h0, [sp, #22] 104; NONEON-NOSVE-NEXT: fcvt s1, h0 105; NONEON-NOSVE-NEXT: ldr h0, [sp, #20] 106; NONEON-NOSVE-NEXT: fcvt s0, h0 107; NONEON-NOSVE-NEXT: stp s0, s1, [sp, #40] 108; NONEON-NOSVE-NEXT: ldr h0, [sp, #18] 109; NONEON-NOSVE-NEXT: fcvt s1, h0 110; NONEON-NOSVE-NEXT: ldr h0, [sp, #16] 111; NONEON-NOSVE-NEXT: fcvt s0, h0 112; NONEON-NOSVE-NEXT: stp s0, s1, [sp, #32] 113; NONEON-NOSVE-NEXT: ldp q0, q1, [sp, #32] 114; NONEON-NOSVE-NEXT: stp q1, q0, [x0] 115; NONEON-NOSVE-NEXT: add sp, sp, #64 116; NONEON-NOSVE-NEXT: ret 117 %res = fpext <8 x half> %a to <8 x float> 118 store <8 x float> %res, ptr %b 119 ret void 120} 121 122define void @fcvt_v16f16_to_v16f32(<16 x half> %a, ptr %b) { 123; CHECK-LABEL: fcvt_v16f16_to_v16f32: 124; CHECK: // %bb.0: 125; CHECK-NEXT: // kill: def $q1 killed $q1 def $z1 126; CHECK-NEXT: // kill: def $q0 killed $q0 def $z0 127; CHECK-NEXT: uunpklo z2.s, z1.h 128; CHECK-NEXT: uunpklo z3.s, z0.h 129; CHECK-NEXT: ptrue p0.s, vl4 130; CHECK-NEXT: ext z1.b, z1.b, z1.b, #8 131; CHECK-NEXT: ext z0.b, z0.b, z0.b, #8 132; CHECK-NEXT: uunpklo z1.s, z1.h 133; CHECK-NEXT: uunpklo z0.s, z0.h 134; CHECK-NEXT: fcvt z2.s, p0/m, z2.h 135; CHECK-NEXT: fcvt z3.s, p0/m, z3.h 136; CHECK-NEXT: fcvt z1.s, p0/m, z1.h 137; CHECK-NEXT: fcvt z0.s, p0/m, z0.h 138; CHECK-NEXT: stp q3, q0, [x0] 139; CHECK-NEXT: stp q2, q1, [x0, #32] 140; CHECK-NEXT: ret 141; 142; NONEON-NOSVE-LABEL: fcvt_v16f16_to_v16f32: 143; NONEON-NOSVE: // %bb.0: 144; NONEON-NOSVE-NEXT: stp q0, q1, [sp, #-128]! 145; NONEON-NOSVE-NEXT: .cfi_def_cfa_offset 128 146; NONEON-NOSVE-NEXT: ldp d1, d0, [sp] 147; NONEON-NOSVE-NEXT: stp d0, d1, [sp, #32] 148; NONEON-NOSVE-NEXT: ldp d1, d0, [sp, #16] 149; NONEON-NOSVE-NEXT: stp d0, d1, [sp, #48] 150; NONEON-NOSVE-NEXT: ldr h0, [sp, #46] 151; NONEON-NOSVE-NEXT: fcvt s1, h0 152; NONEON-NOSVE-NEXT: ldr h0, [sp, #44] 153; NONEON-NOSVE-NEXT: fcvt s0, h0 154; NONEON-NOSVE-NEXT: stp s0, s1, [sp, #88] 155; NONEON-NOSVE-NEXT: ldr h0, [sp, #42] 156; NONEON-NOSVE-NEXT: fcvt s1, h0 157; NONEON-NOSVE-NEXT: ldr h0, [sp, #40] 158; NONEON-NOSVE-NEXT: fcvt s0, h0 159; NONEON-NOSVE-NEXT: stp s0, s1, [sp, #80] 160; NONEON-NOSVE-NEXT: ldr h0, [sp, #38] 161; NONEON-NOSVE-NEXT: fcvt s1, h0 162; NONEON-NOSVE-NEXT: ldr h0, [sp, #36] 163; NONEON-NOSVE-NEXT: fcvt s0, h0 164; NONEON-NOSVE-NEXT: stp s0, s1, [sp, #72] 165; NONEON-NOSVE-NEXT: ldr h0, [sp, #34] 166; NONEON-NOSVE-NEXT: fcvt s1, h0 167; NONEON-NOSVE-NEXT: ldr h0, [sp, #32] 168; NONEON-NOSVE-NEXT: fcvt s0, h0 169; NONEON-NOSVE-NEXT: stp s0, s1, [sp, #64] 170; NONEON-NOSVE-NEXT: ldr h0, [sp, #62] 171; NONEON-NOSVE-NEXT: ldp q3, q2, [sp, #64] 172; NONEON-NOSVE-NEXT: fcvt s1, h0 173; NONEON-NOSVE-NEXT: ldr h0, [sp, #60] 174; NONEON-NOSVE-NEXT: fcvt s0, h0 175; NONEON-NOSVE-NEXT: stp s0, s1, [sp, #120] 176; NONEON-NOSVE-NEXT: ldr h0, [sp, #58] 177; NONEON-NOSVE-NEXT: fcvt s1, h0 178; NONEON-NOSVE-NEXT: ldr h0, [sp, #56] 179; NONEON-NOSVE-NEXT: fcvt s0, h0 180; NONEON-NOSVE-NEXT: stp s0, s1, [sp, #112] 181; NONEON-NOSVE-NEXT: ldr h0, [sp, #54] 182; NONEON-NOSVE-NEXT: fcvt s1, h0 183; NONEON-NOSVE-NEXT: ldr h0, [sp, #52] 184; NONEON-NOSVE-NEXT: fcvt s0, h0 185; NONEON-NOSVE-NEXT: stp s0, s1, [sp, #104] 186; NONEON-NOSVE-NEXT: ldr h0, [sp, #50] 187; NONEON-NOSVE-NEXT: fcvt s1, h0 188; NONEON-NOSVE-NEXT: ldr h0, [sp, #48] 189; NONEON-NOSVE-NEXT: fcvt s0, h0 190; NONEON-NOSVE-NEXT: stp s0, s1, [sp, #96] 191; NONEON-NOSVE-NEXT: ldp q0, q1, [sp, #96] 192; NONEON-NOSVE-NEXT: stp q2, q3, [x0] 193; NONEON-NOSVE-NEXT: stp q1, q0, [x0, #32] 194; NONEON-NOSVE-NEXT: add sp, sp, #128 195; NONEON-NOSVE-NEXT: ret 196 %res = fpext <16 x half> %a to <16 x float> 197 store <16 x float> %res, ptr %b 198 ret void 199} 200 201; 202; 203; FCVT H -> S 204; 205 206define void @fcvt_v2f16_v2f32(ptr %a, ptr %b) { 207; CHECK-LABEL: fcvt_v2f16_v2f32: 208; CHECK: // %bb.0: 209; CHECK-NEXT: ptrue p0.s, vl2 210; CHECK-NEXT: ld1h { z0.s }, p0/z, [x0] 211; CHECK-NEXT: fcvt z0.s, p0/m, z0.h 212; CHECK-NEXT: str d0, [x1] 213; CHECK-NEXT: ret 214; 215; NONEON-NOSVE-LABEL: fcvt_v2f16_v2f32: 216; NONEON-NOSVE: // %bb.0: 217; NONEON-NOSVE-NEXT: sub sp, sp, #32 218; NONEON-NOSVE-NEXT: .cfi_def_cfa_offset 32 219; NONEON-NOSVE-NEXT: ldr w8, [x0] 220; NONEON-NOSVE-NEXT: str w8, [sp, #8] 221; NONEON-NOSVE-NEXT: ldr d0, [sp, #8] 222; NONEON-NOSVE-NEXT: str d0, [sp, #16] 223; NONEON-NOSVE-NEXT: ldr h0, [sp, #18] 224; NONEON-NOSVE-NEXT: fcvt s1, h0 225; NONEON-NOSVE-NEXT: ldr h0, [sp, #16] 226; NONEON-NOSVE-NEXT: fcvt s0, h0 227; NONEON-NOSVE-NEXT: stp s0, s1, [sp, #24] 228; NONEON-NOSVE-NEXT: ldr d0, [sp, #24] 229; NONEON-NOSVE-NEXT: str d0, [x1] 230; NONEON-NOSVE-NEXT: add sp, sp, #32 231; NONEON-NOSVE-NEXT: ret 232 %op1 = load <2 x half>, ptr %a 233 %res = fpext <2 x half> %op1 to <2 x float> 234 store <2 x float> %res, ptr %b 235 ret void 236} 237 238define void @fcvt_v4f16_v4f32(ptr %a, ptr %b) { 239; CHECK-LABEL: fcvt_v4f16_v4f32: 240; CHECK: // %bb.0: 241; CHECK-NEXT: ptrue p0.s, vl4 242; CHECK-NEXT: ld1h { z0.s }, p0/z, [x0] 243; CHECK-NEXT: fcvt z0.s, p0/m, z0.h 244; CHECK-NEXT: str q0, [x1] 245; CHECK-NEXT: ret 246; 247; NONEON-NOSVE-LABEL: fcvt_v4f16_v4f32: 248; NONEON-NOSVE: // %bb.0: 249; NONEON-NOSVE-NEXT: sub sp, sp, #32 250; NONEON-NOSVE-NEXT: .cfi_def_cfa_offset 32 251; NONEON-NOSVE-NEXT: ldr d0, [x0] 252; NONEON-NOSVE-NEXT: str d0, [sp, #8] 253; NONEON-NOSVE-NEXT: ldr h0, [sp, #14] 254; NONEON-NOSVE-NEXT: fcvt s1, h0 255; NONEON-NOSVE-NEXT: ldr h0, [sp, #12] 256; NONEON-NOSVE-NEXT: fcvt s0, h0 257; NONEON-NOSVE-NEXT: stp s0, s1, [sp, #24] 258; NONEON-NOSVE-NEXT: ldr h0, [sp, #10] 259; NONEON-NOSVE-NEXT: fcvt s1, h0 260; NONEON-NOSVE-NEXT: ldr h0, [sp, #8] 261; NONEON-NOSVE-NEXT: fcvt s0, h0 262; NONEON-NOSVE-NEXT: stp s0, s1, [sp, #16] 263; NONEON-NOSVE-NEXT: ldr q0, [sp, #16] 264; NONEON-NOSVE-NEXT: str q0, [x1] 265; NONEON-NOSVE-NEXT: add sp, sp, #32 266; NONEON-NOSVE-NEXT: ret 267 %op1 = load <4 x half>, ptr %a 268 %res = fpext <4 x half> %op1 to <4 x float> 269 store <4 x float> %res, ptr %b 270 ret void 271} 272 273define void @fcvt_v8f16_v8f32(ptr %a, ptr %b) { 274; CHECK-LABEL: fcvt_v8f16_v8f32: 275; CHECK: // %bb.0: 276; CHECK-NEXT: ptrue p0.s, vl4 277; CHECK-NEXT: mov x8, #4 // =0x4 278; CHECK-NEXT: ld1h { z0.s }, p0/z, [x0, x8, lsl #1] 279; CHECK-NEXT: ld1h { z1.s }, p0/z, [x0] 280; CHECK-NEXT: fcvt z0.s, p0/m, z0.h 281; CHECK-NEXT: fcvt z1.s, p0/m, z1.h 282; CHECK-NEXT: stp q1, q0, [x1] 283; CHECK-NEXT: ret 284; 285; NONEON-NOSVE-LABEL: fcvt_v8f16_v8f32: 286; NONEON-NOSVE: // %bb.0: 287; NONEON-NOSVE-NEXT: ldr q0, [x0] 288; NONEON-NOSVE-NEXT: str q0, [sp, #-64]! 289; NONEON-NOSVE-NEXT: .cfi_def_cfa_offset 64 290; NONEON-NOSVE-NEXT: ldp d1, d0, [sp] 291; NONEON-NOSVE-NEXT: stp d0, d1, [sp, #16] 292; NONEON-NOSVE-NEXT: ldr h0, [sp, #30] 293; NONEON-NOSVE-NEXT: fcvt s1, h0 294; NONEON-NOSVE-NEXT: ldr h0, [sp, #28] 295; NONEON-NOSVE-NEXT: fcvt s0, h0 296; NONEON-NOSVE-NEXT: stp s0, s1, [sp, #56] 297; NONEON-NOSVE-NEXT: ldr h0, [sp, #26] 298; NONEON-NOSVE-NEXT: fcvt s1, h0 299; NONEON-NOSVE-NEXT: ldr h0, [sp, #24] 300; NONEON-NOSVE-NEXT: fcvt s0, h0 301; NONEON-NOSVE-NEXT: stp s0, s1, [sp, #48] 302; NONEON-NOSVE-NEXT: ldr h0, [sp, #22] 303; NONEON-NOSVE-NEXT: fcvt s1, h0 304; NONEON-NOSVE-NEXT: ldr h0, [sp, #20] 305; NONEON-NOSVE-NEXT: fcvt s0, h0 306; NONEON-NOSVE-NEXT: stp s0, s1, [sp, #40] 307; NONEON-NOSVE-NEXT: ldr h0, [sp, #18] 308; NONEON-NOSVE-NEXT: fcvt s1, h0 309; NONEON-NOSVE-NEXT: ldr h0, [sp, #16] 310; NONEON-NOSVE-NEXT: fcvt s0, h0 311; NONEON-NOSVE-NEXT: stp s0, s1, [sp, #32] 312; NONEON-NOSVE-NEXT: ldp q0, q1, [sp, #32] 313; NONEON-NOSVE-NEXT: stp q1, q0, [x1] 314; NONEON-NOSVE-NEXT: add sp, sp, #64 315; NONEON-NOSVE-NEXT: ret 316 %op1 = load <8 x half>, ptr %a 317 %res = fpext <8 x half> %op1 to <8 x float> 318 store <8 x float> %res, ptr %b 319 ret void 320} 321 322define void @fcvt_v16f16_v16f32(ptr %a, ptr %b) { 323; CHECK-LABEL: fcvt_v16f16_v16f32: 324; CHECK: // %bb.0: 325; CHECK-NEXT: ptrue p0.s, vl4 326; CHECK-NEXT: mov x8, #8 // =0x8 327; CHECK-NEXT: ld1h { z0.s }, p0/z, [x0, x8, lsl #1] 328; CHECK-NEXT: mov x8, #12 // =0xc 329; CHECK-NEXT: ld1h { z2.s }, p0/z, [x0] 330; CHECK-NEXT: ld1h { z1.s }, p0/z, [x0, x8, lsl #1] 331; CHECK-NEXT: mov x8, #4 // =0x4 332; CHECK-NEXT: ld1h { z3.s }, p0/z, [x0, x8, lsl #1] 333; CHECK-NEXT: fcvt z0.s, p0/m, z0.h 334; CHECK-NEXT: fcvt z2.s, p0/m, z2.h 335; CHECK-NEXT: fcvt z1.s, p0/m, z1.h 336; CHECK-NEXT: fcvt z3.s, p0/m, z3.h 337; CHECK-NEXT: stp q0, q1, [x1, #32] 338; CHECK-NEXT: stp q2, q3, [x1] 339; CHECK-NEXT: ret 340; 341; NONEON-NOSVE-LABEL: fcvt_v16f16_v16f32: 342; NONEON-NOSVE: // %bb.0: 343; NONEON-NOSVE-NEXT: ldp q0, q1, [x0] 344; NONEON-NOSVE-NEXT: stp q0, q1, [sp, #-128]! 345; NONEON-NOSVE-NEXT: .cfi_def_cfa_offset 128 346; NONEON-NOSVE-NEXT: ldp d1, d0, [sp] 347; NONEON-NOSVE-NEXT: stp d0, d1, [sp, #32] 348; NONEON-NOSVE-NEXT: ldp d1, d0, [sp, #16] 349; NONEON-NOSVE-NEXT: stp d0, d1, [sp, #48] 350; NONEON-NOSVE-NEXT: ldr h0, [sp, #46] 351; NONEON-NOSVE-NEXT: fcvt s1, h0 352; NONEON-NOSVE-NEXT: ldr h0, [sp, #44] 353; NONEON-NOSVE-NEXT: fcvt s0, h0 354; NONEON-NOSVE-NEXT: stp s0, s1, [sp, #88] 355; NONEON-NOSVE-NEXT: ldr h0, [sp, #42] 356; NONEON-NOSVE-NEXT: fcvt s1, h0 357; NONEON-NOSVE-NEXT: ldr h0, [sp, #40] 358; NONEON-NOSVE-NEXT: fcvt s0, h0 359; NONEON-NOSVE-NEXT: stp s0, s1, [sp, #80] 360; NONEON-NOSVE-NEXT: ldr h0, [sp, #38] 361; NONEON-NOSVE-NEXT: fcvt s1, h0 362; NONEON-NOSVE-NEXT: ldr h0, [sp, #36] 363; NONEON-NOSVE-NEXT: fcvt s0, h0 364; NONEON-NOSVE-NEXT: stp s0, s1, [sp, #72] 365; NONEON-NOSVE-NEXT: ldr h0, [sp, #34] 366; NONEON-NOSVE-NEXT: fcvt s1, h0 367; NONEON-NOSVE-NEXT: ldr h0, [sp, #32] 368; NONEON-NOSVE-NEXT: fcvt s0, h0 369; NONEON-NOSVE-NEXT: stp s0, s1, [sp, #64] 370; NONEON-NOSVE-NEXT: ldr h0, [sp, #62] 371; NONEON-NOSVE-NEXT: ldp q3, q2, [sp, #64] 372; NONEON-NOSVE-NEXT: fcvt s1, h0 373; NONEON-NOSVE-NEXT: ldr h0, [sp, #60] 374; NONEON-NOSVE-NEXT: fcvt s0, h0 375; NONEON-NOSVE-NEXT: stp s0, s1, [sp, #120] 376; NONEON-NOSVE-NEXT: ldr h0, [sp, #58] 377; NONEON-NOSVE-NEXT: fcvt s1, h0 378; NONEON-NOSVE-NEXT: ldr h0, [sp, #56] 379; NONEON-NOSVE-NEXT: fcvt s0, h0 380; NONEON-NOSVE-NEXT: stp s0, s1, [sp, #112] 381; NONEON-NOSVE-NEXT: ldr h0, [sp, #54] 382; NONEON-NOSVE-NEXT: fcvt s1, h0 383; NONEON-NOSVE-NEXT: ldr h0, [sp, #52] 384; NONEON-NOSVE-NEXT: fcvt s0, h0 385; NONEON-NOSVE-NEXT: stp s0, s1, [sp, #104] 386; NONEON-NOSVE-NEXT: ldr h0, [sp, #50] 387; NONEON-NOSVE-NEXT: fcvt s1, h0 388; NONEON-NOSVE-NEXT: ldr h0, [sp, #48] 389; NONEON-NOSVE-NEXT: fcvt s0, h0 390; NONEON-NOSVE-NEXT: stp s0, s1, [sp, #96] 391; NONEON-NOSVE-NEXT: ldp q0, q1, [sp, #96] 392; NONEON-NOSVE-NEXT: stp q2, q3, [x1] 393; NONEON-NOSVE-NEXT: stp q1, q0, [x1, #32] 394; NONEON-NOSVE-NEXT: add sp, sp, #128 395; NONEON-NOSVE-NEXT: ret 396 %op1 = load <16 x half>, ptr %a 397 %res = fpext <16 x half> %op1 to <16 x float> 398 store <16 x float> %res, ptr %b 399 ret void 400} 401 402; 403; FCVT H -> D 404; 405 406define void @fcvt_v1f16_v1f64(ptr %a, ptr %b) { 407; CHECK-LABEL: fcvt_v1f16_v1f64: 408; CHECK: // %bb.0: 409; CHECK-NEXT: ldr h0, [x0] 410; CHECK-NEXT: fcvt d0, h0 411; CHECK-NEXT: str d0, [x1] 412; CHECK-NEXT: ret 413; 414; NONEON-NOSVE-LABEL: fcvt_v1f16_v1f64: 415; NONEON-NOSVE: // %bb.0: 416; NONEON-NOSVE-NEXT: sub sp, sp, #16 417; NONEON-NOSVE-NEXT: .cfi_def_cfa_offset 16 418; NONEON-NOSVE-NEXT: ldr h0, [x0] 419; NONEON-NOSVE-NEXT: fcvt d0, h0 420; NONEON-NOSVE-NEXT: str d0, [sp, #8] 421; NONEON-NOSVE-NEXT: ldr d0, [sp, #8] 422; NONEON-NOSVE-NEXT: str d0, [x1] 423; NONEON-NOSVE-NEXT: add sp, sp, #16 424; NONEON-NOSVE-NEXT: ret 425 %op1 = load <1 x half>, ptr %a 426 %res = fpext <1 x half> %op1 to <1 x double> 427 store <1 x double> %res, ptr %b 428 ret void 429} 430 431define void @fcvt_v2f16_v2f64(ptr %a, ptr %b) { 432; CHECK-LABEL: fcvt_v2f16_v2f64: 433; CHECK: // %bb.0: 434; CHECK-NEXT: ptrue p0.d, vl2 435; CHECK-NEXT: ld1h { z0.d }, p0/z, [x0] 436; CHECK-NEXT: fcvt z0.d, p0/m, z0.h 437; CHECK-NEXT: str q0, [x1] 438; CHECK-NEXT: ret 439; 440; NONEON-NOSVE-LABEL: fcvt_v2f16_v2f64: 441; NONEON-NOSVE: // %bb.0: 442; NONEON-NOSVE-NEXT: ldr w8, [x0] 443; NONEON-NOSVE-NEXT: str w8, [sp, #-48]! 444; NONEON-NOSVE-NEXT: .cfi_def_cfa_offset 48 445; NONEON-NOSVE-NEXT: ldr d0, [sp] 446; NONEON-NOSVE-NEXT: str d0, [sp, #8] 447; NONEON-NOSVE-NEXT: ldr h0, [sp, #10] 448; NONEON-NOSVE-NEXT: fcvt s1, h0 449; NONEON-NOSVE-NEXT: ldr h0, [sp, #8] 450; NONEON-NOSVE-NEXT: fcvt s0, h0 451; NONEON-NOSVE-NEXT: stp s0, s1, [sp, #16] 452; NONEON-NOSVE-NEXT: ldr d0, [sp, #16] 453; NONEON-NOSVE-NEXT: str d0, [sp, #24] 454; NONEON-NOSVE-NEXT: ldr s0, [sp, #28] 455; NONEON-NOSVE-NEXT: fcvt d1, s0 456; NONEON-NOSVE-NEXT: ldr s0, [sp, #24] 457; NONEON-NOSVE-NEXT: fcvt d0, s0 458; NONEON-NOSVE-NEXT: stp d0, d1, [sp, #32] 459; NONEON-NOSVE-NEXT: ldr q0, [sp, #32] 460; NONEON-NOSVE-NEXT: str q0, [x1] 461; NONEON-NOSVE-NEXT: add sp, sp, #48 462; NONEON-NOSVE-NEXT: ret 463 %op1 = load <2 x half>, ptr %a 464 %res = fpext <2 x half> %op1 to <2 x double> 465 store <2 x double> %res, ptr %b 466 ret void 467} 468 469define void @fcvt_v4f16_v4f64(ptr %a, ptr %b) { 470; CHECK-LABEL: fcvt_v4f16_v4f64: 471; CHECK: // %bb.0: 472; CHECK-NEXT: ptrue p0.d, vl2 473; CHECK-NEXT: mov x8, #2 // =0x2 474; CHECK-NEXT: ld1h { z0.d }, p0/z, [x0, x8, lsl #1] 475; CHECK-NEXT: ld1h { z1.d }, p0/z, [x0] 476; CHECK-NEXT: fcvt z0.d, p0/m, z0.h 477; CHECK-NEXT: fcvt z1.d, p0/m, z1.h 478; CHECK-NEXT: stp q1, q0, [x1] 479; CHECK-NEXT: ret 480; 481; NONEON-NOSVE-LABEL: fcvt_v4f16_v4f64: 482; NONEON-NOSVE: // %bb.0: 483; NONEON-NOSVE-NEXT: sub sp, sp, #80 484; NONEON-NOSVE-NEXT: .cfi_def_cfa_offset 80 485; NONEON-NOSVE-NEXT: ldr d0, [x0] 486; NONEON-NOSVE-NEXT: str d0, [sp, #8] 487; NONEON-NOSVE-NEXT: ldr h0, [sp, #10] 488; NONEON-NOSVE-NEXT: fcvt s1, h0 489; NONEON-NOSVE-NEXT: ldr h0, [sp, #8] 490; NONEON-NOSVE-NEXT: fcvt s0, h0 491; NONEON-NOSVE-NEXT: stp s0, s1, [sp, #24] 492; NONEON-NOSVE-NEXT: ldr h0, [sp, #14] 493; NONEON-NOSVE-NEXT: fcvt s1, h0 494; NONEON-NOSVE-NEXT: ldr h0, [sp, #12] 495; NONEON-NOSVE-NEXT: fcvt s0, h0 496; NONEON-NOSVE-NEXT: stp s0, s1, [sp, #16] 497; NONEON-NOSVE-NEXT: ldp d0, d1, [sp, #16] 498; NONEON-NOSVE-NEXT: stp d0, d1, [sp, #32] 499; NONEON-NOSVE-NEXT: ldr s0, [sp, #44] 500; NONEON-NOSVE-NEXT: fcvt d1, s0 501; NONEON-NOSVE-NEXT: ldr s0, [sp, #40] 502; NONEON-NOSVE-NEXT: fcvt d0, s0 503; NONEON-NOSVE-NEXT: stp d0, d1, [sp, #64] 504; NONEON-NOSVE-NEXT: ldr s0, [sp, #36] 505; NONEON-NOSVE-NEXT: fcvt d1, s0 506; NONEON-NOSVE-NEXT: ldr s0, [sp, #32] 507; NONEON-NOSVE-NEXT: fcvt d0, s0 508; NONEON-NOSVE-NEXT: stp d0, d1, [sp, #48] 509; NONEON-NOSVE-NEXT: ldp q0, q1, [sp, #48] 510; NONEON-NOSVE-NEXT: stp q1, q0, [x1] 511; NONEON-NOSVE-NEXT: add sp, sp, #80 512; NONEON-NOSVE-NEXT: ret 513 %op1 = load <4 x half>, ptr %a 514 %res = fpext <4 x half> %op1 to <4 x double> 515 store <4 x double> %res, ptr %b 516 ret void 517} 518 519define void @fcvt_v8f16_v8f64(ptr %a, ptr %b) { 520; CHECK-LABEL: fcvt_v8f16_v8f64: 521; CHECK: // %bb.0: 522; CHECK-NEXT: ptrue p0.d, vl2 523; CHECK-NEXT: mov x8, #4 // =0x4 524; CHECK-NEXT: ld1h { z0.d }, p0/z, [x0, x8, lsl #1] 525; CHECK-NEXT: mov x8, #6 // =0x6 526; CHECK-NEXT: ld1h { z2.d }, p0/z, [x0] 527; CHECK-NEXT: ld1h { z1.d }, p0/z, [x0, x8, lsl #1] 528; CHECK-NEXT: mov x8, #2 // =0x2 529; CHECK-NEXT: ld1h { z3.d }, p0/z, [x0, x8, lsl #1] 530; CHECK-NEXT: fcvt z0.d, p0/m, z0.h 531; CHECK-NEXT: fcvt z2.d, p0/m, z2.h 532; CHECK-NEXT: fcvt z1.d, p0/m, z1.h 533; CHECK-NEXT: fcvt z3.d, p0/m, z3.h 534; CHECK-NEXT: stp q0, q1, [x1, #32] 535; CHECK-NEXT: stp q2, q3, [x1] 536; CHECK-NEXT: ret 537; 538; NONEON-NOSVE-LABEL: fcvt_v8f16_v8f64: 539; NONEON-NOSVE: // %bb.0: 540; NONEON-NOSVE-NEXT: sub sp, sp, #160 541; NONEON-NOSVE-NEXT: .cfi_def_cfa_offset 160 542; NONEON-NOSVE-NEXT: ldr q0, [x0] 543; NONEON-NOSVE-NEXT: str q0, [sp] 544; NONEON-NOSVE-NEXT: ldp d1, d0, [sp] 545; NONEON-NOSVE-NEXT: stp d0, d1, [sp, #16] 546; NONEON-NOSVE-NEXT: ldr h0, [sp, #26] 547; NONEON-NOSVE-NEXT: fcvt s1, h0 548; NONEON-NOSVE-NEXT: ldr h0, [sp, #24] 549; NONEON-NOSVE-NEXT: fcvt s0, h0 550; NONEON-NOSVE-NEXT: stp s0, s1, [sp, #56] 551; NONEON-NOSVE-NEXT: ldr h0, [sp, #30] 552; NONEON-NOSVE-NEXT: fcvt s1, h0 553; NONEON-NOSVE-NEXT: ldr h0, [sp, #28] 554; NONEON-NOSVE-NEXT: fcvt s0, h0 555; NONEON-NOSVE-NEXT: stp s0, s1, [sp, #48] 556; NONEON-NOSVE-NEXT: ldr h0, [sp, #18] 557; NONEON-NOSVE-NEXT: fcvt s1, h0 558; NONEON-NOSVE-NEXT: ldr h0, [sp, #16] 559; NONEON-NOSVE-NEXT: fcvt s0, h0 560; NONEON-NOSVE-NEXT: stp s0, s1, [sp, #40] 561; NONEON-NOSVE-NEXT: ldr h0, [sp, #22] 562; NONEON-NOSVE-NEXT: fcvt s1, h0 563; NONEON-NOSVE-NEXT: ldr h0, [sp, #20] 564; NONEON-NOSVE-NEXT: fcvt s0, h0 565; NONEON-NOSVE-NEXT: stp s0, s1, [sp, #32] 566; NONEON-NOSVE-NEXT: ldp d0, d1, [sp, #48] 567; NONEON-NOSVE-NEXT: stp d0, d1, [sp, #80] 568; NONEON-NOSVE-NEXT: ldp d0, d1, [sp, #32] 569; NONEON-NOSVE-NEXT: stp d0, d1, [sp, #64] 570; NONEON-NOSVE-NEXT: ldr s0, [sp, #92] 571; NONEON-NOSVE-NEXT: fcvt d1, s0 572; NONEON-NOSVE-NEXT: ldr s0, [sp, #88] 573; NONEON-NOSVE-NEXT: fcvt d0, s0 574; NONEON-NOSVE-NEXT: stp d0, d1, [sp, #144] 575; NONEON-NOSVE-NEXT: ldr s0, [sp, #84] 576; NONEON-NOSVE-NEXT: fcvt d1, s0 577; NONEON-NOSVE-NEXT: ldr s0, [sp, #80] 578; NONEON-NOSVE-NEXT: fcvt d0, s0 579; NONEON-NOSVE-NEXT: stp d0, d1, [sp, #128] 580; NONEON-NOSVE-NEXT: ldr s0, [sp, #76] 581; NONEON-NOSVE-NEXT: ldp q3, q2, [sp, #128] 582; NONEON-NOSVE-NEXT: fcvt d1, s0 583; NONEON-NOSVE-NEXT: ldr s0, [sp, #72] 584; NONEON-NOSVE-NEXT: fcvt d0, s0 585; NONEON-NOSVE-NEXT: stp d0, d1, [sp, #112] 586; NONEON-NOSVE-NEXT: ldr s0, [sp, #68] 587; NONEON-NOSVE-NEXT: fcvt d1, s0 588; NONEON-NOSVE-NEXT: ldr s0, [sp, #64] 589; NONEON-NOSVE-NEXT: fcvt d0, s0 590; NONEON-NOSVE-NEXT: stp d0, d1, [sp, #96] 591; NONEON-NOSVE-NEXT: ldp q0, q1, [sp, #96] 592; NONEON-NOSVE-NEXT: stp q2, q3, [x1] 593; NONEON-NOSVE-NEXT: stp q1, q0, [x1, #32] 594; NONEON-NOSVE-NEXT: add sp, sp, #160 595; NONEON-NOSVE-NEXT: ret 596 %op1 = load <8 x half>, ptr %a 597 %res = fpext <8 x half> %op1 to <8 x double> 598 store <8 x double> %res, ptr %b 599 ret void 600} 601 602define void @fcvt_v16f16_v16f64(ptr %a, ptr %b) { 603; CHECK-LABEL: fcvt_v16f16_v16f64: 604; CHECK: // %bb.0: 605; CHECK-NEXT: ptrue p0.d, vl2 606; CHECK-NEXT: mov x8, #12 // =0xc 607; CHECK-NEXT: ld1h { z0.d }, p0/z, [x0, x8, lsl #1] 608; CHECK-NEXT: mov x8, #14 // =0xe 609; CHECK-NEXT: ld1h { z6.d }, p0/z, [x0] 610; CHECK-NEXT: ld1h { z1.d }, p0/z, [x0, x8, lsl #1] 611; CHECK-NEXT: mov x8, #8 // =0x8 612; CHECK-NEXT: ld1h { z2.d }, p0/z, [x0, x8, lsl #1] 613; CHECK-NEXT: mov x8, #10 // =0xa 614; CHECK-NEXT: ld1h { z3.d }, p0/z, [x0, x8, lsl #1] 615; CHECK-NEXT: mov x8, #4 // =0x4 616; CHECK-NEXT: fcvt z0.d, p0/m, z0.h 617; CHECK-NEXT: ld1h { z4.d }, p0/z, [x0, x8, lsl #1] 618; CHECK-NEXT: mov x8, #6 // =0x6 619; CHECK-NEXT: fcvt z1.d, p0/m, z1.h 620; CHECK-NEXT: ld1h { z5.d }, p0/z, [x0, x8, lsl #1] 621; CHECK-NEXT: fcvt z2.d, p0/m, z2.h 622; CHECK-NEXT: mov x8, #2 // =0x2 623; CHECK-NEXT: fcvt z3.d, p0/m, z3.h 624; CHECK-NEXT: ld1h { z7.d }, p0/z, [x0, x8, lsl #1] 625; CHECK-NEXT: fcvt z4.d, p0/m, z4.h 626; CHECK-NEXT: stp q0, q1, [x1, #96] 627; CHECK-NEXT: movprfx z0, z5 628; CHECK-NEXT: fcvt z0.d, p0/m, z5.h 629; CHECK-NEXT: movprfx z1, z6 630; CHECK-NEXT: fcvt z1.d, p0/m, z6.h 631; CHECK-NEXT: stp q2, q3, [x1, #64] 632; CHECK-NEXT: movprfx z2, z7 633; CHECK-NEXT: fcvt z2.d, p0/m, z7.h 634; CHECK-NEXT: stp q4, q0, [x1, #32] 635; CHECK-NEXT: stp q1, q2, [x1] 636; CHECK-NEXT: ret 637; 638; NONEON-NOSVE-LABEL: fcvt_v16f16_v16f64: 639; NONEON-NOSVE: // %bb.0: 640; NONEON-NOSVE-NEXT: sub sp, sp, #336 641; NONEON-NOSVE-NEXT: str x29, [sp, #320] // 8-byte Folded Spill 642; NONEON-NOSVE-NEXT: .cfi_def_cfa_offset 336 643; NONEON-NOSVE-NEXT: .cfi_offset w29, -16 644; NONEON-NOSVE-NEXT: ldp q0, q1, [x0] 645; NONEON-NOSVE-NEXT: ldr x29, [sp, #320] // 8-byte Folded Reload 646; NONEON-NOSVE-NEXT: stp q0, q1, [sp] 647; NONEON-NOSVE-NEXT: ldp d1, d0, [sp] 648; NONEON-NOSVE-NEXT: stp d0, d1, [sp, #40] 649; NONEON-NOSVE-NEXT: ldp d1, d0, [sp, #16] 650; NONEON-NOSVE-NEXT: stp d0, d1, [sp, #56] 651; NONEON-NOSVE-NEXT: ldr h0, [sp, #50] 652; NONEON-NOSVE-NEXT: fcvt s1, h0 653; NONEON-NOSVE-NEXT: ldr h0, [sp, #48] 654; NONEON-NOSVE-NEXT: fcvt s0, h0 655; NONEON-NOSVE-NEXT: stp s0, s1, [sp, #96] 656; NONEON-NOSVE-NEXT: ldr h0, [sp, #54] 657; NONEON-NOSVE-NEXT: fcvt s1, h0 658; NONEON-NOSVE-NEXT: ldr h0, [sp, #52] 659; NONEON-NOSVE-NEXT: fcvt s0, h0 660; NONEON-NOSVE-NEXT: stp s0, s1, [sp, #88] 661; NONEON-NOSVE-NEXT: ldr h0, [sp, #42] 662; NONEON-NOSVE-NEXT: fcvt s1, h0 663; NONEON-NOSVE-NEXT: ldr h0, [sp, #40] 664; NONEON-NOSVE-NEXT: fcvt s0, h0 665; NONEON-NOSVE-NEXT: stp s0, s1, [sp, #80] 666; NONEON-NOSVE-NEXT: ldr h0, [sp, #46] 667; NONEON-NOSVE-NEXT: fcvt s1, h0 668; NONEON-NOSVE-NEXT: ldr h0, [sp, #44] 669; NONEON-NOSVE-NEXT: fcvt s0, h0 670; NONEON-NOSVE-NEXT: stp s0, s1, [sp, #72] 671; NONEON-NOSVE-NEXT: ldr h0, [sp, #66] 672; NONEON-NOSVE-NEXT: fcvt s1, h0 673; NONEON-NOSVE-NEXT: ldr h0, [sp, #64] 674; NONEON-NOSVE-NEXT: fcvt s0, h0 675; NONEON-NOSVE-NEXT: stp s0, s1, [sp, #128] 676; NONEON-NOSVE-NEXT: ldr h0, [sp, #70] 677; NONEON-NOSVE-NEXT: fcvt s1, h0 678; NONEON-NOSVE-NEXT: ldr h0, [sp, #68] 679; NONEON-NOSVE-NEXT: fcvt s0, h0 680; NONEON-NOSVE-NEXT: stp s0, s1, [sp, #120] 681; NONEON-NOSVE-NEXT: ldr h0, [sp, #58] 682; NONEON-NOSVE-NEXT: fcvt s1, h0 683; NONEON-NOSVE-NEXT: ldr h0, [sp, #56] 684; NONEON-NOSVE-NEXT: fcvt s0, h0 685; NONEON-NOSVE-NEXT: stp s0, s1, [sp, #112] 686; NONEON-NOSVE-NEXT: ldr h0, [sp, #62] 687; NONEON-NOSVE-NEXT: fcvt s1, h0 688; NONEON-NOSVE-NEXT: ldr h0, [sp, #60] 689; NONEON-NOSVE-NEXT: fcvt s0, h0 690; NONEON-NOSVE-NEXT: stp s0, s1, [sp, #104] 691; NONEON-NOSVE-NEXT: ldp d0, d1, [sp, #88] 692; NONEON-NOSVE-NEXT: stp d0, d1, [sp, #152] 693; NONEON-NOSVE-NEXT: ldp d0, d1, [sp, #72] 694; NONEON-NOSVE-NEXT: stp d0, d1, [sp, #136] 695; NONEON-NOSVE-NEXT: ldp d2, d1, [sp, #120] 696; NONEON-NOSVE-NEXT: str d1, [sp, #328] 697; NONEON-NOSVE-NEXT: ldp d0, d1, [sp, #104] 698; NONEON-NOSVE-NEXT: str d0, [sp, #168] 699; NONEON-NOSVE-NEXT: ldr s0, [sp, #164] 700; NONEON-NOSVE-NEXT: stp d1, d2, [sp, #176] 701; NONEON-NOSVE-NEXT: fcvt d1, s0 702; NONEON-NOSVE-NEXT: ldr s0, [sp, #160] 703; NONEON-NOSVE-NEXT: fcvt d0, s0 704; NONEON-NOSVE-NEXT: stp d0, d1, [sp, #240] 705; NONEON-NOSVE-NEXT: ldr s0, [sp, #156] 706; NONEON-NOSVE-NEXT: fcvt d1, s0 707; NONEON-NOSVE-NEXT: ldr s0, [sp, #152] 708; NONEON-NOSVE-NEXT: fcvt d0, s0 709; NONEON-NOSVE-NEXT: stp d0, d1, [sp, #224] 710; NONEON-NOSVE-NEXT: ldr s0, [sp, #148] 711; NONEON-NOSVE-NEXT: fcvt d1, s0 712; NONEON-NOSVE-NEXT: ldr s0, [sp, #144] 713; NONEON-NOSVE-NEXT: fcvt d0, s0 714; NONEON-NOSVE-NEXT: stp d0, d1, [sp, #208] 715; NONEON-NOSVE-NEXT: ldr s0, [sp, #140] 716; NONEON-NOSVE-NEXT: fcvt d1, s0 717; NONEON-NOSVE-NEXT: ldr s0, [sp, #136] 718; NONEON-NOSVE-NEXT: fcvt d0, s0 719; NONEON-NOSVE-NEXT: stp d0, d1, [sp, #192] 720; NONEON-NOSVE-NEXT: ldr s0, [sp, #332] 721; NONEON-NOSVE-NEXT: ldp q4, q3, [sp, #192] 722; NONEON-NOSVE-NEXT: fcvt d1, s0 723; NONEON-NOSVE-NEXT: ldr s0, [sp, #328] 724; NONEON-NOSVE-NEXT: fcvt d0, s0 725; NONEON-NOSVE-NEXT: stp d0, d1, [sp, #304] 726; NONEON-NOSVE-NEXT: ldr s0, [sp, #188] 727; NONEON-NOSVE-NEXT: fcvt d1, s0 728; NONEON-NOSVE-NEXT: ldr s0, [sp, #184] 729; NONEON-NOSVE-NEXT: fcvt d0, s0 730; NONEON-NOSVE-NEXT: stp d0, d1, [sp, #288] 731; NONEON-NOSVE-NEXT: ldr s0, [sp, #180] 732; NONEON-NOSVE-NEXT: ldp q7, q6, [sp, #288] 733; NONEON-NOSVE-NEXT: fcvt d1, s0 734; NONEON-NOSVE-NEXT: ldr s0, [sp, #176] 735; NONEON-NOSVE-NEXT: fcvt d0, s0 736; NONEON-NOSVE-NEXT: stp d0, d1, [sp, #272] 737; NONEON-NOSVE-NEXT: ldr s0, [sp, #172] 738; NONEON-NOSVE-NEXT: fcvt d1, s0 739; NONEON-NOSVE-NEXT: ldr s0, [sp, #168] 740; NONEON-NOSVE-NEXT: fcvt d0, s0 741; NONEON-NOSVE-NEXT: stp d0, d1, [sp, #256] 742; NONEON-NOSVE-NEXT: ldp q1, q0, [sp, #224] 743; NONEON-NOSVE-NEXT: ldp q2, q5, [sp, #256] 744; NONEON-NOSVE-NEXT: stp q3, q4, [x1, #32] 745; NONEON-NOSVE-NEXT: stp q6, q7, [x1, #64] 746; NONEON-NOSVE-NEXT: stp q0, q1, [x1] 747; NONEON-NOSVE-NEXT: stp q5, q2, [x1, #96] 748; NONEON-NOSVE-NEXT: add sp, sp, #336 749; NONEON-NOSVE-NEXT: ret 750 %op1 = load <16 x half>, ptr %a 751 %res = fpext <16 x half> %op1 to <16 x double> 752 store <16 x double> %res, ptr %b 753 ret void 754} 755 756; 757; FCVT S -> D 758; 759 760define void @fcvt_v1f32_v1f64(ptr %a, ptr %b) { 761; CHECK-LABEL: fcvt_v1f32_v1f64: 762; CHECK: // %bb.0: 763; CHECK-NEXT: ldr s0, [x0] 764; CHECK-NEXT: fcvt d0, s0 765; CHECK-NEXT: str d0, [x1] 766; CHECK-NEXT: ret 767; 768; NONEON-NOSVE-LABEL: fcvt_v1f32_v1f64: 769; NONEON-NOSVE: // %bb.0: 770; NONEON-NOSVE-NEXT: ldr s0, [x0] 771; NONEON-NOSVE-NEXT: fcvt d0, s0 772; NONEON-NOSVE-NEXT: str d0, [x1] 773; NONEON-NOSVE-NEXT: ret 774 %op1 = load <1 x float>, ptr %a 775 %res = fpext <1 x float> %op1 to <1 x double> 776 store <1 x double> %res, ptr %b 777 ret void 778} 779 780define void @fcvt_v2f32_v2f64(ptr %a, ptr %b) { 781; CHECK-LABEL: fcvt_v2f32_v2f64: 782; CHECK: // %bb.0: 783; CHECK-NEXT: ptrue p0.d, vl2 784; CHECK-NEXT: ld1w { z0.d }, p0/z, [x0] 785; CHECK-NEXT: fcvt z0.d, p0/m, z0.s 786; CHECK-NEXT: str q0, [x1] 787; CHECK-NEXT: ret 788; 789; NONEON-NOSVE-LABEL: fcvt_v2f32_v2f64: 790; NONEON-NOSVE: // %bb.0: 791; NONEON-NOSVE-NEXT: sub sp, sp, #32 792; NONEON-NOSVE-NEXT: .cfi_def_cfa_offset 32 793; NONEON-NOSVE-NEXT: ldr d0, [x0] 794; NONEON-NOSVE-NEXT: str d0, [sp, #8] 795; NONEON-NOSVE-NEXT: ldr s0, [sp, #12] 796; NONEON-NOSVE-NEXT: fcvt d1, s0 797; NONEON-NOSVE-NEXT: ldr s0, [sp, #8] 798; NONEON-NOSVE-NEXT: fcvt d0, s0 799; NONEON-NOSVE-NEXT: stp d0, d1, [sp, #16] 800; NONEON-NOSVE-NEXT: ldr q0, [sp, #16] 801; NONEON-NOSVE-NEXT: str q0, [x1] 802; NONEON-NOSVE-NEXT: add sp, sp, #32 803; NONEON-NOSVE-NEXT: ret 804 %op1 = load <2 x float>, ptr %a 805 %res = fpext <2 x float> %op1 to <2 x double> 806 store <2 x double> %res, ptr %b 807 ret void 808} 809 810define void @fcvt_v4f32_v4f64(ptr %a, ptr %b) { 811; CHECK-LABEL: fcvt_v4f32_v4f64: 812; CHECK: // %bb.0: 813; CHECK-NEXT: ptrue p0.d, vl2 814; CHECK-NEXT: mov x8, #2 // =0x2 815; CHECK-NEXT: ld1w { z0.d }, p0/z, [x0, x8, lsl #2] 816; CHECK-NEXT: ld1w { z1.d }, p0/z, [x0] 817; CHECK-NEXT: fcvt z0.d, p0/m, z0.s 818; CHECK-NEXT: fcvt z1.d, p0/m, z1.s 819; CHECK-NEXT: stp q1, q0, [x1] 820; CHECK-NEXT: ret 821; 822; NONEON-NOSVE-LABEL: fcvt_v4f32_v4f64: 823; NONEON-NOSVE: // %bb.0: 824; NONEON-NOSVE-NEXT: ldr q0, [x0] 825; NONEON-NOSVE-NEXT: str q0, [sp, #-64]! 826; NONEON-NOSVE-NEXT: .cfi_def_cfa_offset 64 827; NONEON-NOSVE-NEXT: ldp d1, d0, [sp] 828; NONEON-NOSVE-NEXT: stp d0, d1, [sp, #16] 829; NONEON-NOSVE-NEXT: ldr s0, [sp, #28] 830; NONEON-NOSVE-NEXT: fcvt d1, s0 831; NONEON-NOSVE-NEXT: ldr s0, [sp, #24] 832; NONEON-NOSVE-NEXT: fcvt d0, s0 833; NONEON-NOSVE-NEXT: stp d0, d1, [sp, #48] 834; NONEON-NOSVE-NEXT: ldr s0, [sp, #20] 835; NONEON-NOSVE-NEXT: fcvt d1, s0 836; NONEON-NOSVE-NEXT: ldr s0, [sp, #16] 837; NONEON-NOSVE-NEXT: fcvt d0, s0 838; NONEON-NOSVE-NEXT: stp d0, d1, [sp, #32] 839; NONEON-NOSVE-NEXT: ldp q0, q1, [sp, #32] 840; NONEON-NOSVE-NEXT: stp q1, q0, [x1] 841; NONEON-NOSVE-NEXT: add sp, sp, #64 842; NONEON-NOSVE-NEXT: ret 843 %op1 = load <4 x float>, ptr %a 844 %res = fpext <4 x float> %op1 to <4 x double> 845 store <4 x double> %res, ptr %b 846 ret void 847} 848 849define void @fcvt_v8f32_v8f64(ptr %a, ptr %b) { 850; CHECK-LABEL: fcvt_v8f32_v8f64: 851; CHECK: // %bb.0: 852; CHECK-NEXT: ptrue p0.d, vl2 853; CHECK-NEXT: mov x8, #4 // =0x4 854; CHECK-NEXT: ld1w { z0.d }, p0/z, [x0, x8, lsl #2] 855; CHECK-NEXT: mov x8, #6 // =0x6 856; CHECK-NEXT: ld1w { z2.d }, p0/z, [x0] 857; CHECK-NEXT: ld1w { z1.d }, p0/z, [x0, x8, lsl #2] 858; CHECK-NEXT: mov x8, #2 // =0x2 859; CHECK-NEXT: ld1w { z3.d }, p0/z, [x0, x8, lsl #2] 860; CHECK-NEXT: fcvt z0.d, p0/m, z0.s 861; CHECK-NEXT: fcvt z2.d, p0/m, z2.s 862; CHECK-NEXT: fcvt z1.d, p0/m, z1.s 863; CHECK-NEXT: fcvt z3.d, p0/m, z3.s 864; CHECK-NEXT: stp q0, q1, [x1, #32] 865; CHECK-NEXT: stp q2, q3, [x1] 866; CHECK-NEXT: ret 867; 868; NONEON-NOSVE-LABEL: fcvt_v8f32_v8f64: 869; NONEON-NOSVE: // %bb.0: 870; NONEON-NOSVE-NEXT: ldp q0, q1, [x0] 871; NONEON-NOSVE-NEXT: stp q0, q1, [sp, #-128]! 872; NONEON-NOSVE-NEXT: .cfi_def_cfa_offset 128 873; NONEON-NOSVE-NEXT: ldp d1, d0, [sp] 874; NONEON-NOSVE-NEXT: stp d0, d1, [sp, #32] 875; NONEON-NOSVE-NEXT: ldp d1, d0, [sp, #16] 876; NONEON-NOSVE-NEXT: stp d0, d1, [sp, #48] 877; NONEON-NOSVE-NEXT: ldr s0, [sp, #44] 878; NONEON-NOSVE-NEXT: fcvt d1, s0 879; NONEON-NOSVE-NEXT: ldr s0, [sp, #40] 880; NONEON-NOSVE-NEXT: fcvt d0, s0 881; NONEON-NOSVE-NEXT: stp d0, d1, [sp, #80] 882; NONEON-NOSVE-NEXT: ldr s0, [sp, #36] 883; NONEON-NOSVE-NEXT: fcvt d1, s0 884; NONEON-NOSVE-NEXT: ldr s0, [sp, #32] 885; NONEON-NOSVE-NEXT: fcvt d0, s0 886; NONEON-NOSVE-NEXT: stp d0, d1, [sp, #64] 887; NONEON-NOSVE-NEXT: ldr s0, [sp, #60] 888; NONEON-NOSVE-NEXT: ldp q3, q2, [sp, #64] 889; NONEON-NOSVE-NEXT: fcvt d1, s0 890; NONEON-NOSVE-NEXT: ldr s0, [sp, #56] 891; NONEON-NOSVE-NEXT: fcvt d0, s0 892; NONEON-NOSVE-NEXT: stp d0, d1, [sp, #112] 893; NONEON-NOSVE-NEXT: ldr s0, [sp, #52] 894; NONEON-NOSVE-NEXT: fcvt d1, s0 895; NONEON-NOSVE-NEXT: ldr s0, [sp, #48] 896; NONEON-NOSVE-NEXT: fcvt d0, s0 897; NONEON-NOSVE-NEXT: stp d0, d1, [sp, #96] 898; NONEON-NOSVE-NEXT: ldp q0, q1, [sp, #96] 899; NONEON-NOSVE-NEXT: stp q2, q3, [x1] 900; NONEON-NOSVE-NEXT: stp q1, q0, [x1, #32] 901; NONEON-NOSVE-NEXT: add sp, sp, #128 902; NONEON-NOSVE-NEXT: ret 903 %op1 = load <8 x float>, ptr %a 904 %res = fpext <8 x float> %op1 to <8 x double> 905 store <8 x double> %res, ptr %b 906 ret void 907} 908 909; 910; FCVT S -> H 911; 912 913define void @fcvt_v2f32_v2f16(ptr %a, ptr %b) { 914; CHECK-LABEL: fcvt_v2f32_v2f16: 915; CHECK: // %bb.0: 916; CHECK-NEXT: ptrue p0.s, vl2 917; CHECK-NEXT: ldr d0, [x0] 918; CHECK-NEXT: fcvt z0.h, p0/m, z0.s 919; CHECK-NEXT: st1h { z0.s }, p0, [x1] 920; CHECK-NEXT: ret 921; 922; NONEON-NOSVE-LABEL: fcvt_v2f32_v2f16: 923; NONEON-NOSVE: // %bb.0: 924; NONEON-NOSVE-NEXT: sub sp, sp, #32 925; NONEON-NOSVE-NEXT: .cfi_def_cfa_offset 32 926; NONEON-NOSVE-NEXT: ldr d0, [x0] 927; NONEON-NOSVE-NEXT: str d0, [sp, #8] 928; NONEON-NOSVE-NEXT: ldr s0, [sp, #12] 929; NONEON-NOSVE-NEXT: fcvt h0, s0 930; NONEON-NOSVE-NEXT: str h0, [sp, #18] 931; NONEON-NOSVE-NEXT: ldr s0, [sp, #8] 932; NONEON-NOSVE-NEXT: fcvt h0, s0 933; NONEON-NOSVE-NEXT: str h0, [sp, #16] 934; NONEON-NOSVE-NEXT: ldr d0, [sp, #16] 935; NONEON-NOSVE-NEXT: str d0, [sp, #24] 936; NONEON-NOSVE-NEXT: ldr w8, [sp, #24] 937; NONEON-NOSVE-NEXT: str w8, [x1] 938; NONEON-NOSVE-NEXT: add sp, sp, #32 939; NONEON-NOSVE-NEXT: ret 940 %op1 = load <2 x float>, ptr %a 941 %res = fptrunc <2 x float> %op1 to <2 x half> 942 store <2 x half> %res, ptr %b 943 ret void 944} 945 946define void @fcvt_v4f32_v4f16(ptr %a, ptr %b) { 947; CHECK-LABEL: fcvt_v4f32_v4f16: 948; CHECK: // %bb.0: 949; CHECK-NEXT: ptrue p0.s, vl4 950; CHECK-NEXT: ldr q0, [x0] 951; CHECK-NEXT: fcvt z0.h, p0/m, z0.s 952; CHECK-NEXT: st1h { z0.s }, p0, [x1] 953; CHECK-NEXT: ret 954; 955; NONEON-NOSVE-LABEL: fcvt_v4f32_v4f16: 956; NONEON-NOSVE: // %bb.0: 957; NONEON-NOSVE-NEXT: ldr q0, [x0] 958; NONEON-NOSVE-NEXT: str q0, [sp, #-32]! 959; NONEON-NOSVE-NEXT: .cfi_def_cfa_offset 32 960; NONEON-NOSVE-NEXT: ldr s0, [sp, #12] 961; NONEON-NOSVE-NEXT: fcvt h0, s0 962; NONEON-NOSVE-NEXT: str h0, [sp, #30] 963; NONEON-NOSVE-NEXT: ldr s0, [sp, #8] 964; NONEON-NOSVE-NEXT: fcvt h0, s0 965; NONEON-NOSVE-NEXT: str h0, [sp, #28] 966; NONEON-NOSVE-NEXT: ldr s0, [sp, #4] 967; NONEON-NOSVE-NEXT: fcvt h0, s0 968; NONEON-NOSVE-NEXT: str h0, [sp, #26] 969; NONEON-NOSVE-NEXT: ldr s0, [sp] 970; NONEON-NOSVE-NEXT: fcvt h0, s0 971; NONEON-NOSVE-NEXT: str h0, [sp, #24] 972; NONEON-NOSVE-NEXT: ldr d0, [sp, #24] 973; NONEON-NOSVE-NEXT: str d0, [x1] 974; NONEON-NOSVE-NEXT: add sp, sp, #32 975; NONEON-NOSVE-NEXT: ret 976 %op1 = load <4 x float>, ptr %a 977 %res = fptrunc <4 x float> %op1 to <4 x half> 978 store <4 x half> %res, ptr %b 979 ret void 980} 981 982define void @fcvt_v8f32_v8f16(ptr %a, ptr %b) { 983; CHECK-LABEL: fcvt_v8f32_v8f16: 984; CHECK: // %bb.0: 985; CHECK-NEXT: ldp q1, q0, [x0] 986; CHECK-NEXT: ptrue p0.s, vl4 987; CHECK-NEXT: mov x8, #4 // =0x4 988; CHECK-NEXT: fcvt z0.h, p0/m, z0.s 989; CHECK-NEXT: fcvt z1.h, p0/m, z1.s 990; CHECK-NEXT: st1h { z0.s }, p0, [x1, x8, lsl #1] 991; CHECK-NEXT: st1h { z1.s }, p0, [x1] 992; CHECK-NEXT: ret 993; 994; NONEON-NOSVE-LABEL: fcvt_v8f32_v8f16: 995; NONEON-NOSVE: // %bb.0: 996; NONEON-NOSVE-NEXT: ldp q1, q0, [x0] 997; NONEON-NOSVE-NEXT: stp q1, q0, [sp, #-48]! 998; NONEON-NOSVE-NEXT: .cfi_def_cfa_offset 48 999; NONEON-NOSVE-NEXT: ldr s0, [sp, #28] 1000; NONEON-NOSVE-NEXT: fcvt h0, s0 1001; NONEON-NOSVE-NEXT: str h0, [sp, #46] 1002; NONEON-NOSVE-NEXT: ldr s0, [sp, #24] 1003; NONEON-NOSVE-NEXT: fcvt h0, s0 1004; NONEON-NOSVE-NEXT: str h0, [sp, #44] 1005; NONEON-NOSVE-NEXT: ldr s0, [sp, #20] 1006; NONEON-NOSVE-NEXT: fcvt h0, s0 1007; NONEON-NOSVE-NEXT: str h0, [sp, #42] 1008; NONEON-NOSVE-NEXT: ldr s0, [sp, #16] 1009; NONEON-NOSVE-NEXT: fcvt h0, s0 1010; NONEON-NOSVE-NEXT: str h0, [sp, #40] 1011; NONEON-NOSVE-NEXT: ldr s0, [sp, #12] 1012; NONEON-NOSVE-NEXT: fcvt h0, s0 1013; NONEON-NOSVE-NEXT: str h0, [sp, #38] 1014; NONEON-NOSVE-NEXT: ldr s0, [sp, #8] 1015; NONEON-NOSVE-NEXT: fcvt h0, s0 1016; NONEON-NOSVE-NEXT: str h0, [sp, #36] 1017; NONEON-NOSVE-NEXT: ldr s0, [sp, #4] 1018; NONEON-NOSVE-NEXT: fcvt h0, s0 1019; NONEON-NOSVE-NEXT: str h0, [sp, #34] 1020; NONEON-NOSVE-NEXT: ldr s0, [sp] 1021; NONEON-NOSVE-NEXT: fcvt h0, s0 1022; NONEON-NOSVE-NEXT: str h0, [sp, #32] 1023; NONEON-NOSVE-NEXT: ldr q0, [sp, #32] 1024; NONEON-NOSVE-NEXT: str q0, [x1] 1025; NONEON-NOSVE-NEXT: add sp, sp, #48 1026; NONEON-NOSVE-NEXT: ret 1027 %op1 = load <8 x float>, ptr %a 1028 %res = fptrunc <8 x float> %op1 to <8 x half> 1029 store <8 x half> %res, ptr %b 1030 ret void 1031} 1032 1033; 1034; FCVT D -> H 1035; 1036 1037define void @fcvt_v1f64_v1f16(ptr %a, ptr %b) { 1038; CHECK-LABEL: fcvt_v1f64_v1f16: 1039; CHECK: // %bb.0: 1040; CHECK-NEXT: ptrue p0.d, vl1 1041; CHECK-NEXT: ldr d0, [x0] 1042; CHECK-NEXT: fcvt z0.h, p0/m, z0.d 1043; CHECK-NEXT: st1h { z0.d }, p0, [x1] 1044; CHECK-NEXT: ret 1045; 1046; NONEON-NOSVE-LABEL: fcvt_v1f64_v1f16: 1047; NONEON-NOSVE: // %bb.0: 1048; NONEON-NOSVE-NEXT: ldr d0, [x0] 1049; NONEON-NOSVE-NEXT: fcvt h0, d0 1050; NONEON-NOSVE-NEXT: str h0, [x1] 1051; NONEON-NOSVE-NEXT: ret 1052 %op1 = load <1 x double>, ptr %a 1053 %res = fptrunc <1 x double> %op1 to <1 x half> 1054 store <1 x half> %res, ptr %b 1055 ret void 1056} 1057 1058define void @fcvt_v2f64_v2f16(ptr %a, ptr %b) { 1059; CHECK-LABEL: fcvt_v2f64_v2f16: 1060; CHECK: // %bb.0: 1061; CHECK-NEXT: ptrue p0.d, vl2 1062; CHECK-NEXT: ldr q0, [x0] 1063; CHECK-NEXT: fcvt z0.h, p0/m, z0.d 1064; CHECK-NEXT: st1h { z0.d }, p0, [x1] 1065; CHECK-NEXT: ret 1066; 1067; NONEON-NOSVE-LABEL: fcvt_v2f64_v2f16: 1068; NONEON-NOSVE: // %bb.0: 1069; NONEON-NOSVE-NEXT: ldr q0, [x0] 1070; NONEON-NOSVE-NEXT: str q0, [sp, #-32]! 1071; NONEON-NOSVE-NEXT: .cfi_def_cfa_offset 32 1072; NONEON-NOSVE-NEXT: ldr d0, [sp, #8] 1073; NONEON-NOSVE-NEXT: fcvt h0, d0 1074; NONEON-NOSVE-NEXT: str h0, [sp, #18] 1075; NONEON-NOSVE-NEXT: ldr d0, [sp] 1076; NONEON-NOSVE-NEXT: fcvt h0, d0 1077; NONEON-NOSVE-NEXT: str h0, [sp, #16] 1078; NONEON-NOSVE-NEXT: ldr d0, [sp, #16] 1079; NONEON-NOSVE-NEXT: str d0, [sp, #24] 1080; NONEON-NOSVE-NEXT: ldr w8, [sp, #24] 1081; NONEON-NOSVE-NEXT: str w8, [x1] 1082; NONEON-NOSVE-NEXT: add sp, sp, #32 1083; NONEON-NOSVE-NEXT: ret 1084 %op1 = load <2 x double>, ptr %a 1085 %res = fptrunc <2 x double> %op1 to <2 x half> 1086 store <2 x half> %res, ptr %b 1087 ret void 1088} 1089 1090define void @fcvt_v4f64_v4f16(ptr %a, ptr %b) { 1091; CHECK-LABEL: fcvt_v4f64_v4f16: 1092; CHECK: // %bb.0: 1093; CHECK-NEXT: ldp q1, q0, [x0] 1094; CHECK-NEXT: ptrue p0.d, vl2 1095; CHECK-NEXT: mov x8, #2 // =0x2 1096; CHECK-NEXT: fcvt z0.h, p0/m, z0.d 1097; CHECK-NEXT: fcvt z1.h, p0/m, z1.d 1098; CHECK-NEXT: st1h { z0.d }, p0, [x1, x8, lsl #1] 1099; CHECK-NEXT: st1h { z1.d }, p0, [x1] 1100; CHECK-NEXT: ret 1101; 1102; NONEON-NOSVE-LABEL: fcvt_v4f64_v4f16: 1103; NONEON-NOSVE: // %bb.0: 1104; NONEON-NOSVE-NEXT: ldp q1, q0, [x0] 1105; NONEON-NOSVE-NEXT: stp q1, q0, [sp, #-48]! 1106; NONEON-NOSVE-NEXT: .cfi_def_cfa_offset 48 1107; NONEON-NOSVE-NEXT: ldr d0, [sp, #24] 1108; NONEON-NOSVE-NEXT: fcvt h0, d0 1109; NONEON-NOSVE-NEXT: str h0, [sp, #46] 1110; NONEON-NOSVE-NEXT: ldr d0, [sp, #16] 1111; NONEON-NOSVE-NEXT: fcvt h0, d0 1112; NONEON-NOSVE-NEXT: str h0, [sp, #44] 1113; NONEON-NOSVE-NEXT: ldr d0, [sp, #8] 1114; NONEON-NOSVE-NEXT: fcvt h0, d0 1115; NONEON-NOSVE-NEXT: str h0, [sp, #42] 1116; NONEON-NOSVE-NEXT: ldr d0, [sp] 1117; NONEON-NOSVE-NEXT: fcvt h0, d0 1118; NONEON-NOSVE-NEXT: str h0, [sp, #40] 1119; NONEON-NOSVE-NEXT: ldr d0, [sp, #40] 1120; NONEON-NOSVE-NEXT: str d0, [x1] 1121; NONEON-NOSVE-NEXT: add sp, sp, #48 1122; NONEON-NOSVE-NEXT: ret 1123 %op1 = load <4 x double>, ptr %a 1124 %res = fptrunc <4 x double> %op1 to <4 x half> 1125 store <4 x half> %res, ptr %b 1126 ret void 1127} 1128 1129; 1130; FCVT D -> S 1131; 1132 1133define void @fcvt_v1f64_v1f32(<1 x double> %op1, ptr %b) { 1134; CHECK-LABEL: fcvt_v1f64_v1f32: 1135; CHECK: // %bb.0: 1136; CHECK-NEXT: ptrue p0.d, vl1 1137; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0 1138; CHECK-NEXT: fcvt z0.s, p0/m, z0.d 1139; CHECK-NEXT: st1w { z0.d }, p0, [x0] 1140; CHECK-NEXT: ret 1141; 1142; NONEON-NOSVE-LABEL: fcvt_v1f64_v1f32: 1143; NONEON-NOSVE: // %bb.0: 1144; NONEON-NOSVE-NEXT: fcvt s0, d0 1145; NONEON-NOSVE-NEXT: str s0, [x0] 1146; NONEON-NOSVE-NEXT: ret 1147 %res = fptrunc <1 x double> %op1 to <1 x float> 1148 store <1 x float> %res, ptr %b 1149 ret void 1150} 1151 1152define void @fcvt_v2f64_v2f32(<2 x double> %op1, ptr %b) { 1153; CHECK-LABEL: fcvt_v2f64_v2f32: 1154; CHECK: // %bb.0: 1155; CHECK-NEXT: ptrue p0.d, vl2 1156; CHECK-NEXT: // kill: def $q0 killed $q0 def $z0 1157; CHECK-NEXT: fcvt z0.s, p0/m, z0.d 1158; CHECK-NEXT: st1w { z0.d }, p0, [x0] 1159; CHECK-NEXT: ret 1160; 1161; NONEON-NOSVE-LABEL: fcvt_v2f64_v2f32: 1162; NONEON-NOSVE: // %bb.0: 1163; NONEON-NOSVE-NEXT: str q0, [sp, #-32]! 1164; NONEON-NOSVE-NEXT: .cfi_def_cfa_offset 32 1165; NONEON-NOSVE-NEXT: ldr d0, [sp, #8] 1166; NONEON-NOSVE-NEXT: fcvt s1, d0 1167; NONEON-NOSVE-NEXT: ldr d0, [sp] 1168; NONEON-NOSVE-NEXT: fcvt s0, d0 1169; NONEON-NOSVE-NEXT: stp s0, s1, [sp, #24] 1170; NONEON-NOSVE-NEXT: ldr d0, [sp, #24] 1171; NONEON-NOSVE-NEXT: str d0, [x0] 1172; NONEON-NOSVE-NEXT: add sp, sp, #32 1173; NONEON-NOSVE-NEXT: ret 1174 %res = fptrunc <2 x double> %op1 to <2 x float> 1175 store <2 x float> %res, ptr %b 1176 ret void 1177} 1178 1179define void @fcvt_v4f64_v4f32(ptr %a, ptr %b) { 1180; CHECK-LABEL: fcvt_v4f64_v4f32: 1181; CHECK: // %bb.0: 1182; CHECK-NEXT: ldp q1, q0, [x0] 1183; CHECK-NEXT: ptrue p0.d, vl2 1184; CHECK-NEXT: mov x8, #2 // =0x2 1185; CHECK-NEXT: fcvt z0.s, p0/m, z0.d 1186; CHECK-NEXT: fcvt z1.s, p0/m, z1.d 1187; CHECK-NEXT: st1w { z0.d }, p0, [x1, x8, lsl #2] 1188; CHECK-NEXT: st1w { z1.d }, p0, [x1] 1189; CHECK-NEXT: ret 1190; 1191; NONEON-NOSVE-LABEL: fcvt_v4f64_v4f32: 1192; NONEON-NOSVE: // %bb.0: 1193; NONEON-NOSVE-NEXT: ldp q1, q0, [x0] 1194; NONEON-NOSVE-NEXT: stp q1, q0, [sp, #-48]! 1195; NONEON-NOSVE-NEXT: .cfi_def_cfa_offset 48 1196; NONEON-NOSVE-NEXT: ldr d0, [sp, #24] 1197; NONEON-NOSVE-NEXT: fcvt s1, d0 1198; NONEON-NOSVE-NEXT: ldr d0, [sp, #16] 1199; NONEON-NOSVE-NEXT: fcvt s0, d0 1200; NONEON-NOSVE-NEXT: stp s0, s1, [sp, #40] 1201; NONEON-NOSVE-NEXT: ldr d0, [sp, #8] 1202; NONEON-NOSVE-NEXT: fcvt s1, d0 1203; NONEON-NOSVE-NEXT: ldr d0, [sp] 1204; NONEON-NOSVE-NEXT: fcvt s0, d0 1205; NONEON-NOSVE-NEXT: stp s0, s1, [sp, #32] 1206; NONEON-NOSVE-NEXT: ldr q0, [sp, #32] 1207; NONEON-NOSVE-NEXT: str q0, [x1] 1208; NONEON-NOSVE-NEXT: add sp, sp, #48 1209; NONEON-NOSVE-NEXT: ret 1210 %op1 = load <4 x double>, ptr %a 1211 %res = fptrunc <4 x double> %op1 to <4 x float> 1212 store <4 x float> %res, ptr %b 1213 ret void 1214} 1215