xref: /llvm-project/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-extract-subvector.ll (revision 61510b51c33464a6bc15e4cf5b1ee07e2e0ec1c9) 
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mattr=+sve -force-streaming-compatible  < %s | FileCheck %s
3; RUN: llc -mattr=+sme -force-streaming  < %s | FileCheck %s
4; RUN: llc -force-streaming-compatible < %s | FileCheck %s --check-prefix=NONEON-NOSVE
5
6target triple = "aarch64-unknown-linux-gnu"
7
8; i1
9
10define <4 x i1> @extract_subvector_v8i1(<8 x i1> %op) {
11; CHECK-LABEL: extract_subvector_v8i1:
12; CHECK:       // %bb.0:
13; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
14; CHECK-NEXT:    mov z1.b, z0.b[7]
15; CHECK-NEXT:    mov z2.b, z0.b[6]
16; CHECK-NEXT:    mov z3.b, z0.b[5]
17; CHECK-NEXT:    mov z0.b, z0.b[4]
18; CHECK-NEXT:    zip1 z1.h, z2.h, z1.h
19; CHECK-NEXT:    zip1 z0.h, z0.h, z3.h
20; CHECK-NEXT:    zip1 z0.s, z0.s, z1.s
21; CHECK-NEXT:    // kill: def $d0 killed $d0 killed $z0
22; CHECK-NEXT:    ret
23;
24; NONEON-NOSVE-LABEL: extract_subvector_v8i1:
25; NONEON-NOSVE:       // %bb.0:
26; NONEON-NOSVE-NEXT:    str d0, [sp, #-16]!
27; NONEON-NOSVE-NEXT:    .cfi_def_cfa_offset 16
28; NONEON-NOSVE-NEXT:    ldrb w8, [sp, #7]
29; NONEON-NOSVE-NEXT:    strh w8, [sp, #14]
30; NONEON-NOSVE-NEXT:    ldrb w8, [sp, #6]
31; NONEON-NOSVE-NEXT:    strh w8, [sp, #12]
32; NONEON-NOSVE-NEXT:    ldrb w8, [sp, #5]
33; NONEON-NOSVE-NEXT:    strh w8, [sp, #10]
34; NONEON-NOSVE-NEXT:    ldrb w8, [sp, #4]
35; NONEON-NOSVE-NEXT:    strh w8, [sp, #8]
36; NONEON-NOSVE-NEXT:    ldr d0, [sp, #8]
37; NONEON-NOSVE-NEXT:    add sp, sp, #16
38; NONEON-NOSVE-NEXT:    ret
39  %ret = call <4 x i1> @llvm.vector.extract.v4i1.v8i1(<8 x i1> %op, i64 4)
40  ret <4 x i1> %ret
41}
42
43; i8
44
45define <4 x i8> @extract_subvector_v8i8(<8 x i8> %op) {
46; CHECK-LABEL: extract_subvector_v8i8:
47; CHECK:       // %bb.0:
48; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
49; CHECK-NEXT:    mov z1.b, z0.b[7]
50; CHECK-NEXT:    mov z2.b, z0.b[6]
51; CHECK-NEXT:    mov z3.b, z0.b[5]
52; CHECK-NEXT:    mov z0.b, z0.b[4]
53; CHECK-NEXT:    zip1 z1.h, z2.h, z1.h
54; CHECK-NEXT:    zip1 z0.h, z0.h, z3.h
55; CHECK-NEXT:    zip1 z0.s, z0.s, z1.s
56; CHECK-NEXT:    // kill: def $d0 killed $d0 killed $z0
57; CHECK-NEXT:    ret
58;
59; NONEON-NOSVE-LABEL: extract_subvector_v8i8:
60; NONEON-NOSVE:       // %bb.0:
61; NONEON-NOSVE-NEXT:    str d0, [sp, #-16]!
62; NONEON-NOSVE-NEXT:    .cfi_def_cfa_offset 16
63; NONEON-NOSVE-NEXT:    ldrb w8, [sp, #7]
64; NONEON-NOSVE-NEXT:    strh w8, [sp, #14]
65; NONEON-NOSVE-NEXT:    ldrb w8, [sp, #6]
66; NONEON-NOSVE-NEXT:    strh w8, [sp, #12]
67; NONEON-NOSVE-NEXT:    ldrb w8, [sp, #5]
68; NONEON-NOSVE-NEXT:    strh w8, [sp, #10]
69; NONEON-NOSVE-NEXT:    ldrb w8, [sp, #4]
70; NONEON-NOSVE-NEXT:    strh w8, [sp, #8]
71; NONEON-NOSVE-NEXT:    ldr d0, [sp, #8]
72; NONEON-NOSVE-NEXT:    add sp, sp, #16
73; NONEON-NOSVE-NEXT:    ret
74  %ret = call <4 x i8> @llvm.vector.extract.v4i8.v8i8(<8 x i8> %op, i64 4)
75  ret <4 x i8> %ret
76}
77
78define <8 x i8> @extract_subvector_v16i8(<16 x i8> %op) {
79; CHECK-LABEL: extract_subvector_v16i8:
80; CHECK:       // %bb.0:
81; CHECK-NEXT:    // kill: def $q0 killed $q0 def $z0
82; CHECK-NEXT:    ext z0.b, z0.b, z0.b, #8
83; CHECK-NEXT:    // kill: def $d0 killed $d0 killed $z0
84; CHECK-NEXT:    ret
85;
86; NONEON-NOSVE-LABEL: extract_subvector_v16i8:
87; NONEON-NOSVE:       // %bb.0:
88; NONEON-NOSVE-NEXT:    str q0, [sp, #-16]!
89; NONEON-NOSVE-NEXT:    .cfi_def_cfa_offset 16
90; NONEON-NOSVE-NEXT:    ldr d0, [sp, #8]
91; NONEON-NOSVE-NEXT:    add sp, sp, #16
92; NONEON-NOSVE-NEXT:    ret
93  %ret = call <8 x i8> @llvm.vector.extract.v8i8.v16i8(<16 x i8> %op, i64 8)
94  ret <8 x i8> %ret
95}
96
97define void @extract_subvector_v32i8(ptr %a, ptr %b) {
98; CHECK-LABEL: extract_subvector_v32i8:
99; CHECK:       // %bb.0:
100; CHECK-NEXT:    ldr q0, [x0, #16]
101; CHECK-NEXT:    str q0, [x1]
102; CHECK-NEXT:    ret
103;
104; NONEON-NOSVE-LABEL: extract_subvector_v32i8:
105; NONEON-NOSVE:       // %bb.0:
106; NONEON-NOSVE-NEXT:    ldr q0, [x0, #16]
107; NONEON-NOSVE-NEXT:    str q0, [x1]
108; NONEON-NOSVE-NEXT:    ret
109  %op = load <32 x i8>, ptr %a
110  %ret = call <16 x i8> @llvm.vector.extract.v16i8.v32i8(<32 x i8> %op, i64 16)
111  store <16 x i8> %ret, ptr %b
112  ret void
113}
114
115; i16
116
117define <2 x i16> @extract_subvector_v4i16(<4 x i16> %op) {
118; CHECK-LABEL: extract_subvector_v4i16:
119; CHECK:       // %bb.0:
120; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
121; CHECK-NEXT:    uunpklo z0.s, z0.h
122; CHECK-NEXT:    ext z0.b, z0.b, z0.b, #8
123; CHECK-NEXT:    // kill: def $d0 killed $d0 killed $z0
124; CHECK-NEXT:    ret
125;
126; NONEON-NOSVE-LABEL: extract_subvector_v4i16:
127; NONEON-NOSVE:       // %bb.0:
128; NONEON-NOSVE-NEXT:    ushll v0.4s, v0.4h, #0
129; NONEON-NOSVE-NEXT:    str q0, [sp, #-16]!
130; NONEON-NOSVE-NEXT:    .cfi_def_cfa_offset 16
131; NONEON-NOSVE-NEXT:    ldr d0, [sp, #8]
132; NONEON-NOSVE-NEXT:    add sp, sp, #16
133; NONEON-NOSVE-NEXT:    ret
134  %ret = call <2 x i16> @llvm.vector.extract.v2i16.v4i16(<4 x i16> %op, i64 2)
135  ret <2 x i16> %ret
136}
137
138define <4 x i16> @extract_subvector_v8i16(<8 x i16> %op) {
139; CHECK-LABEL: extract_subvector_v8i16:
140; CHECK:       // %bb.0:
141; CHECK-NEXT:    // kill: def $q0 killed $q0 def $z0
142; CHECK-NEXT:    ext z0.b, z0.b, z0.b, #8
143; CHECK-NEXT:    // kill: def $d0 killed $d0 killed $z0
144; CHECK-NEXT:    ret
145;
146; NONEON-NOSVE-LABEL: extract_subvector_v8i16:
147; NONEON-NOSVE:       // %bb.0:
148; NONEON-NOSVE-NEXT:    str q0, [sp, #-16]!
149; NONEON-NOSVE-NEXT:    .cfi_def_cfa_offset 16
150; NONEON-NOSVE-NEXT:    ldr d0, [sp, #8]
151; NONEON-NOSVE-NEXT:    add sp, sp, #16
152; NONEON-NOSVE-NEXT:    ret
153  %ret = call <4 x i16> @llvm.vector.extract.v4i16.v8i16(<8 x i16> %op, i64 4)
154  ret <4 x i16> %ret
155}
156
157define void @extract_subvector_v16i16(ptr %a, ptr %b) {
158; CHECK-LABEL: extract_subvector_v16i16:
159; CHECK:       // %bb.0:
160; CHECK-NEXT:    ldr q0, [x0, #16]
161; CHECK-NEXT:    str q0, [x1]
162; CHECK-NEXT:    ret
163;
164; NONEON-NOSVE-LABEL: extract_subvector_v16i16:
165; NONEON-NOSVE:       // %bb.0:
166; NONEON-NOSVE-NEXT:    ldr q0, [x0, #16]
167; NONEON-NOSVE-NEXT:    str q0, [x1]
168; NONEON-NOSVE-NEXT:    ret
169  %op = load <16 x i16>, ptr %a
170  %ret = call <8 x i16> @llvm.vector.extract.v8i16.v16i16(<16 x i16> %op, i64 8)
171  store <8 x i16> %ret, ptr %b
172  ret void
173}
174
175; i32
176
177define <1 x i32> @extract_subvector_v2i32(<2 x i32> %op) {
178; CHECK-LABEL: extract_subvector_v2i32:
179; CHECK:       // %bb.0:
180; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
181; CHECK-NEXT:    mov z0.s, z0.s[1]
182; CHECK-NEXT:    // kill: def $d0 killed $d0 killed $z0
183; CHECK-NEXT:    ret
184;
185; NONEON-NOSVE-LABEL: extract_subvector_v2i32:
186; NONEON-NOSVE:       // %bb.0:
187; NONEON-NOSVE-NEXT:    sub sp, sp, #16
188; NONEON-NOSVE-NEXT:    .cfi_def_cfa_offset 16
189; NONEON-NOSVE-NEXT:    str d0, [sp, #8]
190; NONEON-NOSVE-NEXT:    ldr w8, [sp, #12]
191; NONEON-NOSVE-NEXT:    str w8, [sp]
192; NONEON-NOSVE-NEXT:    ldr d0, [sp], #16
193; NONEON-NOSVE-NEXT:    ret
194  %ret = call <1 x i32> @llvm.vector.extract.v1i32.v2i32(<2 x i32> %op, i64 1)
195  ret <1 x i32> %ret
196}
197
198define <2 x i32> @extract_subvector_v4i32(<4 x i32> %op) {
199; CHECK-LABEL: extract_subvector_v4i32:
200; CHECK:       // %bb.0:
201; CHECK-NEXT:    // kill: def $q0 killed $q0 def $z0
202; CHECK-NEXT:    ext z0.b, z0.b, z0.b, #8
203; CHECK-NEXT:    // kill: def $d0 killed $d0 killed $z0
204; CHECK-NEXT:    ret
205;
206; NONEON-NOSVE-LABEL: extract_subvector_v4i32:
207; NONEON-NOSVE:       // %bb.0:
208; NONEON-NOSVE-NEXT:    str q0, [sp, #-16]!
209; NONEON-NOSVE-NEXT:    .cfi_def_cfa_offset 16
210; NONEON-NOSVE-NEXT:    ldr d0, [sp, #8]
211; NONEON-NOSVE-NEXT:    add sp, sp, #16
212; NONEON-NOSVE-NEXT:    ret
213  %ret = call <2 x i32> @llvm.vector.extract.v2i32.v4i32(<4 x i32> %op, i64 2)
214  ret <2 x i32> %ret
215}
216
217define void @extract_subvector_v8i32(ptr %a, ptr %b) {
218; CHECK-LABEL: extract_subvector_v8i32:
219; CHECK:       // %bb.0:
220; CHECK-NEXT:    ldr q0, [x0, #16]
221; CHECK-NEXT:    str q0, [x1]
222; CHECK-NEXT:    ret
223;
224; NONEON-NOSVE-LABEL: extract_subvector_v8i32:
225; NONEON-NOSVE:       // %bb.0:
226; NONEON-NOSVE-NEXT:    ldr q0, [x0, #16]
227; NONEON-NOSVE-NEXT:    str q0, [x1]
228; NONEON-NOSVE-NEXT:    ret
229  %op = load <8 x i32>, ptr %a
230  %ret = call <4 x i32> @llvm.vector.extract.v4i32.v8i32(<8 x i32> %op, i64 4)
231  store <4 x i32> %ret, ptr %b
232  ret void
233}
234
235; i64
236
237define <1 x i64> @extract_subvector_v2i64(<2 x i64> %op) {
238; CHECK-LABEL: extract_subvector_v2i64:
239; CHECK:       // %bb.0:
240; CHECK-NEXT:    // kill: def $q0 killed $q0 def $z0
241; CHECK-NEXT:    ext z0.b, z0.b, z0.b, #8
242; CHECK-NEXT:    // kill: def $d0 killed $d0 killed $z0
243; CHECK-NEXT:    ret
244;
245; NONEON-NOSVE-LABEL: extract_subvector_v2i64:
246; NONEON-NOSVE:       // %bb.0:
247; NONEON-NOSVE-NEXT:    str q0, [sp, #-16]!
248; NONEON-NOSVE-NEXT:    .cfi_def_cfa_offset 16
249; NONEON-NOSVE-NEXT:    ldr d0, [sp, #8]
250; NONEON-NOSVE-NEXT:    add sp, sp, #16
251; NONEON-NOSVE-NEXT:    ret
252  %ret = call <1 x i64> @llvm.vector.extract.v1i64.v2i64(<2 x i64> %op, i64 1)
253  ret <1 x i64> %ret
254}
255
256define void @extract_subvector_v4i64(ptr %a, ptr %b) {
257; CHECK-LABEL: extract_subvector_v4i64:
258; CHECK:       // %bb.0:
259; CHECK-NEXT:    ldr q0, [x0, #16]
260; CHECK-NEXT:    str q0, [x1]
261; CHECK-NEXT:    ret
262;
263; NONEON-NOSVE-LABEL: extract_subvector_v4i64:
264; NONEON-NOSVE:       // %bb.0:
265; NONEON-NOSVE-NEXT:    ldr q0, [x0, #16]
266; NONEON-NOSVE-NEXT:    str q0, [x1]
267; NONEON-NOSVE-NEXT:    ret
268  %op = load <4 x i64>, ptr %a
269  %ret = call <2 x i64> @llvm.vector.extract.v2i64.v4i64(<4 x i64> %op, i64 2)
270  store <2 x i64> %ret, ptr %b
271  ret void
272}
273
274; f16
275
276define <2 x half> @extract_subvector_v4f16(<4 x half> %op) {
277; CHECK-LABEL: extract_subvector_v4f16:
278; CHECK:       // %bb.0:
279; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
280; CHECK-NEXT:    mov z0.s, z0.s[1]
281; CHECK-NEXT:    // kill: def $d0 killed $d0 killed $z0
282; CHECK-NEXT:    ret
283;
284; NONEON-NOSVE-LABEL: extract_subvector_v4f16:
285; NONEON-NOSVE:       // %bb.0:
286; NONEON-NOSVE-NEXT:    str d0, [sp, #-16]!
287; NONEON-NOSVE-NEXT:    .cfi_def_cfa_offset 16
288; NONEON-NOSVE-NEXT:    ldr w8, [sp, #4]
289; NONEON-NOSVE-NEXT:    str w8, [sp, #8]
290; NONEON-NOSVE-NEXT:    ldr d0, [sp, #8]
291; NONEON-NOSVE-NEXT:    add sp, sp, #16
292; NONEON-NOSVE-NEXT:    ret
293  %ret = call <2 x half> @llvm.vector.extract.v2f16.v4f16(<4 x half> %op, i64 2)
294  ret <2 x half> %ret
295}
296
297define <4 x half> @extract_subvector_v8f16(<8 x half> %op) {
298; CHECK-LABEL: extract_subvector_v8f16:
299; CHECK:       // %bb.0:
300; CHECK-NEXT:    // kill: def $q0 killed $q0 def $z0
301; CHECK-NEXT:    ext z0.b, z0.b, z0.b, #8
302; CHECK-NEXT:    // kill: def $d0 killed $d0 killed $z0
303; CHECK-NEXT:    ret
304;
305; NONEON-NOSVE-LABEL: extract_subvector_v8f16:
306; NONEON-NOSVE:       // %bb.0:
307; NONEON-NOSVE-NEXT:    str q0, [sp, #-16]!
308; NONEON-NOSVE-NEXT:    .cfi_def_cfa_offset 16
309; NONEON-NOSVE-NEXT:    ldr d0, [sp, #8]
310; NONEON-NOSVE-NEXT:    add sp, sp, #16
311; NONEON-NOSVE-NEXT:    ret
312  %ret = call <4 x half> @llvm.vector.extract.v4f16.v8f16(<8 x half> %op, i64 4)
313  ret <4 x half> %ret
314}
315
316define void @extract_subvector_v16f16(ptr %a, ptr %b) {
317; CHECK-LABEL: extract_subvector_v16f16:
318; CHECK:       // %bb.0:
319; CHECK-NEXT:    ldr q0, [x0, #16]
320; CHECK-NEXT:    str q0, [x1]
321; CHECK-NEXT:    ret
322;
323; NONEON-NOSVE-LABEL: extract_subvector_v16f16:
324; NONEON-NOSVE:       // %bb.0:
325; NONEON-NOSVE-NEXT:    ldr q0, [x0, #16]
326; NONEON-NOSVE-NEXT:    str q0, [x1]
327; NONEON-NOSVE-NEXT:    ret
328  %op = load <16 x half>, ptr %a
329  %ret = call <8 x half> @llvm.vector.extract.v8f16.v16f16(<16 x half> %op, i64 8)
330  store <8 x half> %ret, ptr %b
331  ret void
332}
333
334; f32
335
336define <1 x float> @extract_subvector_v2f32(<2 x float> %op) {
337; CHECK-LABEL: extract_subvector_v2f32:
338; CHECK:       // %bb.0:
339; CHECK-NEXT:    // kill: def $d0 killed $d0 def $z0
340; CHECK-NEXT:    mov z0.s, z0.s[1]
341; CHECK-NEXT:    // kill: def $d0 killed $d0 killed $z0
342; CHECK-NEXT:    ret
343;
344; NONEON-NOSVE-LABEL: extract_subvector_v2f32:
345; NONEON-NOSVE:       // %bb.0:
346; NONEON-NOSVE-NEXT:    sub sp, sp, #16
347; NONEON-NOSVE-NEXT:    .cfi_def_cfa_offset 16
348; NONEON-NOSVE-NEXT:    str d0, [sp, #8]
349; NONEON-NOSVE-NEXT:    ldr w8, [sp, #12]
350; NONEON-NOSVE-NEXT:    str w8, [sp]
351; NONEON-NOSVE-NEXT:    ldr d0, [sp], #16
352; NONEON-NOSVE-NEXT:    ret
353  %ret = call <1 x float> @llvm.vector.extract.v1f32.v2f32(<2 x float> %op, i64 1)
354  ret <1 x float> %ret
355}
356
357define <2 x float> @extract_subvector_v4f32(<4 x float> %op) {
358; CHECK-LABEL: extract_subvector_v4f32:
359; CHECK:       // %bb.0:
360; CHECK-NEXT:    // kill: def $q0 killed $q0 def $z0
361; CHECK-NEXT:    ext z0.b, z0.b, z0.b, #8
362; CHECK-NEXT:    // kill: def $d0 killed $d0 killed $z0
363; CHECK-NEXT:    ret
364;
365; NONEON-NOSVE-LABEL: extract_subvector_v4f32:
366; NONEON-NOSVE:       // %bb.0:
367; NONEON-NOSVE-NEXT:    str q0, [sp, #-16]!
368; NONEON-NOSVE-NEXT:    .cfi_def_cfa_offset 16
369; NONEON-NOSVE-NEXT:    ldr d0, [sp, #8]
370; NONEON-NOSVE-NEXT:    add sp, sp, #16
371; NONEON-NOSVE-NEXT:    ret
372  %ret = call <2 x float> @llvm.vector.extract.v2f32.v4f32(<4 x float> %op, i64 2)
373  ret <2 x float> %ret
374}
375
376define void @extract_subvector_v8f32(ptr %a, ptr %b) {
377; CHECK-LABEL: extract_subvector_v8f32:
378; CHECK:       // %bb.0:
379; CHECK-NEXT:    ldr q0, [x0, #16]
380; CHECK-NEXT:    str q0, [x1]
381; CHECK-NEXT:    ret
382;
383; NONEON-NOSVE-LABEL: extract_subvector_v8f32:
384; NONEON-NOSVE:       // %bb.0:
385; NONEON-NOSVE-NEXT:    ldr q0, [x0, #16]
386; NONEON-NOSVE-NEXT:    str q0, [x1]
387; NONEON-NOSVE-NEXT:    ret
388  %op = load <8 x float>, ptr %a
389  %ret = call <4 x float> @llvm.vector.extract.v4f32.v8f32(<8 x float> %op, i64 4)
390  store <4 x float> %ret, ptr %b
391  ret void
392}
393
394; f64
395
396define <1 x double> @extract_subvector_v2f64(<2 x double> %op) {
397; CHECK-LABEL: extract_subvector_v2f64:
398; CHECK:       // %bb.0:
399; CHECK-NEXT:    // kill: def $q0 killed $q0 def $z0
400; CHECK-NEXT:    ext z0.b, z0.b, z0.b, #8
401; CHECK-NEXT:    // kill: def $d0 killed $d0 killed $z0
402; CHECK-NEXT:    ret
403;
404; NONEON-NOSVE-LABEL: extract_subvector_v2f64:
405; NONEON-NOSVE:       // %bb.0:
406; NONEON-NOSVE-NEXT:    str q0, [sp, #-16]!
407; NONEON-NOSVE-NEXT:    .cfi_def_cfa_offset 16
408; NONEON-NOSVE-NEXT:    ldr d0, [sp, #8]
409; NONEON-NOSVE-NEXT:    add sp, sp, #16
410; NONEON-NOSVE-NEXT:    ret
411  %ret = call <1 x double> @llvm.vector.extract.v1f64.v2f64(<2 x double> %op, i64 1)
412  ret <1 x double> %ret
413}
414
415define void @extract_subvector_v4f64(ptr %a, ptr %b) {
416; CHECK-LABEL: extract_subvector_v4f64:
417; CHECK:       // %bb.0:
418; CHECK-NEXT:    ldr q0, [x0, #16]
419; CHECK-NEXT:    str q0, [x1]
420; CHECK-NEXT:    ret
421;
422; NONEON-NOSVE-LABEL: extract_subvector_v4f64:
423; NONEON-NOSVE:       // %bb.0:
424; NONEON-NOSVE-NEXT:    ldr q0, [x0, #16]
425; NONEON-NOSVE-NEXT:    str q0, [x1]
426; NONEON-NOSVE-NEXT:    ret
427  %op = load <4 x double>, ptr %a
428  %ret = call <2 x double> @llvm.vector.extract.v2f64.v4f64(<4 x double> %op, i64 2)
429  store <2 x double> %ret, ptr %b
430  ret void
431}
432
433declare <4 x i1> @llvm.vector.extract.v4i1.v8i1(<8 x i1>, i64)
434
435declare <4 x i8> @llvm.vector.extract.v4i8.v8i8(<8 x i8>, i64)
436declare <8 x i8> @llvm.vector.extract.v8i8.v16i8(<16 x i8>, i64)
437declare <16 x i8> @llvm.vector.extract.v16i8.v32i8(<32 x i8>, i64)
438declare <32 x i8> @llvm.vector.extract.v32i8.v64i8(<64 x i8>, i64)
439
440declare <2 x i16> @llvm.vector.extract.v2i16.v4i16(<4 x i16>, i64)
441declare <4 x i16> @llvm.vector.extract.v4i16.v8i16(<8 x i16>, i64)
442declare <8 x i16> @llvm.vector.extract.v8i16.v16i16(<16 x i16>, i64)
443declare <16 x i16> @llvm.vector.extract.v16i16.v32i16(<32 x i16>, i64)
444
445declare <1 x i32> @llvm.vector.extract.v1i32.v2i32(<2 x i32>, i64)
446declare <2 x i32> @llvm.vector.extract.v2i32.v4i32(<4 x i32>, i64)
447declare <4 x i32> @llvm.vector.extract.v4i32.v8i32(<8 x i32>, i64)
448declare <8 x i32> @llvm.vector.extract.v8i32.v16i32(<16 x i32>, i64)
449
450declare <1 x i64> @llvm.vector.extract.v1i64.v2i64(<2 x i64>, i64)
451declare <2 x i64> @llvm.vector.extract.v2i64.v4i64(<4 x i64>, i64)
452declare <4 x i64> @llvm.vector.extract.v4i64.v8i64(<8 x i64>, i64)
453
454declare <2 x half> @llvm.vector.extract.v2f16.v4f16(<4 x half>, i64)
455declare <4 x half> @llvm.vector.extract.v4f16.v8f16(<8 x half>, i64)
456declare <8 x half> @llvm.vector.extract.v8f16.v16f16(<16 x half>, i64)
457declare <16 x half> @llvm.vector.extract.v16f16.v32f16(<32 x half>, i64)
458
459declare <1 x float> @llvm.vector.extract.v1f32.v2f32(<2 x float>, i64)
460declare <2 x float> @llvm.vector.extract.v2f32.v4f32(<4 x float>, i64)
461declare <4 x float> @llvm.vector.extract.v4f32.v8f32(<8 x float>, i64)
462declare <8 x float> @llvm.vector.extract.v8f32.v16f32(<16 x float>, i64)
463
464declare <1 x double> @llvm.vector.extract.v1f64.v2f64(<2 x double>, i64)
465declare <2 x double> @llvm.vector.extract.v2f64.v4f64(<4 x double>, i64)
466declare <4 x double> @llvm.vector.extract.v4f64.v8f64(<8 x double>, i64)
467