1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc -mattr=+sve -force-streaming-compatible < %s | FileCheck %s 3; RUN: llc -mattr=+sme -force-streaming < %s | FileCheck %s 4; RUN: llc -force-streaming-compatible < %s | FileCheck %s --check-prefix=NONEON-NOSVE 5 6target triple = "aarch64" 7 8; 9; NOTE: SVE lowering for the BSP pseudoinst is not currently implemented, so we 10; don't currently expect the code below to lower to BSL/BIT/BIF. Once 11; this is implemented, this test will be fleshed out. 12; 13 14define <8 x i32> @fixed_bitselect_v8i32(ptr %pre_cond_ptr, ptr %left_ptr, ptr %right_ptr) { 15; CHECK-LABEL: fixed_bitselect_v8i32: 16; CHECK: // %bb.0: 17; CHECK-NEXT: mov z0.s, #-1 // =0xffffffffffffffff 18; CHECK-NEXT: ldp q2, q1, [x0] 19; CHECK-NEXT: ldp q5, q4, [x1] 20; CHECK-NEXT: ldp q6, q7, [x2] 21; CHECK-NEXT: add z3.s, z1.s, z0.s 22; CHECK-NEXT: subr z1.s, z1.s, #0 // =0x0 23; CHECK-NEXT: add z0.s, z2.s, z0.s 24; CHECK-NEXT: subr z2.s, z2.s, #0 // =0x0 25; CHECK-NEXT: and z1.d, z1.d, z4.d 26; CHECK-NEXT: and z3.d, z3.d, z7.d 27; CHECK-NEXT: and z0.d, z0.d, z6.d 28; CHECK-NEXT: and z2.d, z2.d, z5.d 29; CHECK-NEXT: orr z1.d, z3.d, z1.d 30; CHECK-NEXT: orr z0.d, z0.d, z2.d 31; CHECK-NEXT: // kill: def $q1 killed $q1 killed $z1 32; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0 33; CHECK-NEXT: ret 34; 35; NONEON-NOSVE-LABEL: fixed_bitselect_v8i32: 36; NONEON-NOSVE: // %bb.0: 37; NONEON-NOSVE-NEXT: ldp q0, q1, [x0] 38; NONEON-NOSVE-NEXT: ldp q2, q3, [x1] 39; NONEON-NOSVE-NEXT: ldp q4, q5, [x2] 40; NONEON-NOSVE-NEXT: stp q0, q2, [sp, #-128]! 41; NONEON-NOSVE-NEXT: .cfi_def_cfa_offset 128 42; NONEON-NOSVE-NEXT: stp q1, q3, [sp, #48] 43; NONEON-NOSVE-NEXT: ldp w8, w14, [sp, #48] 44; NONEON-NOSVE-NEXT: ldp w9, w4, [sp, #64] 45; NONEON-NOSVE-NEXT: ldp w13, w11, [sp, #56] 46; NONEON-NOSVE-NEXT: neg w3, w8 47; NONEON-NOSVE-NEXT: neg w15, w14 48; NONEON-NOSVE-NEXT: str q4, [sp, #32] 49; NONEON-NOSVE-NEXT: and w9, w3, w9 50; NONEON-NOSVE-NEXT: and w15, w15, w4 51; NONEON-NOSVE-NEXT: str q5, [sp, #80] 52; NONEON-NOSVE-NEXT: ldp w5, w3, [sp, #72] 53; NONEON-NOSVE-NEXT: ldp w16, w12, [sp] 54; NONEON-NOSVE-NEXT: neg w4, w11 55; NONEON-NOSVE-NEXT: neg w2, w13 56; NONEON-NOSVE-NEXT: sub w11, w11, #1 57; NONEON-NOSVE-NEXT: and w3, w4, w3 58; NONEON-NOSVE-NEXT: and w2, w2, w5 59; NONEON-NOSVE-NEXT: sub w13, w13, #1 60; NONEON-NOSVE-NEXT: ldp w6, w4, [sp, #16] 61; NONEON-NOSVE-NEXT: ldp w10, w17, [sp, #8] 62; NONEON-NOSVE-NEXT: neg w1, w16 63; NONEON-NOSVE-NEXT: neg w0, w12 64; NONEON-NOSVE-NEXT: sub w16, w16, #1 65; NONEON-NOSVE-NEXT: and w1, w1, w6 66; NONEON-NOSVE-NEXT: and w0, w0, w4 67; NONEON-NOSVE-NEXT: sub w12, w12, #1 68; NONEON-NOSVE-NEXT: ldp w5, w6, [sp, #24] 69; NONEON-NOSVE-NEXT: neg w18, w17 70; NONEON-NOSVE-NEXT: neg w4, w10 71; NONEON-NOSVE-NEXT: sub w17, w17, #1 72; NONEON-NOSVE-NEXT: sub w10, w10, #1 73; NONEON-NOSVE-NEXT: sub w14, w14, #1 74; NONEON-NOSVE-NEXT: sub w8, w8, #1 75; NONEON-NOSVE-NEXT: and w4, w4, w5 76; NONEON-NOSVE-NEXT: and w18, w18, w6 77; NONEON-NOSVE-NEXT: ldp w5, w6, [sp, #32] 78; NONEON-NOSVE-NEXT: and w16, w16, w5 79; NONEON-NOSVE-NEXT: and w12, w12, w6 80; NONEON-NOSVE-NEXT: ldp w5, w6, [sp, #40] 81; NONEON-NOSVE-NEXT: and w10, w10, w5 82; NONEON-NOSVE-NEXT: and w17, w17, w6 83; NONEON-NOSVE-NEXT: orr w17, w17, w18 84; NONEON-NOSVE-NEXT: orr w10, w10, w4 85; NONEON-NOSVE-NEXT: ldp w18, w4, [sp, #88] 86; NONEON-NOSVE-NEXT: ldp w5, w6, [sp, #80] 87; NONEON-NOSVE-NEXT: stp w10, w17, [sp, #104] 88; NONEON-NOSVE-NEXT: orr w10, w12, w0 89; NONEON-NOSVE-NEXT: orr w12, w16, w1 90; NONEON-NOSVE-NEXT: and w11, w11, w4 91; NONEON-NOSVE-NEXT: stp w12, w10, [sp, #96] 92; NONEON-NOSVE-NEXT: and w10, w13, w18 93; NONEON-NOSVE-NEXT: orr w11, w11, w3 94; NONEON-NOSVE-NEXT: and w12, w14, w6 95; NONEON-NOSVE-NEXT: orr w10, w10, w2 96; NONEON-NOSVE-NEXT: and w8, w8, w5 97; NONEON-NOSVE-NEXT: stp w10, w11, [sp, #120] 98; NONEON-NOSVE-NEXT: orr w10, w12, w15 99; NONEON-NOSVE-NEXT: orr w8, w8, w9 100; NONEON-NOSVE-NEXT: stp w8, w10, [sp, #112] 101; NONEON-NOSVE-NEXT: ldp q0, q1, [sp, #96] 102; NONEON-NOSVE-NEXT: add sp, sp, #128 103; NONEON-NOSVE-NEXT: ret 104 %pre_cond = load <8 x i32>, ptr %pre_cond_ptr 105 %left = load <8 x i32>, ptr %left_ptr 106 %right = load <8 x i32>, ptr %right_ptr 107 108 %neg_cond = sub <8 x i32> zeroinitializer, %pre_cond 109 %min_cond = add <8 x i32> %pre_cond, <i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1> 110 %left_bits_0 = and <8 x i32> %neg_cond, %left 111 %right_bits_0 = and <8 x i32> %min_cond, %right 112 %bsl0000 = or <8 x i32> %right_bits_0, %left_bits_0 113 ret <8 x i32> %bsl0000 114} 115 116