xref: /llvm-project/llvm/test/CodeGen/AArch64/sve-split-trunc.ll (revision cd89f5c91b4bad90278a59865fc06a75211589a1) 
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple=aarch64--linux-gnu -mattr=+sve < %s | FileCheck %s
3
4define <vscale x 16 x i8> @trunc_i16toi8(<vscale x 16 x i16> %in) {
5; CHECK-LABEL: trunc_i16toi8:
6; CHECK:       // %bb.0:
7; CHECK-NEXT:    uzp1 z0.b, z0.b, z1.b
8; CHECK-NEXT:    ret
9  %out = trunc <vscale x 16 x i16> %in to <vscale x 16 x i8>
10  ret <vscale x 16 x i8> %out
11}
12
13define <vscale x 16 x i8> @trunc_i32toi8(<vscale x 16 x i32> %in) {
14; CHECK-LABEL: trunc_i32toi8:
15; CHECK:       // %bb.0:
16; CHECK-NEXT:    uzp1 z2.h, z2.h, z3.h
17; CHECK-NEXT:    uzp1 z0.h, z0.h, z1.h
18; CHECK-NEXT:    uzp1 z0.b, z0.b, z2.b
19; CHECK-NEXT:    ret
20  %out = trunc <vscale x 16 x i32> %in to <vscale x 16 x i8>
21  ret <vscale x 16 x i8> %out
22}
23
24define <vscale x 8 x i16> @trunc_i32toi16(<vscale x 8 x i32> %in) {
25; CHECK-LABEL: trunc_i32toi16:
26; CHECK:       // %bb.0:
27; CHECK-NEXT:    uzp1 z0.h, z0.h, z1.h
28; CHECK-NEXT:    ret
29  %out = trunc <vscale x 8 x i32> %in to <vscale x 8 x i16>
30  ret <vscale x 8 x i16> %out
31}
32
33define <vscale x 4 x i32> @trunc_i64toi32(<vscale x 4 x i64> %in) {
34; CHECK-LABEL: trunc_i64toi32:
35; CHECK:       // %bb.0:
36; CHECK-NEXT:    uzp1 z0.s, z0.s, z1.s
37; CHECK-NEXT:    ret
38  %out = trunc <vscale x 4 x i64> %in to <vscale x 4 x i32>
39  ret <vscale x 4 x i32> %out
40}
41
42define <vscale x 8 x i16> @trunc_i64toi16(<vscale x 8 x i64> %in) {
43; CHECK-LABEL: trunc_i64toi16:
44; CHECK:       // %bb.0:
45; CHECK-NEXT:    uzp1 z2.s, z2.s, z3.s
46; CHECK-NEXT:    uzp1 z0.s, z0.s, z1.s
47; CHECK-NEXT:    uzp1 z0.h, z0.h, z2.h
48; CHECK-NEXT:    ret
49  %out = trunc <vscale x 8 x i64> %in to <vscale x 8 x i16>
50  ret <vscale x 8 x i16> %out
51}
52
53define <vscale x 16 x i8> @trunc_i64toi8(<vscale x 16 x i64> %in) {
54; CHECK-LABEL: trunc_i64toi8:
55; CHECK:       // %bb.0:
56; CHECK-NEXT:    uzp1 z6.s, z6.s, z7.s
57; CHECK-NEXT:    uzp1 z4.s, z4.s, z5.s
58; CHECK-NEXT:    uzp1 z2.s, z2.s, z3.s
59; CHECK-NEXT:    uzp1 z0.s, z0.s, z1.s
60; CHECK-NEXT:    uzp1 z1.h, z4.h, z6.h
61; CHECK-NEXT:    uzp1 z0.h, z0.h, z2.h
62; CHECK-NEXT:    uzp1 z0.b, z0.b, z1.b
63; CHECK-NEXT:    ret
64  %out = trunc <vscale x 16 x i64> %in to <vscale x 16 x i8>
65  ret <vscale x 16 x i8> %out
66}
67