1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve < %s | FileCheck %s 3 4; UNPREDICATED 5 6define void @store_promote_4i8(<vscale x 4 x i8> %data, ptr %a) { 7; CHECK-LABEL: store_promote_4i8: 8; CHECK: // %bb.0: 9; CHECK-NEXT: ptrue p0.s 10; CHECK-NEXT: st1b { z0.s }, p0, [x0] 11; CHECK-NEXT: ret 12 store <vscale x 4 x i8> %data, ptr %a 13 ret void 14} 15 16define void @store_split_i16(<vscale x 16 x i16> %data, ptr %a) { 17; CHECK-LABEL: store_split_i16: 18; CHECK: // %bb.0: 19; CHECK-NEXT: ptrue p0.h 20; CHECK-NEXT: st1h { z1.h }, p0, [x0, #1, mul vl] 21; CHECK-NEXT: st1h { z0.h }, p0, [x0] 22; CHECK-NEXT: ret 23 store <vscale x 16 x i16> %data, ptr %a 24 ret void 25} 26 27define void @store_split_16i32(<vscale x 16 x i32> %data, ptr %a) { 28; CHECK-LABEL: store_split_16i32: 29; CHECK: // %bb.0: 30; CHECK-NEXT: ptrue p0.s 31; CHECK-NEXT: st1w { z3.s }, p0, [x0, #3, mul vl] 32; CHECK-NEXT: st1w { z2.s }, p0, [x0, #2, mul vl] 33; CHECK-NEXT: st1w { z1.s }, p0, [x0, #1, mul vl] 34; CHECK-NEXT: st1w { z0.s }, p0, [x0] 35; CHECK-NEXT: ret 36 store <vscale x 16 x i32> %data, ptr %a 37 ret void 38} 39 40define void @store_split_16i64(<vscale x 16 x i64> %data, ptr %a) { 41; CHECK-LABEL: store_split_16i64: 42; CHECK: // %bb.0: 43; CHECK-NEXT: ptrue p0.d 44; CHECK-NEXT: st1d { z7.d }, p0, [x0, #7, mul vl] 45; CHECK-NEXT: st1d { z6.d }, p0, [x0, #6, mul vl] 46; CHECK-NEXT: st1d { z5.d }, p0, [x0, #5, mul vl] 47; CHECK-NEXT: st1d { z4.d }, p0, [x0, #4, mul vl] 48; CHECK-NEXT: st1d { z3.d }, p0, [x0, #3, mul vl] 49; CHECK-NEXT: st1d { z2.d }, p0, [x0, #2, mul vl] 50; CHECK-NEXT: st1d { z1.d }, p0, [x0, #1, mul vl] 51; CHECK-NEXT: st1d { z0.d }, p0, [x0] 52; CHECK-NEXT: ret 53 store <vscale x 16 x i64> %data, ptr %a 54 ret void 55} 56 57; MASKED 58 59define void @masked_store_promote_2i8(<vscale x 2 x i8> %data, ptr %a, <vscale x 2 x i1> %pg) { 60; CHECK-LABEL: masked_store_promote_2i8: 61; CHECK: // %bb.0: 62; CHECK-NEXT: st1b { z0.d }, p0, [x0] 63; CHECK-NEXT: ret 64 call void @llvm.masked.store.nxv2i8(<vscale x 2 x i8> %data, ptr %a, i32 1, <vscale x 2 x i1> %pg) 65 ret void 66} 67 68define void @masked_store_split_32i8(<vscale x 32 x i8> %data, ptr %a, <vscale x 32 x i1> %pg) { 69; CHECK-LABEL: masked_store_split_32i8: 70; CHECK: // %bb.0: 71; CHECK-NEXT: st1b { z1.b }, p1, [x0, #1, mul vl] 72; CHECK-NEXT: st1b { z0.b }, p0, [x0] 73; CHECK-NEXT: ret 74 call void @llvm.masked.store.nxv32i8(<vscale x 32 x i8> %data, ptr %a, i32 1, <vscale x 32 x i1> %pg) 75 ret void 76} 77 78define void @masked_store_split_32i16(<vscale x 32 x i16> %data, ptr %a, <vscale x 32 x i1> %pg) { 79; CHECK-LABEL: masked_store_split_32i16: 80; CHECK: // %bb.0: 81; CHECK-NEXT: punpkhi p2.h, p1.b 82; CHECK-NEXT: punpklo p1.h, p1.b 83; CHECK-NEXT: punpkhi p3.h, p0.b 84; CHECK-NEXT: st1h { z3.h }, p2, [x0, #3, mul vl] 85; CHECK-NEXT: punpklo p0.h, p0.b 86; CHECK-NEXT: st1h { z2.h }, p1, [x0, #2, mul vl] 87; CHECK-NEXT: st1h { z1.h }, p3, [x0, #1, mul vl] 88; CHECK-NEXT: st1h { z0.h }, p0, [x0] 89; CHECK-NEXT: ret 90 call void @llvm.masked.store.nxv32i16(<vscale x 32 x i16> %data, ptr %a, i32 1, <vscale x 32 x i1> %pg) 91 ret void 92} 93 94define void @masked_store_split_8i32(<vscale x 8 x i32> %data, ptr %a, <vscale x 8 x i1> %pg) { 95; CHECK-LABEL: masked_store_split_8i32: 96; CHECK: // %bb.0: 97; CHECK-NEXT: punpkhi p1.h, p0.b 98; CHECK-NEXT: punpklo p0.h, p0.b 99; CHECK-NEXT: st1w { z1.s }, p1, [x0, #1, mul vl] 100; CHECK-NEXT: st1w { z0.s }, p0, [x0] 101; CHECK-NEXT: ret 102 call void @llvm.masked.store.nxv8i32(<vscale x 8 x i32> %data, ptr %a, i32 1, <vscale x 8 x i1> %pg) 103 ret void 104} 105 106define void @masked_store_split_8i64(<vscale x 8 x i64> %data, ptr %a, <vscale x 8 x i1> %pg) { 107; CHECK-LABEL: masked_store_split_8i64: 108; CHECK: // %bb.0: 109; CHECK-NEXT: punpkhi p1.h, p0.b 110; CHECK-NEXT: punpklo p0.h, p0.b 111; CHECK-NEXT: punpkhi p2.h, p1.b 112; CHECK-NEXT: punpklo p1.h, p1.b 113; CHECK-NEXT: st1d { z3.d }, p2, [x0, #3, mul vl] 114; CHECK-NEXT: punpkhi p2.h, p0.b 115; CHECK-NEXT: punpklo p0.h, p0.b 116; CHECK-NEXT: st1d { z2.d }, p1, [x0, #2, mul vl] 117; CHECK-NEXT: st1d { z1.d }, p2, [x0, #1, mul vl] 118; CHECK-NEXT: st1d { z0.d }, p0, [x0] 119; CHECK-NEXT: ret 120 call void @llvm.masked.store.nxv8i64(<vscale x 8 x i64> %data, ptr %a, i32 1, <vscale x 8 x i1> %pg) 121 ret void 122} 123 124declare void @llvm.masked.store.nxv2i8(<vscale x 2 x i8>, ptr, i32, <vscale x 2 x i1>) 125declare void @llvm.masked.store.nxv32i8(<vscale x 32 x i8>, ptr, i32, <vscale x 32 x i1>) 126 127declare void @llvm.masked.store.nxv32i16(<vscale x 32 x i16>, ptr, i32, <vscale x 32 x i1>) 128 129declare void @llvm.masked.store.nxv8i32(<vscale x 8 x i32>, ptr, i32, <vscale x 8 x i1>) 130 131declare void @llvm.masked.store.nxv8i64(<vscale x 8 x i64>, ptr, i32, <vscale x 8 x i1>) 132