xref: /llvm-project/llvm/test/CodeGen/AArch64/sve-sext-zext.ll (revision 64094e3e6df223cde2861b89c31bb529bb36f8f7) 
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple=aarch64--linux-gnu -mattr=+sve < %s | FileCheck %s
3
4define <vscale x 16 x i8> @sext_i1_i8(<vscale x 16 x i1> %a) {
5; CHECK-LABEL: sext_i1_i8:
6; CHECK:       // %bb.0:
7; CHECK-NEXT:    mov z0.b, p0/z, #-1 // =0xffffffffffffffff
8; CHECK-NEXT:    ret
9  %r = sext <vscale x 16 x i1> %a to <vscale x 16 x i8>
10  ret <vscale x 16 x i8> %r
11}
12
13define <vscale x 8 x i16> @sext_i1_i16(<vscale x 8 x i1> %a) {
14; CHECK-LABEL: sext_i1_i16:
15; CHECK:       // %bb.0:
16; CHECK-NEXT:    mov z0.h, p0/z, #-1 // =0xffffffffffffffff
17; CHECK-NEXT:    ret
18  %r = sext <vscale x 8 x i1> %a to <vscale x 8 x i16>
19  ret <vscale x 8 x i16> %r
20}
21
22define <vscale x 4 x i32> @sext_i1_i32(<vscale x 4 x i1> %a) {
23; CHECK-LABEL: sext_i1_i32:
24; CHECK:       // %bb.0:
25; CHECK-NEXT:    mov z0.s, p0/z, #-1 // =0xffffffffffffffff
26; CHECK-NEXT:    ret
27  %r = sext <vscale x 4 x i1> %a to <vscale x 4 x i32>
28  ret <vscale x 4 x i32> %r
29}
30
31define <vscale x 2 x i64> @sext_i1_i64(<vscale x 2 x i1> %a) {
32; CHECK-LABEL: sext_i1_i64:
33; CHECK:       // %bb.0:
34; CHECK-NEXT:    mov z0.d, p0/z, #-1 // =0xffffffffffffffff
35; CHECK-NEXT:    ret
36  %r = sext <vscale x 2 x i1> %a to <vscale x 2 x i64>
37  ret <vscale x 2 x i64> %r
38}
39
40define <vscale x 16 x i8> @zext_i1_i8(<vscale x 16 x i1> %a) {
41; CHECK-LABEL: zext_i1_i8:
42; CHECK:       // %bb.0:
43; CHECK-NEXT:    mov z0.b, p0/z, #1 // =0x1
44; CHECK-NEXT:    ret
45  %r = zext <vscale x 16 x i1> %a to <vscale x 16 x i8>
46  ret <vscale x 16 x i8> %r
47}
48
49define <vscale x 8 x i16> @zext_i1_i16(<vscale x 8 x i1> %a) {
50; CHECK-LABEL: zext_i1_i16:
51; CHECK:       // %bb.0:
52; CHECK-NEXT:    mov z0.h, p0/z, #1 // =0x1
53; CHECK-NEXT:    ret
54  %r = zext <vscale x 8 x i1> %a to <vscale x 8 x i16>
55  ret <vscale x 8 x i16> %r
56}
57
58define <vscale x 4 x i32> @zext_i1_i32(<vscale x 4 x i1> %a) {
59; CHECK-LABEL: zext_i1_i32:
60; CHECK:       // %bb.0:
61; CHECK-NEXT:    mov z0.s, p0/z, #1 // =0x1
62; CHECK-NEXT:    ret
63  %r = zext <vscale x 4 x i1> %a to <vscale x 4 x i32>
64  ret <vscale x 4 x i32> %r
65}
66
67define <vscale x 2 x i64> @zext_i1_i64(<vscale x 2 x i1> %a) {
68; CHECK-LABEL: zext_i1_i64:
69; CHECK:       // %bb.0:
70; CHECK-NEXT:    mov z0.d, p0/z, #1 // =0x1
71; CHECK-NEXT:    ret
72  %r = zext <vscale x 2 x i1> %a to <vscale x 2 x i64>
73  ret <vscale x 2 x i64> %r
74}
75
76define <vscale x 8 x i16> @sext_i8_i16(<vscale x 8 x i8> %a) {
77; CHECK-LABEL: sext_i8_i16:
78; CHECK:       // %bb.0:
79; CHECK-NEXT:    ptrue p0.h
80; CHECK-NEXT:    sxtb z0.h, p0/m, z0.h
81; CHECK-NEXT:    ret
82  %r = sext <vscale x 8 x i8> %a to <vscale x 8 x i16>
83  ret <vscale x 8 x i16> %r
84}
85
86define <vscale x 4 x i32> @sext_i8_i32(<vscale x 4 x i8> %a) {
87; CHECK-LABEL: sext_i8_i32:
88; CHECK:       // %bb.0:
89; CHECK-NEXT:    ptrue p0.s
90; CHECK-NEXT:    sxtb z0.s, p0/m, z0.s
91; CHECK-NEXT:    ret
92  %r = sext <vscale x 4 x i8> %a to <vscale x 4 x i32>
93  ret <vscale x 4 x i32> %r
94}
95
96define <vscale x 2 x i64> @sext_i8_i64(<vscale x 2 x i8> %a) {
97; CHECK-LABEL: sext_i8_i64:
98; CHECK:       // %bb.0:
99; CHECK-NEXT:    ptrue p0.d
100; CHECK-NEXT:    sxtb z0.d, p0/m, z0.d
101; CHECK-NEXT:    ret
102  %r = sext <vscale x 2 x i8> %a to <vscale x 2 x i64>
103  ret <vscale x 2 x i64> %r
104}
105
106define <vscale x 8 x i16> @zext_i8_i16(<vscale x 8 x i8> %a) {
107; CHECK-LABEL: zext_i8_i16:
108; CHECK:       // %bb.0:
109; CHECK-NEXT:    and z0.h, z0.h, #0xff
110; CHECK-NEXT:    ret
111  %r = zext <vscale x 8 x i8> %a to <vscale x 8 x i16>
112  ret <vscale x 8 x i16> %r
113}
114
115define <vscale x 4 x i32> @zext_i8_i32(<vscale x 4 x i8> %a) {
116; CHECK-LABEL: zext_i8_i32:
117; CHECK:       // %bb.0:
118; CHECK-NEXT:    and z0.s, z0.s, #0xff
119; CHECK-NEXT:    ret
120  %r = zext <vscale x 4 x i8> %a to <vscale x 4 x i32>
121  ret <vscale x 4 x i32> %r
122}
123
124define <vscale x 2 x i64> @zext_i8_i64(<vscale x 2 x i8> %a) {
125; CHECK-LABEL: zext_i8_i64:
126; CHECK:       // %bb.0:
127; CHECK-NEXT:    and z0.d, z0.d, #0xff
128; CHECK-NEXT:    ret
129  %r = zext <vscale x 2 x i8> %a to <vscale x 2 x i64>
130  ret <vscale x 2 x i64> %r
131}
132
133define <vscale x 4 x i32> @sext_i16_i32(<vscale x 4 x i16> %a) {
134; CHECK-LABEL: sext_i16_i32:
135; CHECK:       // %bb.0:
136; CHECK-NEXT:    ptrue p0.s
137; CHECK-NEXT:    sxth z0.s, p0/m, z0.s
138; CHECK-NEXT:    ret
139  %r = sext <vscale x 4 x i16> %a to <vscale x 4 x i32>
140  ret <vscale x 4 x i32> %r
141}
142
143define <vscale x 2 x i64> @sext_i16_i64(<vscale x 2 x i16> %a) {
144; CHECK-LABEL: sext_i16_i64:
145; CHECK:       // %bb.0:
146; CHECK-NEXT:    ptrue p0.d
147; CHECK-NEXT:    sxth z0.d, p0/m, z0.d
148; CHECK-NEXT:    ret
149  %r = sext <vscale x 2 x i16> %a to <vscale x 2 x i64>
150  ret <vscale x 2 x i64> %r
151}
152
153define <vscale x 4 x i32> @zext_i16_i32(<vscale x 4 x i16> %a) {
154; CHECK-LABEL: zext_i16_i32:
155; CHECK:       // %bb.0:
156; CHECK-NEXT:    and z0.s, z0.s, #0xffff
157; CHECK-NEXT:    ret
158  %r = zext <vscale x 4 x i16> %a to <vscale x 4 x i32>
159  ret <vscale x 4 x i32> %r
160}
161
162define <vscale x 2 x i64> @zext_i16_i64(<vscale x 2 x i16> %a) {
163; CHECK-LABEL: zext_i16_i64:
164; CHECK:       // %bb.0:
165; CHECK-NEXT:    and z0.d, z0.d, #0xffff
166; CHECK-NEXT:    ret
167  %r = zext <vscale x 2 x i16> %a to <vscale x 2 x i64>
168  ret <vscale x 2 x i64> %r
169}
170
171define <vscale x 2 x i64> @sext_i32_i64(<vscale x 2 x i32> %a) {
172; CHECK-LABEL: sext_i32_i64:
173; CHECK:       // %bb.0:
174; CHECK-NEXT:    ptrue p0.d
175; CHECK-NEXT:    sxtw z0.d, p0/m, z0.d
176; CHECK-NEXT:    ret
177  %r = sext <vscale x 2 x i32> %a to <vscale x 2 x i64>
178  ret <vscale x 2 x i64> %r
179}
180
181define <vscale x 2 x i64> @zext_i32_i64(<vscale x 2 x i32> %a) {
182; CHECK-LABEL: zext_i32_i64:
183; CHECK:       // %bb.0:
184; CHECK-NEXT:    and z0.d, z0.d, #0xffffffff
185; CHECK-NEXT:    ret
186  %r = zext <vscale x 2 x i32> %a to <vscale x 2 x i64>
187  ret <vscale x 2 x i64> %r
188}
189
190; Extending to illegal types
191
192define <vscale x 16 x i16> @sext_b_to_h(<vscale x 16 x i8> %a) {
193; CHECK-LABEL: sext_b_to_h:
194; CHECK:       // %bb.0:
195; CHECK-NEXT:    sunpklo z2.h, z0.b
196; CHECK-NEXT:    sunpkhi z1.h, z0.b
197; CHECK-NEXT:    mov z0.d, z2.d
198; CHECK-NEXT:    ret
199  %ext = sext <vscale x 16 x i8> %a to <vscale x 16 x i16>
200  ret <vscale x 16 x i16> %ext
201}
202
203define <vscale x 8 x i32> @sext_h_to_s(<vscale x 8 x i16> %a) {
204; CHECK-LABEL: sext_h_to_s:
205; CHECK:       // %bb.0:
206; CHECK-NEXT:    sunpklo z2.s, z0.h
207; CHECK-NEXT:    sunpkhi z1.s, z0.h
208; CHECK-NEXT:    mov z0.d, z2.d
209; CHECK-NEXT:    ret
210  %ext = sext <vscale x 8 x i16> %a to <vscale x 8 x i32>
211  ret <vscale x 8 x i32> %ext
212}
213
214define <vscale x 4 x i64> @sext_s_to_d(<vscale x 4 x i32> %a) {
215; CHECK-LABEL: sext_s_to_d:
216; CHECK:       // %bb.0:
217; CHECK-NEXT:    sunpklo z2.d, z0.s
218; CHECK-NEXT:    sunpkhi z1.d, z0.s
219; CHECK-NEXT:    mov z0.d, z2.d
220; CHECK-NEXT:    ret
221  %ext = sext <vscale x 4 x i32> %a to <vscale x 4 x i64>
222  ret <vscale x 4 x i64> %ext
223}
224
225define <vscale x 16 x i32> @sext_b_to_s(<vscale x 16 x i8> %a) {
226; CHECK-LABEL: sext_b_to_s:
227; CHECK:       // %bb.0:
228; CHECK-NEXT:    sunpklo z1.h, z0.b
229; CHECK-NEXT:    sunpkhi z3.h, z0.b
230; CHECK-NEXT:    sunpklo z0.s, z1.h
231; CHECK-NEXT:    sunpkhi z1.s, z1.h
232; CHECK-NEXT:    sunpklo z2.s, z3.h
233; CHECK-NEXT:    sunpkhi z3.s, z3.h
234; CHECK-NEXT:    ret
235  %ext = sext <vscale x 16 x i8> %a to <vscale x 16 x i32>
236  ret <vscale x 16 x i32> %ext
237}
238
239define <vscale x 16 x i64> @sext_b_to_d(<vscale x 16 x i8> %a) {
240; CHECK-LABEL: sext_b_to_d:
241; CHECK:       // %bb.0:
242; CHECK-NEXT:    sunpklo z1.h, z0.b
243; CHECK-NEXT:    sunpkhi z0.h, z0.b
244; CHECK-NEXT:    sunpklo z2.s, z1.h
245; CHECK-NEXT:    sunpkhi z3.s, z1.h
246; CHECK-NEXT:    sunpklo z5.s, z0.h
247; CHECK-NEXT:    sunpkhi z7.s, z0.h
248; CHECK-NEXT:    sunpklo z0.d, z2.s
249; CHECK-NEXT:    sunpkhi z1.d, z2.s
250; CHECK-NEXT:    sunpklo z2.d, z3.s
251; CHECK-NEXT:    sunpkhi z3.d, z3.s
252; CHECK-NEXT:    sunpklo z4.d, z5.s
253; CHECK-NEXT:    sunpkhi z5.d, z5.s
254; CHECK-NEXT:    sunpklo z6.d, z7.s
255; CHECK-NEXT:    sunpkhi z7.d, z7.s
256; CHECK-NEXT:    ret
257  %ext = sext <vscale x 16 x i8> %a to <vscale x 16 x i64>
258  ret <vscale x 16 x i64> %ext
259}
260
261define <vscale x 16 x i16> @zext_b_to_h(<vscale x 16 x i8> %a) {
262; CHECK-LABEL: zext_b_to_h:
263; CHECK:       // %bb.0:
264; CHECK-NEXT:    uunpklo z2.h, z0.b
265; CHECK-NEXT:    uunpkhi z1.h, z0.b
266; CHECK-NEXT:    mov z0.d, z2.d
267; CHECK-NEXT:    ret
268  %ext = zext <vscale x 16 x i8> %a to <vscale x 16 x i16>
269  ret <vscale x 16 x i16> %ext
270}
271
272define <vscale x 8 x i32> @zext_h_to_s(<vscale x 8 x i16> %a) {
273; CHECK-LABEL: zext_h_to_s:
274; CHECK:       // %bb.0:
275; CHECK-NEXT:    uunpklo z2.s, z0.h
276; CHECK-NEXT:    uunpkhi z1.s, z0.h
277; CHECK-NEXT:    mov z0.d, z2.d
278; CHECK-NEXT:    ret
279  %ext = zext <vscale x 8 x i16> %a to <vscale x 8 x i32>
280  ret <vscale x 8 x i32> %ext
281}
282
283define <vscale x 4 x i64> @zext_s_to_d(<vscale x 4 x i32> %a) {
284; CHECK-LABEL: zext_s_to_d:
285; CHECK:       // %bb.0:
286; CHECK-NEXT:    uunpklo z2.d, z0.s
287; CHECK-NEXT:    uunpkhi z1.d, z0.s
288; CHECK-NEXT:    mov z0.d, z2.d
289; CHECK-NEXT:    ret
290  %ext = zext <vscale x 4 x i32> %a to <vscale x 4 x i64>
291  ret <vscale x 4 x i64> %ext
292}
293
294define <vscale x 16 x i32> @zext_b_to_s(<vscale x 16 x i8> %a) {
295; CHECK-LABEL: zext_b_to_s:
296; CHECK:       // %bb.0:
297; CHECK-NEXT:    uunpklo z1.h, z0.b
298; CHECK-NEXT:    uunpkhi z3.h, z0.b
299; CHECK-NEXT:    uunpklo z0.s, z1.h
300; CHECK-NEXT:    uunpkhi z1.s, z1.h
301; CHECK-NEXT:    uunpklo z2.s, z3.h
302; CHECK-NEXT:    uunpkhi z3.s, z3.h
303; CHECK-NEXT:    ret
304  %ext = zext <vscale x 16 x i8> %a to <vscale x 16 x i32>
305  ret <vscale x 16 x i32> %ext
306}
307
308define <vscale x 16 x i64> @zext_b_to_d(<vscale x 16 x i8> %a) {
309; CHECK-LABEL: zext_b_to_d:
310; CHECK:       // %bb.0:
311; CHECK-NEXT:    uunpklo z1.h, z0.b
312; CHECK-NEXT:    uunpkhi z0.h, z0.b
313; CHECK-NEXT:    uunpklo z2.s, z1.h
314; CHECK-NEXT:    uunpkhi z3.s, z1.h
315; CHECK-NEXT:    uunpklo z5.s, z0.h
316; CHECK-NEXT:    uunpkhi z7.s, z0.h
317; CHECK-NEXT:    uunpklo z0.d, z2.s
318; CHECK-NEXT:    uunpkhi z1.d, z2.s
319; CHECK-NEXT:    uunpklo z2.d, z3.s
320; CHECK-NEXT:    uunpkhi z3.d, z3.s
321; CHECK-NEXT:    uunpklo z4.d, z5.s
322; CHECK-NEXT:    uunpkhi z5.d, z5.s
323; CHECK-NEXT:    uunpklo z6.d, z7.s
324; CHECK-NEXT:    uunpkhi z7.d, z7.s
325; CHECK-NEXT:    ret
326  %ext = zext <vscale x 16 x i8> %a to <vscale x 16 x i64>
327  ret <vscale x 16 x i64> %ext
328}
329
330; Extending unpacked data to wide, illegal types
331
332define <vscale x 4 x i64> @zext_4i8_4i64(<vscale x 4 x i8> %aval) {
333; CHECK-LABEL: zext_4i8_4i64:
334; CHECK:       // %bb.0:
335; CHECK-NEXT:    and z0.s, z0.s, #0xff
336; CHECK-NEXT:    uunpklo z2.d, z0.s
337; CHECK-NEXT:    uunpkhi z1.d, z0.s
338; CHECK-NEXT:    mov z0.d, z2.d
339; CHECK-NEXT:    ret
340  %aext = zext <vscale x 4 x i8> %aval to <vscale x 4 x i64>
341  ret <vscale x 4 x i64> %aext
342}
343
344define <vscale x 4 x i64> @zext_4i16_4i64(<vscale x 4 x i16> %aval) {
345; CHECK-LABEL: zext_4i16_4i64:
346; CHECK:       // %bb.0:
347; CHECK-NEXT:    and z0.s, z0.s, #0xffff
348; CHECK-NEXT:    uunpklo z2.d, z0.s
349; CHECK-NEXT:    uunpkhi z1.d, z0.s
350; CHECK-NEXT:    mov z0.d, z2.d
351; CHECK-NEXT:    ret
352  %aext = zext <vscale x 4 x i16> %aval to <vscale x 4 x i64>
353  ret <vscale x 4 x i64> %aext
354}
355
356define <vscale x 8 x i32> @zext_8i8_8i32(<vscale x 8 x i8> %aval) {
357; CHECK-LABEL: zext_8i8_8i32:
358; CHECK:       // %bb.0:
359; CHECK-NEXT:    and z0.h, z0.h, #0xff
360; CHECK-NEXT:    uunpklo z2.s, z0.h
361; CHECK-NEXT:    uunpkhi z1.s, z0.h
362; CHECK-NEXT:    mov z0.d, z2.d
363; CHECK-NEXT:    ret
364  %aext = zext <vscale x 8 x i8> %aval to <vscale x 8 x i32>
365  ret <vscale x 8 x i32> %aext
366}
367
368define <vscale x 8 x i64> @zext_8i8_8i64(<vscale x 8 x i8> %aval) {
369; CHECK-LABEL: zext_8i8_8i64:
370; CHECK:       // %bb.0:
371; CHECK-NEXT:    and z0.h, z0.h, #0xff
372; CHECK-NEXT:    uunpklo z1.s, z0.h
373; CHECK-NEXT:    uunpkhi z3.s, z0.h
374; CHECK-NEXT:    uunpklo z0.d, z1.s
375; CHECK-NEXT:    uunpkhi z1.d, z1.s
376; CHECK-NEXT:    uunpklo z2.d, z3.s
377; CHECK-NEXT:    uunpkhi z3.d, z3.s
378; CHECK-NEXT:    ret
379  %aext = zext <vscale x 8 x i8> %aval to <vscale x 8 x i64>
380  ret <vscale x 8 x i64> %aext
381}
382
383define <vscale x 4 x i64> @sext_4i8_4i64(<vscale x 4 x i8> %aval) {
384; CHECK-LABEL: sext_4i8_4i64:
385; CHECK:       // %bb.0:
386; CHECK-NEXT:    ptrue p0.s
387; CHECK-NEXT:    movprfx z1, z0
388; CHECK-NEXT:    sxtb z1.s, p0/m, z0.s
389; CHECK-NEXT:    sunpklo z0.d, z1.s
390; CHECK-NEXT:    sunpkhi z1.d, z1.s
391; CHECK-NEXT:    ret
392  %aext = sext <vscale x 4 x i8> %aval to <vscale x 4 x i64>
393  ret <vscale x 4 x i64> %aext
394}
395
396define <vscale x 4 x i64> @sext_4i16_4i64(<vscale x 4 x i16> %aval) {
397; CHECK-LABEL: sext_4i16_4i64:
398; CHECK:       // %bb.0:
399; CHECK-NEXT:    ptrue p0.s
400; CHECK-NEXT:    movprfx z1, z0
401; CHECK-NEXT:    sxth z1.s, p0/m, z0.s
402; CHECK-NEXT:    sunpklo z0.d, z1.s
403; CHECK-NEXT:    sunpkhi z1.d, z1.s
404; CHECK-NEXT:    ret
405  %aext = sext <vscale x 4 x i16> %aval to <vscale x 4 x i64>
406  ret <vscale x 4 x i64> %aext
407}
408
409define <vscale x 8 x i32> @sext_8i8_8i32(<vscale x 8 x i8> %aval) {
410; CHECK-LABEL: sext_8i8_8i32:
411; CHECK:       // %bb.0:
412; CHECK-NEXT:    ptrue p0.h
413; CHECK-NEXT:    movprfx z1, z0
414; CHECK-NEXT:    sxtb z1.h, p0/m, z0.h
415; CHECK-NEXT:    sunpklo z0.s, z1.h
416; CHECK-NEXT:    sunpkhi z1.s, z1.h
417; CHECK-NEXT:    ret
418  %aext = sext <vscale x 8 x i8> %aval to <vscale x 8 x i32>
419  ret <vscale x 8 x i32> %aext
420}
421
422define <vscale x 8 x i64> @sext_8i8_8i64(<vscale x 8 x i8> %aval) {
423; CHECK-LABEL: sext_8i8_8i64:
424; CHECK:       // %bb.0:
425; CHECK-NEXT:    ptrue p0.h
426; CHECK-NEXT:    sxtb z0.h, p0/m, z0.h
427; CHECK-NEXT:    sunpklo z1.s, z0.h
428; CHECK-NEXT:    sunpkhi z3.s, z0.h
429; CHECK-NEXT:    sunpklo z0.d, z1.s
430; CHECK-NEXT:    sunpkhi z1.d, z1.s
431; CHECK-NEXT:    sunpklo z2.d, z3.s
432; CHECK-NEXT:    sunpkhi z3.d, z3.s
433; CHECK-NEXT:    ret
434  %aext = sext <vscale x 8 x i8> %aval to <vscale x 8 x i64>
435  ret <vscale x 8 x i64> %aext
436}
437
438
439; Extending non power-of-two types
440
441define <vscale x 2 x i64> @sext_i18_i64(<vscale x 2 x i18> %a) {
442; CHECK-LABEL: sext_i18_i64:
443; CHECK:       // %bb.0:
444; CHECK-NEXT:    lsl z0.d, z0.d, #46
445; CHECK-NEXT:    asr z0.d, z0.d, #46
446; CHECK-NEXT:    ret
447  %r = sext <vscale x 2 x i18> %a to <vscale x 2 x i64>
448  ret <vscale x 2 x i64> %r
449}
450
451define <vscale x 2 x i64> @zext_i18_i64(<vscale x 2 x i18> %a) {
452; CHECK-LABEL: zext_i18_i64:
453; CHECK:       // %bb.0:
454; CHECK-NEXT:    and z0.d, z0.d, #0x3ffff
455; CHECK-NEXT:    ret
456  %r = zext <vscale x 2 x i18> %a to <vscale x 2 x i64>
457  ret <vscale x 2 x i64> %r
458}
459