1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc < %s | FileCheck %s 3 4target triple = "aarch64-unknown-linux-gnu" 5 6define <vscale x 16 x i8> @sdiv_i8(<vscale x 16 x i8> %a) #0 { 7; CHECK-LABEL: sdiv_i8: 8; CHECK: // %bb.0: 9; CHECK-NEXT: ptrue p0.b 10; CHECK-NEXT: asrd z0.b, p0/m, z0.b, #4 11; CHECK-NEXT: ret 12 %out = sdiv <vscale x 16 x i8> %a, splat (i8 16) 13 ret <vscale x 16 x i8> %out 14} 15 16define <vscale x 16 x i8> @sdiv_i8_neg(<vscale x 16 x i8> %a) #0 { 17; CHECK-LABEL: sdiv_i8_neg: 18; CHECK: // %bb.0: 19; CHECK-NEXT: ptrue p0.b 20; CHECK-NEXT: asrd z0.b, p0/m, z0.b, #6 21; CHECK-NEXT: subr z0.b, z0.b, #0 // =0x0 22; CHECK-NEXT: ret 23 %out = sdiv <vscale x 16 x i8> %a, splat (i8 -64) 24 ret <vscale x 16 x i8> %out 25} 26 27define <vscale x 8 x i16> @sdiv_i16(<vscale x 8 x i16> %a) #0 { 28; CHECK-LABEL: sdiv_i16: 29; CHECK: // %bb.0: 30; CHECK-NEXT: ptrue p0.h 31; CHECK-NEXT: asrd z0.h, p0/m, z0.h, #10 32; CHECK-NEXT: ret 33 %out = sdiv <vscale x 8 x i16> %a, splat (i16 1024) 34 ret <vscale x 8 x i16> %out 35} 36 37define <vscale x 8 x i16> @sdiv_i16_neg(<vscale x 8 x i16> %a) #0 { 38; CHECK-LABEL: sdiv_i16_neg: 39; CHECK: // %bb.0: 40; CHECK-NEXT: ptrue p0.h 41; CHECK-NEXT: asrd z0.h, p0/m, z0.h, #12 42; CHECK-NEXT: subr z0.h, z0.h, #0 // =0x0 43; CHECK-NEXT: ret 44 %out = sdiv <vscale x 8 x i16> %a, splat (i16 -4096) 45 ret <vscale x 8 x i16> %out 46} 47 48define <vscale x 4 x i32> @sdiv_i32(<vscale x 4 x i32> %a) #0 { 49; CHECK-LABEL: sdiv_i32: 50; CHECK: // %bb.0: 51; CHECK-NEXT: ptrue p0.s 52; CHECK-NEXT: asrd z0.s, p0/m, z0.s, #23 53; CHECK-NEXT: ret 54 %out = sdiv <vscale x 4 x i32> %a, splat (i32 8388608) 55 ret <vscale x 4 x i32> %out 56} 57 58define <vscale x 4 x i32> @sdiv_i32_neg(<vscale x 4 x i32> %a) #0 { 59; CHECK-LABEL: sdiv_i32_neg: 60; CHECK: // %bb.0: 61; CHECK-NEXT: ptrue p0.s 62; CHECK-NEXT: asrd z0.s, p0/m, z0.s, #25 63; CHECK-NEXT: subr z0.s, z0.s, #0 // =0x0 64; CHECK-NEXT: ret 65 %out = sdiv <vscale x 4 x i32> %a, splat (i32 -33554432) 66 ret <vscale x 4 x i32> %out 67} 68 69define <vscale x 2 x i64> @sdiv_i64(<vscale x 2 x i64> %a) #0 { 70; CHECK-LABEL: sdiv_i64: 71; CHECK: // %bb.0: 72; CHECK-NEXT: ptrue p0.d 73; CHECK-NEXT: asrd z0.d, p0/m, z0.d, #53 74; CHECK-NEXT: ret 75 %out = sdiv <vscale x 2 x i64> %a, splat (i64 9007199254740992) 76 ret <vscale x 2 x i64> %out 77} 78 79define <vscale x 2 x i64> @sdiv_i64_neg(<vscale x 2 x i64> %a) #0 { 80; CHECK-LABEL: sdiv_i64_neg: 81; CHECK: // %bb.0: 82; CHECK-NEXT: ptrue p0.d 83; CHECK-NEXT: asrd z0.d, p0/m, z0.d, #55 84; CHECK-NEXT: subr z0.d, z0.d, #0 // =0x0 85; CHECK-NEXT: ret 86 %out = sdiv <vscale x 2 x i64> %a, splat (i64 -36028797018963968) 87 ret <vscale x 2 x i64> %out 88} 89 90attributes #0 = { "target-features"="+sve" } 91