xref: /llvm-project/llvm/test/CodeGen/AArch64/sve-rev.ll (revision 672f673004663aeb15ece1af4b5b219994924167) 
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc < %s | FileCheck %s
3
4target triple = "aarch64-unknown-linux-gnu"
5
6;
7; RBIT
8;
9
10define <vscale x 16 x i8> @bitreverse_i8(<vscale x 16 x i8> %a) #0 {
11; CHECK-LABEL: bitreverse_i8:
12; CHECK:       // %bb.0:
13; CHECK-NEXT:    ptrue p0.b
14; CHECK-NEXT:    rbit z0.b, p0/m, z0.b
15; CHECK-NEXT:    ret
16  %res = call <vscale x 16 x i8> @llvm.bitreverse.nxv16i8(<vscale x 16 x i8> %a)
17  ret <vscale x 16 x i8> %res
18}
19
20define <vscale x 8 x i16> @bitreverse_i16(<vscale x 8 x i16> %a) #0 {
21; CHECK-LABEL: bitreverse_i16:
22; CHECK:       // %bb.0:
23; CHECK-NEXT:    ptrue p0.h
24; CHECK-NEXT:    rbit z0.h, p0/m, z0.h
25; CHECK-NEXT:    ret
26  %res = call <vscale x 8 x i16> @llvm.bitreverse.nxv8i16(<vscale x 8 x i16> %a)
27  ret <vscale x 8 x i16> %res
28}
29
30define <vscale x 4 x i32> @bitreverse_i32(<vscale x 4 x i32> %a) #0 {
31; CHECK-LABEL: bitreverse_i32:
32; CHECK:       // %bb.0:
33; CHECK-NEXT:    ptrue p0.s
34; CHECK-NEXT:    rbit z0.s, p0/m, z0.s
35; CHECK-NEXT:    ret
36  %res = call <vscale x 4 x i32> @llvm.bitreverse.nxv4i32(<vscale x 4 x i32> %a)
37  ret <vscale x 4 x i32> %res
38}
39
40define <vscale x 2 x i64> @bitreverse_i64(<vscale x 2 x i64> %a) #0 {
41; CHECK-LABEL: bitreverse_i64:
42; CHECK:       // %bb.0:
43; CHECK-NEXT:    ptrue p0.d
44; CHECK-NEXT:    rbit z0.d, p0/m, z0.d
45; CHECK-NEXT:    ret
46  %res = call <vscale x 2 x i64> @llvm.bitreverse.nxv2i64(<vscale x 2 x i64> %a)
47  ret <vscale x 2 x i64> %res
48}
49
50;
51; REVB
52;
53
54define <vscale x 8 x i16> @byteswap_i16(<vscale x 8 x i16> %a) #0 {
55; CHECK-LABEL: byteswap_i16:
56; CHECK:       // %bb.0:
57; CHECK-NEXT:    ptrue p0.h
58; CHECK-NEXT:    revb z0.h, p0/m, z0.h
59; CHECK-NEXT:    ret
60  %res = call <vscale x 8 x i16> @llvm.bswap.nxv8i16(<vscale x 8 x i16> %a)
61  ret <vscale x 8 x i16> %res
62}
63
64define <vscale x 4 x i32> @byteswap_i32(<vscale x 4 x i32> %a) #0 {
65; CHECK-LABEL: byteswap_i32:
66; CHECK:       // %bb.0:
67; CHECK-NEXT:    ptrue p0.s
68; CHECK-NEXT:    revb z0.s, p0/m, z0.s
69; CHECK-NEXT:    ret
70  %res = call <vscale x 4 x i32> @llvm.bswap.nxv4i32(<vscale x 4 x i32> %a)
71  ret <vscale x 4 x i32> %res
72}
73
74define <vscale x 2 x i64> @byteswap_i64(<vscale x 2 x i64> %a) #0 {
75; CHECK-LABEL: byteswap_i64:
76; CHECK:       // %bb.0:
77; CHECK-NEXT:    ptrue p0.d
78; CHECK-NEXT:    revb z0.d, p0/m, z0.d
79; CHECK-NEXT:    ret
80  %res = call <vscale x 2 x i64> @llvm.bswap.nxv2i64(<vscale x 2 x i64> %a)
81  ret <vscale x 2 x i64> %res
82}
83
84attributes #0 = { "target-features"="+sve" }
85
86declare <vscale x 16 x i8> @llvm.bitreverse.nxv16i8(<vscale x 16 x i8>)
87declare <vscale x 8 x i16> @llvm.bitreverse.nxv8i16(<vscale x 8 x i16>)
88declare <vscale x 4 x i32> @llvm.bitreverse.nxv4i32(<vscale x 4 x i32>)
89declare <vscale x 2 x i64> @llvm.bitreverse.nxv2i64(<vscale x 2 x i64>)
90
91declare <vscale x 8 x i16> @llvm.bswap.nxv8i16(<vscale x 8 x i16>)
92declare <vscale x 4 x i32> @llvm.bswap.nxv4i32(<vscale x 4 x i32>)
93declare <vscale x 2 x i64> @llvm.bswap.nxv2i64(<vscale x 2 x i64>)
94