xref: /llvm-project/llvm/test/CodeGen/AArch64/sve-ptest-removal-cmphi.ll (revision 2fb3e3c46d57db51459160801f17f6f3b0f83300) 
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple=aarch64--linux-gnu -mattr=+sve %s -o - | FileCheck %s
3
4;
5; Compares
6;
7
8define i32 @cmphi_nxv16i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %a, <vscale x 16 x i8> %b) {
9; CHECK-LABEL: cmphi_nxv16i8:
10; CHECK:       // %bb.0:
11; CHECK-NEXT:    cmphi p0.b, p0/z, z0.b, z1.b
12; CHECK-NEXT:    cset w0, ne
13; CHECK-NEXT:    ret
14  %1 = tail call <vscale x 16 x i1> @llvm.aarch64.sve.cmphi.nxv16i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %a, <vscale x 16 x i8> %b)
15  %2 = tail call i1 @llvm.aarch64.sve.ptest.any.nxv16i1(<vscale x 16 x i1> %pg, <vscale x 16 x i1> %1)
16  %conv = zext i1 %2 to i32
17  ret i32 %conv
18}
19
20define i32 @cmphi_nxv4i32(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %a, <vscale x 4 x i32> %b) {
21; CHECK-LABEL: cmphi_nxv4i32:
22; CHECK:       // %bb.0:
23; CHECK-NEXT:    cmphi p0.s, p0/z, z0.s, z1.s
24; CHECK-NEXT:    cset w0, ne
25; CHECK-NEXT:    ret
26  %1 = tail call <vscale x 4 x i1> @llvm.aarch64.sve.cmphi.nxv4i32(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %a, <vscale x 4 x i32> %b)
27  %2 = tail call i1 @llvm.aarch64.sve.ptest.any.nxv4i1(<vscale x 4 x i1> %pg, <vscale x 4 x i1> %1)
28  %conv = zext i1 %2 to i32
29  ret i32 %conv
30}
31
32
33;
34; Immediate Compares
35;
36
37define i32 @cmphi_imm_nxv16i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %a) {
38; CHECK-LABEL: cmphi_imm_nxv16i8:
39; CHECK:       // %bb.0:
40; CHECK-NEXT:    cmphi p0.b, p0/z, z0.b, #0
41; CHECK-NEXT:    cset w0, ne
42; CHECK-NEXT:    ret
43  %1 = tail call <vscale x 16 x i1> @llvm.aarch64.sve.cmphi.nxv16i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %a, <vscale x 16 x i8> zeroinitializer)
44  %2 = tail call <vscale x 16 x i1> @llvm.aarch64.sve.ptrue.nxv16i1(i32 31)
45  %3 = tail call i1 @llvm.aarch64.sve.ptest.any.nxv16i1(<vscale x 16 x i1> %2, <vscale x 16 x i1> %1)
46  %conv = zext i1 %3 to i32
47  ret i32 %conv
48}
49
50;
51; Wide Compares
52;
53
54define i32 @cmphi_wide_nxv16i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %a, <vscale x 2 x i64> %b) {
55; CHECK-LABEL: cmphi_wide_nxv16i8:
56; CHECK:       // %bb.0:
57; CHECK-NEXT:    cmphi p0.b, p0/z, z0.b, z1.d
58; CHECK-NEXT:    cset w0, ne
59; CHECK-NEXT:    ret
60  %1 = tail call <vscale x 16 x i1> @llvm.aarch64.sve.cmphi.wide.nxv16i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %a, <vscale x 2 x i64> %b)
61  %2 = tail call i1 @llvm.aarch64.sve.ptest.any.nxv16i1(<vscale x 16 x i1> %pg, <vscale x 16 x i1> %1)
62  %conv = zext i1 %2 to i32
63  ret i32 %conv
64}
65
66define i32 @cmphi_wide_nxv8i16(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %a, <vscale x 2 x i64> %b) {
67; CHECK-LABEL: cmphi_wide_nxv8i16:
68; CHECK:       // %bb.0:
69; CHECK-NEXT:    cmphi p0.h, p0/z, z0.h, z1.d
70; CHECK-NEXT:    cset w0, ne
71; CHECK-NEXT:    ret
72  %1 = tail call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %pg)
73  %2 = tail call <vscale x 8 x i1> @llvm.aarch64.sve.cmphi.wide.nxv8i16(<vscale x 8 x i1> %1, <vscale x 8 x i16> %a, <vscale x 2 x i64> %b)
74  %3 = tail call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1> %2)
75  %4 = tail call i1 @llvm.aarch64.sve.ptest.any.nxv16i1(<vscale x 16 x i1> %pg, <vscale x 16 x i1> %3)
76  %conv = zext i1 %4 to i32
77  ret i32 %conv
78}
79
80define i32 @cmphi_wide_nxv4i32(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %a, <vscale x 2 x i64> %b) {
81; CHECK-LABEL: cmphi_wide_nxv4i32:
82; CHECK:       // %bb.0:
83; CHECK-NEXT:    cmphi p0.s, p0/z, z0.s, z1.d
84; CHECK-NEXT:    cset w0, ne
85; CHECK-NEXT:    ret
86  %1 = tail call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %pg)
87  %2 = tail call <vscale x 4 x i1> @llvm.aarch64.sve.cmphi.wide.nxv4i32(<vscale x 4 x i1> %1, <vscale x 4 x i32> %a, <vscale x 2 x i64> %b)
88  %3 = tail call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv4i1(<vscale x 4 x i1> %2)
89  %4 = tail call i1 @llvm.aarch64.sve.ptest.any.nxv16i1(<vscale x 16 x i1> %pg, <vscale x 16 x i1> %3)
90  %conv = zext i1 %4 to i32
91  ret i32 %conv
92}
93
94declare <vscale x 4 x i1> @llvm.aarch64.sve.cmphi.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>)
95declare <vscale x 16 x i1> @llvm.aarch64.sve.cmphi.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 16 x i8>)
96declare <vscale x 16 x i1> @llvm.aarch64.sve.cmphi.wide.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 2 x i64>)
97declare <vscale x 8 x i1> @llvm.aarch64.sve.cmphi.wide.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 2 x i64>)
98declare <vscale x 4 x i1> @llvm.aarch64.sve.cmphi.wide.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 2 x i64>)
99
100declare i1 @llvm.aarch64.sve.ptest.any.nxv4i1(<vscale x 4 x i1>, <vscale x 4 x i1>)
101declare i1 @llvm.aarch64.sve.ptest.any.nxv16i1(<vscale x 16 x i1>, <vscale x 16 x i1>)
102
103declare <vscale x 16 x i1> @llvm.aarch64.sve.ptrue.nxv16i1(i32)
104
105declare <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1>)
106declare <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv4i1(<vscale x 4 x i1>)
107
108declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>)
109declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>)
110