xref: /llvm-project/llvm/test/CodeGen/AArch64/sve-ptest-removal-cmpgt.ll (revision 2fb3e3c46d57db51459160801f17f6f3b0f83300) 
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple=aarch64--linux-gnu -mattr=+sve %s -o - | FileCheck %s
3
4;
5; Compares
6;
7
8define i32 @cmpgt_nxv16i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %a, <vscale x 16 x i8> %b) {
9; CHECK-LABEL: cmpgt_nxv16i8:
10; CHECK:       // %bb.0:
11; CHECK-NEXT:    cmpgt p0.b, p0/z, z0.b, z1.b
12; CHECK-NEXT:    cset w0, ne
13; CHECK-NEXT:    ret
14  %1 = tail call <vscale x 16 x i1> @llvm.aarch64.sve.cmpgt.nxv16i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %a, <vscale x 16 x i8> %b)
15  %2 = tail call i1 @llvm.aarch64.sve.ptest.any.nxv16i1(<vscale x 16 x i1> %pg, <vscale x 16 x i1> %1)
16  %conv = zext i1 %2 to i32
17  ret i32 %conv
18}
19
20define i32 @cmpgt_nxv4i32(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %a, <vscale x 4 x i32> %b) {
21; CHECK-LABEL: cmpgt_nxv4i32:
22; CHECK:       // %bb.0:
23; CHECK-NEXT:    cmpgt p0.s, p0/z, z0.s, z1.s
24; CHECK-NEXT:    cset w0, ne
25; CHECK-NEXT:    ret
26  %1 = tail call <vscale x 4 x i1> @llvm.aarch64.sve.cmpgt.nxv4i32(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %a, <vscale x 4 x i32> %b)
27  %2 = tail call i1 @llvm.aarch64.sve.ptest.any.nxv4i1(<vscale x 4 x i1> %pg, <vscale x 4 x i1> %1)
28  %conv = zext i1 %2 to i32
29  ret i32 %conv
30}
31
32;
33; Immediate Compares
34;
35
36define i32 @cmpgt_imm_nxv16i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %a) {
37; CHECK-LABEL: cmpgt_imm_nxv16i8:
38; CHECK:       // %bb.0:
39; CHECK-NEXT:    cmpgt p0.b, p0/z, z0.b, #0
40; CHECK-NEXT:    cset w0, ne
41; CHECK-NEXT:    ret
42  %1 = tail call <vscale x 16 x i1> @llvm.aarch64.sve.cmpgt.nxv16i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %a, <vscale x 16 x i8> zeroinitializer)
43  %2 = tail call <vscale x 16 x i1> @llvm.aarch64.sve.ptrue.nxv16i1(i32 31)
44  %3 = tail call i1 @llvm.aarch64.sve.ptest.any.nxv16i1(<vscale x 16 x i1> %2, <vscale x 16 x i1> %1)
45  %conv = zext i1 %3 to i32
46  ret i32 %conv
47}
48
49;
50; Wide Compares
51;
52
53define i32 @cmpgt_wide_nxv16i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %a, <vscale x 2 x i64> %b) {
54; CHECK-LABEL: cmpgt_wide_nxv16i8:
55; CHECK:       // %bb.0:
56; CHECK-NEXT:    cmpgt p0.b, p0/z, z0.b, z1.d
57; CHECK-NEXT:    cset w0, ne
58; CHECK-NEXT:    ret
59  %1 = tail call <vscale x 16 x i1> @llvm.aarch64.sve.cmpgt.wide.nxv16i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %a, <vscale x 2 x i64> %b)
60  %2 = tail call i1 @llvm.aarch64.sve.ptest.any.nxv16i1(<vscale x 16 x i1> %pg, <vscale x 16 x i1> %1)
61  %conv = zext i1 %2 to i32
62  ret i32 %conv
63}
64
65define i32 @cmpgt_wide_nxv8i16(<vscale x 16 x i1> %pg, <vscale x 8 x i16> %a, <vscale x 2 x i64> %b) {
66; CHECK-LABEL: cmpgt_wide_nxv8i16:
67; CHECK:       // %bb.0:
68; CHECK-NEXT:    cmpgt p0.h, p0/z, z0.h, z1.d
69; CHECK-NEXT:    cset w0, ne
70; CHECK-NEXT:    ret
71  %1 = tail call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %pg)
72  %2 = tail call <vscale x 8 x i1> @llvm.aarch64.sve.cmpgt.wide.nxv8i16(<vscale x 8 x i1> %1, <vscale x 8 x i16> %a, <vscale x 2 x i64> %b)
73  %3 = tail call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1> %2)
74  %4 = tail call i1 @llvm.aarch64.sve.ptest.any.nxv16i1(<vscale x 16 x i1> %pg, <vscale x 16 x i1> %3)
75  %conv = zext i1 %4 to i32
76  ret i32 %conv
77}
78
79define i32 @cmpgt_wide_nxv4i32(<vscale x 16 x i1> %pg, <vscale x 4 x i32> %a, <vscale x 2 x i64> %b) {
80; CHECK-LABEL: cmpgt_wide_nxv4i32:
81; CHECK:       // %bb.0:
82; CHECK-NEXT:    cmpgt p0.s, p0/z, z0.s, z1.d
83; CHECK-NEXT:    cset w0, ne
84; CHECK-NEXT:    ret
85  %1 = tail call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %pg)
86  %2 = tail call <vscale x 4 x i1> @llvm.aarch64.sve.cmpgt.wide.nxv4i32(<vscale x 4 x i1> %1, <vscale x 4 x i32> %a, <vscale x 2 x i64> %b)
87  %3 = tail call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv4i1(<vscale x 4 x i1> %2)
88  %4 = tail call i1 @llvm.aarch64.sve.ptest.any.nxv16i1(<vscale x 16 x i1> %pg, <vscale x 16 x i1> %3)
89  %conv = zext i1 %4 to i32
90  ret i32 %conv
91}
92
93declare <vscale x 4 x i1> @llvm.aarch64.sve.cmpgt.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>)
94declare <vscale x 16 x i1> @llvm.aarch64.sve.cmpgt.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 16 x i8>)
95declare <vscale x 16 x i1> @llvm.aarch64.sve.cmpgt.wide.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 2 x i64>)
96declare <vscale x 8 x i1> @llvm.aarch64.sve.cmpgt.wide.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 2 x i64>)
97declare <vscale x 4 x i1> @llvm.aarch64.sve.cmpgt.wide.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 2 x i64>)
98
99declare i1 @llvm.aarch64.sve.ptest.any.nxv4i1(<vscale x 4 x i1>, <vscale x 4 x i1>)
100declare i1 @llvm.aarch64.sve.ptest.any.nxv16i1(<vscale x 16 x i1>, <vscale x 16 x i1>)
101
102declare <vscale x 4 x i1> @llvm.aarch64.sve.ptrue.nxv4i1(i32)
103declare <vscale x 16 x i1> @llvm.aarch64.sve.ptrue.nxv16i1(i32)
104
105declare <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1>)
106declare <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv4i1(<vscale x 4 x i1>)
107
108declare <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1>)
109declare <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1>)
110