xref: /llvm-project/llvm/test/CodeGen/AArch64/sve-ptest-removal-brk.ll (revision 1e02a29e4753ef70d7ce0ad90b7e4f29f1223006) 
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple=aarch64--linux-gnu -mattr=+sve %s -o - | FileCheck %s
3
4; Test that redundant ptest instruction is removed when using a flag setting brk
5
6define i32 @brkpa(<vscale x 16 x i1> %pg, <vscale x 16 x i1> %a, <vscale x 16 x i1> %b) {
7; CHECK-LABEL: brkpa:
8; CHECK:       // %bb.0:
9; CHECK-NEXT:    brkpas p0.b, p0/z, p1.b, p2.b
10; CHECK-NEXT:    cset w0, ne
11; CHECK-NEXT:    ret
12  %1 = tail call <vscale x 16 x i1> @llvm.aarch64.sve.brkpa.z.nxv16i1(<vscale x 16 x i1> %pg, <vscale x 16 x i1> %a, <vscale x 16 x i1> %b)
13  %2 = tail call i1 @llvm.aarch64.sve.ptest.any.nxv16i1(<vscale x 16 x i1> %pg, <vscale x 16 x i1> %1)
14  %conv = zext i1 %2 to i32
15  ret i32 %conv
16}
17
18define i32 @brkpb(<vscale x 16 x i1> %pg, <vscale x 16 x i1> %a, <vscale x 16 x i1> %b) {
19; CHECK-LABEL: brkpb:
20; CHECK:       // %bb.0:
21; CHECK-NEXT:    brkpbs p0.b, p0/z, p1.b, p2.b
22; CHECK-NEXT:    cset w0, ne
23; CHECK-NEXT:    ret
24  %1 = tail call <vscale x 16 x i1> @llvm.aarch64.sve.brkpb.z.nxv16i1(<vscale x 16 x i1> %pg, <vscale x 16 x i1> %a, <vscale x 16 x i1> %b)
25  %2 = tail call i1 @llvm.aarch64.sve.ptest.any.nxv16i1(<vscale x 16 x i1> %pg, <vscale x 16 x i1> %1)
26  %conv = zext i1 %2 to i32
27  ret i32 %conv
28}
29
30define i32 @brka(<vscale x 16 x i1> %pg, <vscale x 16 x i1> %a) {
31; CHECK-LABEL: brka:
32; CHECK:       // %bb.0:
33; CHECK-NEXT:    brkas p0.b, p0/z, p1.b
34; CHECK-NEXT:    cset w0, ne
35; CHECK-NEXT:    ret
36  %1 = tail call <vscale x 16 x i1> @llvm.aarch64.sve.brka.z.nxv16i1(<vscale x 16 x i1> %pg, <vscale x 16 x i1> %a)
37  %2 = tail call i1 @llvm.aarch64.sve.ptest.any.nxv16i1(<vscale x 16 x i1> %pg, <vscale x 16 x i1> %1)
38  %conv = zext i1 %2 to i32
39  ret i32 %conv
40}
41
42define i32 @brkb(<vscale x 16 x i1> %pg, <vscale x 16 x i1> %a) {
43; CHECK-LABEL: brkb:
44; CHECK:       // %bb.0:
45; CHECK-NEXT:    brkbs p0.b, p0/z, p1.b
46; CHECK-NEXT:    cset w0, ne
47; CHECK-NEXT:    ret
48  %1 = tail call <vscale x 16 x i1> @llvm.aarch64.sve.brkb.z.nxv16i1(<vscale x 16 x i1> %pg, <vscale x 16 x i1> %a)
49  %2 = tail call i1 @llvm.aarch64.sve.ptest.any.nxv16i1(<vscale x 16 x i1> %pg, <vscale x 16 x i1> %1)
50  %conv = zext i1 %2 to i32
51  ret i32 %conv
52}
53
54define i32 @brkn_all_active(<vscale x 16 x i1> %pg, <vscale x 16 x i1> %a, <vscale x 16 x i1> %b) {
55; CHECK-LABEL: brkn_all_active:
56; CHECK:       // %bb.0:
57; CHECK-NEXT:    brkns p2.b, p0/z, p1.b, p2.b
58; CHECK-NEXT:    cset w0, ne
59; CHECK-NEXT:    ret
60  %1 = tail call <vscale x 16 x i1> @llvm.aarch64.sve.brkn.z.nxv16i1(<vscale x 16 x i1> %pg, <vscale x 16 x i1> %a, <vscale x 16 x i1> %b)
61  %2 = call <vscale x 16 x i1> @llvm.aarch64.sve.ptrue.nxv16i1(i32 31)
62  %3 = tail call i1 @llvm.aarch64.sve.ptest.any.nxv16i1(<vscale x 16 x i1> %2, <vscale x 16 x i1> %1)
63  %conv = zext i1 %3 to i32
64  ret i32 %conv
65}
66
67; Test that ptest instruction is not removed when using a non-flag setting brk
68
69define i32 @brkpa_neg(<vscale x 16 x i1> %pg, <vscale x 16 x i1> %a, <vscale x 16 x i1> %b) {
70; CHECK-LABEL: brkpa_neg:
71; CHECK:       // %bb.0:
72; CHECK-NEXT:    brkpa p0.b, p0/z, p1.b, p2.b
73; CHECK-NEXT:    ptest p1, p0.b
74; CHECK-NEXT:    cset w0, ne
75; CHECK-NEXT:    ret
76  %1 = tail call <vscale x 16 x i1> @llvm.aarch64.sve.brkpa.z.nxv16i1(<vscale x 16 x i1> %pg, <vscale x 16 x i1> %a, <vscale x 16 x i1> %b)
77  %2 = tail call i1 @llvm.aarch64.sve.ptest.any.nxv16i1(<vscale x 16 x i1> %a, <vscale x 16 x i1> %1)
78  %conv = zext i1 %2 to i32
79  ret i32 %conv
80}
81
82define i32 @brkpb_neg(<vscale x 16 x i1> %pg, <vscale x 16 x i1> %a, <vscale x 16 x i1> %b) {
83; CHECK-LABEL: brkpb_neg:
84; CHECK:       // %bb.0:
85; CHECK-NEXT:    brkpb p0.b, p0/z, p1.b, p2.b
86; CHECK-NEXT:    ptest p1, p0.b
87; CHECK-NEXT:    cset w0, ne
88; CHECK-NEXT:    ret
89  %1 = tail call <vscale x 16 x i1> @llvm.aarch64.sve.brkpb.z.nxv16i1(<vscale x 16 x i1> %pg, <vscale x 16 x i1> %a, <vscale x 16 x i1> %b)
90  %2 = tail call i1 @llvm.aarch64.sve.ptest.any.nxv16i1(<vscale x 16 x i1> %a, <vscale x 16 x i1> %1)
91  %conv = zext i1 %2 to i32
92  ret i32 %conv
93}
94
95define i32 @brka_neg(<vscale x 16 x i1> %pg, <vscale x 16 x i1> %a) {
96; CHECK-LABEL: brka_neg:
97; CHECK:       // %bb.0:
98; CHECK-NEXT:    brka p0.b, p0/z, p1.b
99; CHECK-NEXT:    ptest p1, p0.b
100; CHECK-NEXT:    cset w0, ne
101; CHECK-NEXT:    ret
102  %1 = tail call <vscale x 16 x i1> @llvm.aarch64.sve.brka.z.nxv16i1(<vscale x 16 x i1> %pg, <vscale x 16 x i1> %a)
103  %2 = tail call i1 @llvm.aarch64.sve.ptest.any.nxv16i1(<vscale x 16 x i1> %a, <vscale x 16 x i1> %1)
104  %conv = zext i1 %2 to i32
105  ret i32 %conv
106}
107
108define i32 @brkb_neg(<vscale x 16 x i1> %pg, <vscale x 16 x i1> %a) {
109; CHECK-LABEL: brkb_neg:
110; CHECK:       // %bb.0:
111; CHECK-NEXT:    brkb p0.b, p0/z, p1.b
112; CHECK-NEXT:    ptest p1, p0.b
113; CHECK-NEXT:    cset w0, ne
114; CHECK-NEXT:    ret
115  %1 = tail call <vscale x 16 x i1> @llvm.aarch64.sve.brkb.z.nxv16i1(<vscale x 16 x i1> %pg, <vscale x 16 x i1> %a)
116  %2 = tail call i1 @llvm.aarch64.sve.ptest.any.nxv16i1(<vscale x 16 x i1> %a, <vscale x 16 x i1> %1)
117  %conv = zext i1 %2 to i32
118  ret i32 %conv
119}
120
121define i32 @brkn_neg(<vscale x 16 x i1> %pg, <vscale x 16 x i1> %a, <vscale x 16 x i1> %b) {
122; CHECK-LABEL: brkn_neg:
123; CHECK:       // %bb.0:
124; CHECK-NEXT:    brkn p2.b, p0/z, p1.b, p2.b
125; CHECK-NEXT:    ptest p1, p2.b
126; CHECK-NEXT:    cset w0, ne
127; CHECK-NEXT:    ret
128  %1 = tail call <vscale x 16 x i1> @llvm.aarch64.sve.brkn.z.nxv16i1(<vscale x 16 x i1> %pg, <vscale x 16 x i1> %a, <vscale x 16 x i1> %b)
129  %2 = tail call i1 @llvm.aarch64.sve.ptest.any.nxv16i1(<vscale x 16 x i1> %a, <vscale x 16 x i1> %1)
130  %conv = zext i1 %2 to i32
131  ret i32 %conv
132}
133
134define i32 @brkn_neg2(<vscale x 16 x i1> %pg, <vscale x 16 x i1> %a, <vscale x 16 x i1> %b) {
135; CHECK-LABEL: brkn_neg2:
136; CHECK:       // %bb.0:
137; CHECK-NEXT:    brkn p2.b, p0/z, p1.b, p2.b
138; CHECK-NEXT:    ptest p0, p2.b
139; CHECK-NEXT:    cset w0, ne
140; CHECK-NEXT:    ret
141  %1 = tail call <vscale x 16 x i1> @llvm.aarch64.sve.brkn.z.nxv16i1(<vscale x 16 x i1> %pg, <vscale x 16 x i1> %a, <vscale x 16 x i1> %b)
142  %2 = tail call i1 @llvm.aarch64.sve.ptest.any.nxv16i1(<vscale x 16 x i1> %pg, <vscale x 16 x i1> %1)
143  %conv = zext i1 %2 to i32
144  ret i32 %conv
145}
146
147declare <vscale x 16 x i1> @llvm.aarch64.sve.brkpa.z.nxv16i1(<vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>)
148declare <vscale x 16 x i1> @llvm.aarch64.sve.brkpb.z.nxv16i1(<vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>)
149declare <vscale x 16 x i1> @llvm.aarch64.sve.brka.z.nxv16i1(<vscale x 16 x i1>, <vscale x 16 x i1>)
150declare <vscale x 16 x i1> @llvm.aarch64.sve.brkb.z.nxv16i1(<vscale x 16 x i1>, <vscale x 16 x i1>)
151declare <vscale x 16 x i1> @llvm.aarch64.sve.brkn.z.nxv16i1(<vscale x 16 x i1>, <vscale x 16 x i1>, <vscale x 16 x i1>)
152declare i1 @llvm.aarch64.sve.ptest.any.nxv16i1(<vscale x 16 x i1>, <vscale x 16 x i1>)
153declare <vscale x 16 x i1> @llvm.aarch64.sve.ptrue.nxv16i1(i32)
154