xref: /llvm-project/llvm/test/CodeGen/AArch64/sve-pred-non-temporal-ldst-addressing-mode-reg-reg.ll (revision 5ddce70ef0e5a641d7fea95e31fc5e2439cb98cb) 
1; RUN: llc -mtriple=aarch64--linux-gnu -mattr=+sve --asm-verbose=false < %s | FileCheck %s
2
3; 2-lane non-temporal load/stores
4
5define void @test_masked_ldst_sv2i64(ptr %base, <vscale x 2 x i1> %mask, i64 %offset) nounwind {
6; CHECK-LABEL: test_masked_ldst_sv2i64:
7; CHECK-NEXT: ldnt1d { z[[DATA:[0-9]+]].d }, p0/z, [x0, x1, lsl #3]
8; CHECK-NEXT: stnt1d { z[[DATA]].d }, p0, [x0, x1, lsl #3]
9; CHECK-NEXT: ret
10  %gep = getelementptr i64, ptr %base, i64 %offset
11  %data = call <vscale x 2 x i64> @llvm.aarch64.sve.ldnt1.nxv2i64(<vscale x 2 x i1> %mask,
12                                                                  ptr %gep)
13  call void @llvm.aarch64.sve.stnt1.nxv2i64(<vscale x 2 x i64> %data,
14                                            <vscale x 2 x i1> %mask,
15                                            ptr %gep)
16  ret void
17}
18
19define void @test_masked_ldst_sv2f64(ptr %base, <vscale x 2 x i1> %mask, i64 %offset) nounwind {
20; CHECK-LABEL: test_masked_ldst_sv2f64:
21; CHECK-NEXT: ldnt1d { z[[DATA:[0-9]+]].d }, p0/z, [x0, x1, lsl #3]
22; CHECK-NEXT: stnt1d { z[[DATA]].d }, p0, [x0, x1, lsl #3]
23; CHECK-NEXT: ret
24  %gep = getelementptr double, ptr %base, i64 %offset
25  %data = call <vscale x 2 x double> @llvm.aarch64.sve.ldnt1.nxv2f64(<vscale x 2 x i1> %mask,
26                                                                    ptr %gep)
27  call void @llvm.aarch64.sve.stnt1.nxv2f64(<vscale x 2 x double> %data,
28                                            <vscale x 2 x i1> %mask,
29                                            ptr %gep)
30  ret void
31}
32
33; 4-lane non-temporal load/stores.
34
35define void @test_masked_ldst_sv4i32(ptr %base, <vscale x 4 x i1> %mask, i64 %offset) nounwind {
36; CHECK-LABEL: test_masked_ldst_sv4i32:
37; CHECK-NEXT: ldnt1w { z[[DATA:[0-9]+]].s }, p0/z, [x0, x1, lsl #2]
38; CHECK-NEXT: stnt1w { z[[DATA]].s }, p0, [x0, x1, lsl #2]
39; CHECK-NEXT: ret
40  %gep = getelementptr i32, ptr %base, i64 %offset
41  %data = call <vscale x 4 x i32> @llvm.aarch64.sve.ldnt1.nxv4i32(<vscale x 4 x i1> %mask,
42                                                                  ptr %gep)
43  call void @llvm.aarch64.sve.stnt1.nxv4i32(<vscale x 4 x i32> %data,
44                                            <vscale x 4 x i1> %mask,
45                                            ptr %gep)
46  ret void
47}
48
49define void @test_masked_ldst_sv4f32(ptr %base, <vscale x 4 x i1> %mask, i64 %offset) nounwind {
50; CHECK-LABEL: test_masked_ldst_sv4f32:
51; CHECK-NEXT: ldnt1w { z[[DATA:[0-9]+]].s }, p0/z, [x0, x1, lsl #2]
52; CHECK-NEXT: stnt1w { z[[DATA]].s }, p0, [x0, x1, lsl #2]
53; CHECK-NEXT: ret
54  %gep = getelementptr float, ptr %base, i64 %offset
55  %data = call <vscale x 4 x float> @llvm.aarch64.sve.ldnt1.nxv4f32(<vscale x 4 x i1> %mask,
56                                                                    ptr %gep)
57  call void @llvm.aarch64.sve.stnt1.nxv4f32(<vscale x 4 x float> %data,
58                                            <vscale x 4 x i1> %mask,
59                                            ptr %gep)
60  ret void
61}
62
63
64; 8-lane non-temporal load/stores.
65
66define void @test_masked_ldst_sv8i16(ptr %base, <vscale x 8 x i1> %mask, i64 %offset) nounwind {
67; CHECK-LABEL: test_masked_ldst_sv8i16:
68; CHECK-NEXT: ldnt1h { z[[DATA:[0-9]+]].h }, p0/z, [x0, x1, lsl #1]
69; CHECK-NEXT: stnt1h { z[[DATA]].h }, p0, [x0, x1, lsl #1]
70; CHECK-NEXT: ret
71  %gep = getelementptr i16, ptr %base, i64 %offset
72  %data = call <vscale x 8 x i16> @llvm.aarch64.sve.ldnt1.nxv8i16(<vscale x 8 x i1> %mask,
73                                                                  ptr %gep)
74  call void @llvm.aarch64.sve.stnt1.nxv8i16(<vscale x 8 x i16> %data,
75                                            <vscale x 8 x i1> %mask,
76                                            ptr %gep)
77  ret void
78}
79
80define void @test_masked_ldst_sv8f16(ptr %base, <vscale x 8 x i1> %mask, i64 %offset) nounwind {
81; CHECK-LABEL: test_masked_ldst_sv8f16:
82; CHECK-NEXT: ldnt1h { z[[DATA:[0-9]+]].h }, p0/z, [x0, x1, lsl #1]
83; CHECK-NEXT: stnt1h { z[[DATA]].h }, p0, [x0, x1, lsl #1]
84; CHECK-NEXT: ret
85  %gep = getelementptr half, ptr %base, i64 %offset
86  %data = call <vscale x 8 x half> @llvm.aarch64.sve.ldnt1.nxv8f16(<vscale x 8 x i1> %mask,
87                                                                   ptr %gep)
88  call void @llvm.aarch64.sve.stnt1.nxv8f16(<vscale x 8 x half> %data,
89                                            <vscale x 8 x i1> %mask,
90                                            ptr %gep)
91  ret void
92}
93
94define void @test_masked_ldst_sv8bf16(ptr %base, <vscale x 8 x i1> %mask, i64 %offset) nounwind #0 {
95; CHECK-LABEL: test_masked_ldst_sv8bf16:
96; CHECK-NEXT: ldnt1h { z[[DATA:[0-9]+]].h }, p0/z, [x0, x1, lsl #1]
97; CHECK-NEXT: stnt1h { z[[DATA]].h }, p0, [x0, x1, lsl #1]
98; CHECK-NEXT: ret
99  %gep = getelementptr bfloat, ptr %base, i64 %offset
100  %data = call <vscale x 8 x bfloat> @llvm.aarch64.sve.ldnt1.nxv8bf16(<vscale x 8 x i1> %mask,
101                                                                      ptr %gep)
102  call void @llvm.aarch64.sve.stnt1.nxv8bf16(<vscale x 8 x bfloat> %data,
103                                             <vscale x 8 x i1> %mask,
104                                             ptr %gep)
105  ret void
106}
107
108; 16-lane non-temporal load/stores.
109
110define void @test_masked_ldst_sv16i8(ptr %base, <vscale x 16 x i1> %mask, i64 %offset) nounwind {
111; CHECK-LABEL: test_masked_ldst_sv16i8:
112; CHECK-NEXT: ldnt1b { z[[DATA:[0-9]+]].b }, p0/z, [x0, x1]
113; CHECK-NEXT: stnt1b { z[[DATA]].b }, p0, [x0, x1]
114; CHECK-NEXT: ret
115  %gep = getelementptr i8, ptr %base, i64 %offset
116  %data = call <vscale x 16 x i8> @llvm.aarch64.sve.ldnt1.nxv16i8(<vscale x 16 x i1> %mask,
117                                                                  ptr %gep)
118  call void @llvm.aarch64.sve.stnt1.nxv16i8(<vscale x 16 x i8> %data,
119                                            <vscale x 16 x i1> %mask,
120                                            ptr %gep)
121  ret void
122}
123
124; 2-element non-temporal loads.
125declare <vscale x 2 x i64> @llvm.aarch64.sve.ldnt1.nxv2i64(<vscale x 2 x i1>, ptr)
126declare <vscale x 2 x double> @llvm.aarch64.sve.ldnt1.nxv2f64(<vscale x 2 x i1>, ptr)
127
128; 4-element non-temporal loads.
129declare <vscale x 4 x i32> @llvm.aarch64.sve.ldnt1.nxv4i32(<vscale x 4 x i1>, ptr)
130declare <vscale x 4 x float> @llvm.aarch64.sve.ldnt1.nxv4f32(<vscale x 4 x i1>, ptr)
131
132; 8-element non-temporal loads.
133declare <vscale x 8 x i16> @llvm.aarch64.sve.ldnt1.nxv8i16(<vscale x 8 x i1>, ptr)
134declare <vscale x 8 x half> @llvm.aarch64.sve.ldnt1.nxv8f16(<vscale x 8 x i1>, ptr)
135declare <vscale x 8 x bfloat> @llvm.aarch64.sve.ldnt1.nxv8bf16(<vscale x 8 x i1>, ptr)
136
137; 16-element non-temporal loads.
138declare <vscale x 16 x i8> @llvm.aarch64.sve.ldnt1.nxv16i8(<vscale x 16 x i1>, ptr)
139
140; 2-element non-temporal stores.
141declare void @llvm.aarch64.sve.stnt1.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i1>, ptr)
142declare void @llvm.aarch64.sve.stnt1.nxv2f64(<vscale x 2 x double>, <vscale x 2 x i1>, ptr)
143
144; 4-element non-temporal stores.
145declare void @llvm.aarch64.sve.stnt1.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i1>, ptr)
146declare void @llvm.aarch64.sve.stnt1.nxv4f32(<vscale x 4 x float>, <vscale x 4 x i1>, ptr)
147
148; 8-element non-temporal stores.
149declare void @llvm.aarch64.sve.stnt1.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i1>, ptr)
150declare void @llvm.aarch64.sve.stnt1.nxv8f16(<vscale x 8 x half>, <vscale x 8 x i1>, ptr)
151declare void @llvm.aarch64.sve.stnt1.nxv8bf16(<vscale x 8 x bfloat>, <vscale x 8 x i1>, ptr)
152
153; 16-element non-temporal stores.
154declare void @llvm.aarch64.sve.stnt1.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i1>, ptr)
155
156; +bf16 is required for the bfloat version.
157attributes #0 = { "target-features"="+sve,+bf16" }
158