xref: /llvm-project/llvm/test/CodeGen/AArch64/sve-masked-scatter.ll (revision cc82f1290a1e2157a6c0530d78d8cc84d2b8553d) 
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve < %s | FileCheck %s
3
4define void @masked_scatter_nxv2i8(<vscale x 2 x i8> %data, <vscale x 2 x ptr> %ptrs, <vscale x 2 x i1> %masks) nounwind {
5; CHECK-LABEL: masked_scatter_nxv2i8:
6; CHECK:       // %bb.0:
7; CHECK-NEXT:    st1b { z0.d }, p0, [z1.d]
8; CHECK-NEXT:    ret
9  call void @llvm.masked.scatter.nxv2i8(<vscale x 2 x i8> %data, <vscale x 2 x ptr> %ptrs, i32 0, <vscale x 2 x i1> %masks)
10  ret void
11}
12
13define void @masked_scatter_nxv2i16(<vscale x 2 x i16> %data, <vscale x 2 x ptr> %ptrs, <vscale x 2 x i1> %masks) nounwind {
14; CHECK-LABEL: masked_scatter_nxv2i16:
15; CHECK:       // %bb.0:
16; CHECK-NEXT:    st1h { z0.d }, p0, [z1.d]
17; CHECK-NEXT:    ret
18  call void @llvm.masked.scatter.nxv2i16(<vscale x 2 x i16> %data, <vscale x 2 x ptr> %ptrs, i32 0, <vscale x 2 x i1> %masks)
19  ret void
20}
21
22define void @masked_scatter_nxv2i32(<vscale x 2 x i32> %data, <vscale x 2 x ptr> %ptrs, <vscale x 2 x i1> %masks) nounwind {
23; CHECK-LABEL: masked_scatter_nxv2i32:
24; CHECK:       // %bb.0:
25; CHECK-NEXT:    st1w { z0.d }, p0, [z1.d]
26; CHECK-NEXT:    ret
27  call void @llvm.masked.scatter.nxv2i32(<vscale x 2 x i32> %data, <vscale x 2 x ptr> %ptrs, i32 0, <vscale x 2 x i1> %masks)
28  ret void
29}
30
31define void @masked_scatter_nxv2i64(<vscale x 2 x i64> %data, <vscale x 2 x ptr> %ptrs, <vscale x 2 x i1> %masks) nounwind {
32; CHECK-LABEL: masked_scatter_nxv2i64:
33; CHECK:       // %bb.0:
34; CHECK-NEXT:    st1d { z0.d }, p0, [z1.d]
35; CHECK-NEXT:    ret
36  call void @llvm.masked.scatter.nxv2i64(<vscale x 2 x i64> %data, <vscale x 2 x ptr> %ptrs, i32 0, <vscale x 2 x i1> %masks)
37  ret void
38}
39
40define void @masked_scatter_nxv2f16(<vscale x 2 x half> %data, <vscale x 2 x ptr> %ptrs, <vscale x 2 x i1> %masks) nounwind {
41; CHECK-LABEL: masked_scatter_nxv2f16:
42; CHECK:       // %bb.0:
43; CHECK-NEXT:    st1h { z0.d }, p0, [z1.d]
44; CHECK-NEXT:    ret
45  call void @llvm.masked.scatter.nxv2f16(<vscale x 2 x half> %data, <vscale x 2 x ptr> %ptrs, i32 0, <vscale x 2 x i1> %masks)
46  ret void
47}
48
49define void @masked_scatter_nxv2bf16(<vscale x 2 x bfloat> %data, <vscale x 2 x ptr> %ptrs, <vscale x 2 x i1> %masks) nounwind #0 {
50; CHECK-LABEL: masked_scatter_nxv2bf16:
51; CHECK:       // %bb.0:
52; CHECK-NEXT:    st1h { z0.d }, p0, [z1.d]
53; CHECK-NEXT:    ret
54  call void @llvm.masked.scatter.nxv2bf16(<vscale x 2 x bfloat> %data, <vscale x 2 x ptr> %ptrs, i32 0, <vscale x 2 x i1> %masks)
55  ret void
56}
57
58define void @masked_scatter_nxv2f32(<vscale x 2 x float> %data, <vscale x 2 x ptr> %ptrs, <vscale x 2 x i1> %masks) nounwind {
59; CHECK-LABEL: masked_scatter_nxv2f32:
60; CHECK:       // %bb.0:
61; CHECK-NEXT:    st1w { z0.d }, p0, [z1.d]
62; CHECK-NEXT:    ret
63  call void @llvm.masked.scatter.nxv2f32(<vscale x 2 x float> %data, <vscale x 2 x ptr> %ptrs, i32 0, <vscale x 2 x i1> %masks)
64  ret void
65}
66
67define void @masked_scatter_nxv2f64(<vscale x 2 x double> %data, <vscale x 2 x ptr> %ptrs, <vscale x 2 x i1> %masks) nounwind {
68; CHECK-LABEL: masked_scatter_nxv2f64:
69; CHECK:       // %bb.0:
70; CHECK-NEXT:    st1d { z0.d }, p0, [z1.d]
71; CHECK-NEXT:    ret
72  call void @llvm.masked.scatter.nxv2f64(<vscale x 2 x double> %data, <vscale x 2 x ptr> %ptrs, i32 0, <vscale x 2 x i1> %masks)
73  ret void
74}
75
76define void @masked_scatter_splat_constant_pointer (<vscale x 4 x i1> %pg) {
77; CHECK-LABEL: masked_scatter_splat_constant_pointer:
78; CHECK:       // %bb.0: // %vector.body
79; CHECK-NEXT:    mov z0.d, #0 // =0x0
80; CHECK-NEXT:    punpklo p1.h, p0.b
81; CHECK-NEXT:    punpkhi p0.h, p0.b
82; CHECK-NEXT:    st1w { z0.d }, p1, [z0.d]
83; CHECK-NEXT:    st1w { z0.d }, p0, [z0.d]
84; CHECK-NEXT:    ret
85vector.body:
86  call void @llvm.masked.scatter.nxv4i32.nxv4p0(<vscale x 4 x i32> undef,
87    <vscale x 4 x ptr> shufflevector (<vscale x 4 x ptr> insertelement (<vscale x 4 x ptr> poison, ptr null, i32 0), <vscale x 4 x ptr> poison, <vscale x 4 x i32> zeroinitializer),
88    i32 4,
89    <vscale x 4 x i1> %pg)
90  ret void
91}
92
93%i64_x3 = type { i64, i64, i64 }
94define void @masked_scatter_non_power_of_two_based_scaling(<vscale x 2 x double> %data, ptr %base, <vscale x 2 x i64> %offsets, <vscale x 2 x i1> %mask) {
95; CHECK-LABEL: masked_scatter_non_power_of_two_based_scaling:
96; CHECK:       // %bb.0:
97; CHECK-NEXT:    mul z1.d, z1.d, #24
98; CHECK-NEXT:    st1d { z0.d }, p0, [x0, z1.d]
99; CHECK-NEXT:    ret
100  %ptrs = getelementptr inbounds %i64_x3, ptr %base, <vscale x 2 x i64> %offsets
101  call void @llvm.masked.scatter.nxv2f64(<vscale x 2 x double> %data, <vscale x 2 x ptr> %ptrs, i32 8, <vscale x 2 x i1> %mask)
102  ret void
103}
104
105%i64_x4 = type { i64, i64, i64, i64}
106define void @masked_scatter_non_element_type_based_scaling(<vscale x 2 x double> %data, ptr %base, <vscale x 2 x i64> %offsets, <vscale x 2 x i1> %mask) {
107; CHECK-LABEL: masked_scatter_non_element_type_based_scaling:
108; CHECK:       // %bb.0:
109; CHECK-NEXT:    lsl z1.d, z1.d, #5
110; CHECK-NEXT:    st1d { z0.d }, p0, [x0, z1.d]
111; CHECK-NEXT:    ret
112  %ptrs = getelementptr inbounds %i64_x4, ptr %base, <vscale x 2 x i64> %offsets
113  call void @llvm.masked.scatter.nxv2f64(<vscale x 2 x double> %data, <vscale x 2 x ptr> %ptrs, i32 8, <vscale x 2 x i1> %mask)
114  ret void
115}
116
117declare void @llvm.masked.scatter.nxv2f16(<vscale x 2 x half>, <vscale x 2 x ptr>, i32, <vscale x 2 x i1>)
118declare void @llvm.masked.scatter.nxv2bf16(<vscale x 2 x bfloat>, <vscale x 2 x ptr>, i32, <vscale x 2 x i1>)
119declare void @llvm.masked.scatter.nxv2f32(<vscale x 2 x float>, <vscale x 2 x ptr>, i32, <vscale x 2 x i1>)
120declare void @llvm.masked.scatter.nxv2f64(<vscale x 2 x double>, <vscale x 2 x ptr>, i32, <vscale x 2 x i1>)
121declare void @llvm.masked.scatter.nxv2i16(<vscale x 2 x i16>, <vscale x 2 x ptr>, i32, <vscale x 2 x i1>)
122declare void @llvm.masked.scatter.nxv2i32(<vscale x 2 x i32>, <vscale x 2 x ptr>, i32, <vscale x 2 x i1>)
123declare void @llvm.masked.scatter.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x ptr>, i32, <vscale x 2 x i1>)
124declare void @llvm.masked.scatter.nxv2i8(<vscale x 2 x i8>, <vscale x 2 x ptr>, i32, <vscale x 2 x i1>)
125declare void @llvm.masked.scatter.nxv4i32.nxv4p0(<vscale x 4 x i32>, <vscale x 4 x ptr>, i32, <vscale x 4 x i1>)
126attributes #0 = { "target-features"="+sve,+bf16" }
127