xref: /llvm-project/llvm/test/CodeGen/AArch64/sve-masked-ldst-nonext.ll (revision 1ee315ae7964c8433b772e0b5d667834994ba753) 
1; RUN: llc -mtriple=aarch64--linux-gnu -mattr=+sve -asm-verbose=0 < %s | FileCheck %s
2
3;
4; Masked Loads
5;
6
7define <vscale x 2 x i64> @masked_load_nxv2i64(ptr %a, <vscale x 2 x i1> %mask) nounwind {
8; CHECK-LABEL: masked_load_nxv2i64:
9; CHECK-NEXT: ld1d { z0.d }, p0/z, [x0]
10; CHECK-NEXT: ret
11  %load = call <vscale x 2 x i64> @llvm.masked.load.nxv2i64(ptr %a, i32 8, <vscale x 2 x i1> %mask, <vscale x 2 x i64> undef)
12  ret <vscale x 2 x i64> %load
13}
14
15define <vscale x 4 x i32> @masked_load_nxv4i32(ptr %a, <vscale x 4 x i1> %mask) nounwind {
16; CHECK-LABEL: masked_load_nxv4i32:
17; CHECK-NEXT: ld1w { z0.s }, p0/z, [x0]
18; CHECK-NEXT: ret
19  %load = call <vscale x 4 x i32> @llvm.masked.load.nxv4i32(ptr %a, i32 4, <vscale x 4 x i1> %mask, <vscale x 4 x i32> undef)
20  ret <vscale x 4 x i32> %load
21}
22
23define <vscale x 8 x i16> @masked_load_nxv8i16(ptr %a, <vscale x 8 x i1> %mask) nounwind {
24; CHECK-LABEL: masked_load_nxv8i16:
25; CHECK-NEXT: ld1h { z0.h }, p0/z, [x0]
26; CHECK-NEXT: ret
27  %load = call <vscale x 8 x i16> @llvm.masked.load.nxv8i16(ptr %a, i32 2, <vscale x 8 x i1> %mask, <vscale x 8 x i16> undef)
28  ret <vscale x 8 x i16> %load
29}
30
31define <vscale x 16 x i8> @masked_load_nxv16i8(ptr %a, <vscale x 16 x i1> %mask) nounwind {
32; CHECK-LABEL: masked_load_nxv16i8:
33; CHECK-NEXT: ld1b { z0.b }, p0/z, [x0]
34; CHECK-NEXT: ret
35  %load = call <vscale x 16 x i8> @llvm.masked.load.nxv16i8(ptr %a, i32 1, <vscale x 16 x i1> %mask, <vscale x 16 x i8> undef)
36  ret <vscale x 16 x i8> %load
37}
38
39define <vscale x 2 x double> @masked_load_nxv2f64(ptr %a, <vscale x 2 x i1> %mask) nounwind {
40; CHECK-LABEL: masked_load_nxv2f64:
41; CHECK-NEXT: ld1d { z0.d }, p0/z, [x0]
42; CHECK-NEXT: ret
43  %load = call <vscale x 2 x double> @llvm.masked.load.nxv2f64(ptr %a, i32 8, <vscale x 2 x i1> %mask, <vscale x 2 x double> undef)
44  ret <vscale x 2 x double> %load
45}
46
47define <vscale x 2 x float> @masked_load_nxv2f32(ptr %a, <vscale x 2 x i1> %mask) nounwind {
48; CHECK-LABEL: masked_load_nxv2f32:
49; CHECK-NEXT: ld1w { z0.d }, p0/z, [x0]
50; CHECK-NEXT: ret
51  %load = call <vscale x 2 x float> @llvm.masked.load.nxv2f32(ptr %a, i32 4, <vscale x 2 x i1> %mask, <vscale x 2 x float> undef)
52  ret <vscale x 2 x float> %load
53}
54
55define <vscale x 2 x half> @masked_load_nxv2f16(ptr %a, <vscale x 2 x i1> %mask) nounwind {
56; CHECK-LABEL: masked_load_nxv2f16:
57; CHECK-NEXT: ld1h { z0.d }, p0/z, [x0]
58; CHECK-NEXT: ret
59  %load = call <vscale x 2 x half> @llvm.masked.load.nxv2f16(ptr %a, i32 2, <vscale x 2 x i1> %mask, <vscale x 2 x half> undef)
60  ret <vscale x 2 x half> %load
61}
62
63define <vscale x 2 x bfloat> @masked_load_nxv2bf16(ptr %a, <vscale x 2 x i1> %mask) nounwind #0 {
64; CHECK-LABEL: masked_load_nxv2bf16:
65; CHECK-NEXT: ld1h { z0.d }, p0/z, [x0]
66; CHECK-NEXT: ret
67  %load = call <vscale x 2 x bfloat> @llvm.masked.load.nxv2bf16(ptr %a, i32 2, <vscale x 2 x i1> %mask, <vscale x 2 x bfloat> undef)
68  ret <vscale x 2 x bfloat> %load
69}
70
71define <vscale x 4 x float> @masked_load_nxv4f32(ptr %a, <vscale x 4 x i1> %mask) nounwind {
72; CHECK-LABEL: masked_load_nxv4f32:
73; CHECK-NEXT: ld1w { z0.s }, p0/z, [x0]
74; CHECK-NEXT: ret
75  %load = call <vscale x 4 x float> @llvm.masked.load.nxv4f32(ptr %a, i32 4, <vscale x 4 x i1> %mask, <vscale x 4 x float> undef)
76  ret <vscale x 4 x float> %load
77}
78
79define <vscale x 4 x half> @masked_load_nxv4f16(ptr %a, <vscale x 4 x i1> %mask) nounwind {
80; CHECK-LABEL: masked_load_nxv4f16:
81; CHECK-NEXT: ld1h { z0.s }, p0/z, [x0]
82; CHECK-NEXT: ret
83  %load = call <vscale x 4 x half> @llvm.masked.load.nxv4f16(ptr %a, i32 2, <vscale x 4 x i1> %mask, <vscale x 4 x half> undef)
84  ret <vscale x 4 x half> %load
85}
86
87define <vscale x 4 x bfloat> @masked_load_nxv4bf16(ptr %a, <vscale x 4 x i1> %mask) nounwind #0 {
88; CHECK-LABEL: masked_load_nxv4bf16:
89; CHECK-NEXT: ld1h { z0.s }, p0/z, [x0]
90; CHECK-NEXT: ret
91  %load = call <vscale x 4 x bfloat> @llvm.masked.load.nxv4bf16(ptr %a, i32 2, <vscale x 4 x i1> %mask, <vscale x 4 x bfloat> undef)
92  ret <vscale x 4 x bfloat> %load
93}
94
95define <vscale x 8 x half> @masked_load_nxv8f16(ptr %a, <vscale x 8 x i1> %mask) nounwind {
96; CHECK-LABEL: masked_load_nxv8f16:
97; CHECK-NEXT: ld1h { z0.h }, p0/z, [x0]
98; CHECK-NEXT: ret
99  %load = call <vscale x 8 x half> @llvm.masked.load.nxv8f16(ptr %a, i32 2, <vscale x 8 x i1> %mask, <vscale x 8 x half> undef)
100  ret <vscale x 8 x half> %load
101}
102
103define <vscale x 8 x bfloat> @masked_load_nxv8bf16(ptr %a, <vscale x 8 x i1> %mask) nounwind #0 {
104; CHECK-LABEL: masked_load_nxv8bf16:
105; CHECK-NEXT: ld1h { z0.h }, p0/z, [x0]
106; CHECK-NEXT: ret
107  %load = call <vscale x 8 x bfloat> @llvm.masked.load.nxv8bf16(ptr %a, i32 2, <vscale x 8 x i1> %mask, <vscale x 8 x bfloat> undef)
108  ret <vscale x 8 x bfloat> %load
109}
110
111define <vscale x 4 x i32> @masked_load_passthru(ptr %a, <vscale x 4 x i1> %mask, <vscale x 4 x i32> %passthru) nounwind {
112; CHECK-LABEL: masked_load_passthru:
113; CHECK-NEXT: ld1w { z1.s }, p0/z, [x0]
114; CHECK-NEXT: mov z0.s, p0/m, z1.s
115; CHECK-NEXT: ret
116  %load = call <vscale x 4 x i32> @llvm.masked.load.nxv4i32(ptr %a, i32 4, <vscale x 4 x i1> %mask, <vscale x 4 x i32> %passthru)
117  ret <vscale x 4 x i32> %load
118}
119
120; Masked load requires promotion
121define <vscale x 2 x i16> @masked_load_nxv2i16(ptr noalias %in, <vscale x 2 x i1> %mask) {
122; CHECK-LABEL: masked_load_nxv2i16
123; CHECK:       ld1h { z0.d }, p0/z, [x0]
124; CHECK-NEXT:  ret
125  %wide.load = call <vscale x 2 x i16> @llvm.masked.load.nxv2i16(ptr %in, i32 2, <vscale x 2 x i1> %mask, <vscale x 2 x i16> undef)
126  ret <vscale x 2 x i16> %wide.load
127}
128
129;
130; Masked Stores
131;
132
133define void @masked_store_nxv2i64(ptr %a, <vscale x 2 x i64> %val, <vscale x 2 x i1> %mask) nounwind {
134; CHECK-LABEL: masked_store_nxv2i64:
135; CHECK-NEXT: st1d { z0.d }, p0, [x0]
136; CHECK-NEXT: ret
137  call void @llvm.masked.store.nxv2i64(<vscale x 2 x i64> %val, ptr %a, i32 8, <vscale x 2 x i1> %mask)
138  ret void
139}
140
141define void @masked_store_nxv4i32(ptr %a, <vscale x 4 x i32> %val, <vscale x 4 x i1> %mask) nounwind {
142; CHECK-LABEL: masked_store_nxv4i32:
143; CHECK-NEXT: st1w { z0.s }, p0, [x0]
144; CHECK-NEXT: ret
145  call void @llvm.masked.store.nxv4i32(<vscale x 4 x i32> %val, ptr %a, i32 4, <vscale x 4 x i1> %mask)
146  ret void
147}
148
149define void @masked_store_nxv8i16(ptr %a, <vscale x 8 x i16> %val, <vscale x 8 x i1> %mask) nounwind {
150; CHECK-LABEL: masked_store_nxv8i16:
151; CHECK-NEXT: st1h { z0.h }, p0, [x0]
152; CHECK-NEXT: ret
153  call void @llvm.masked.store.nxv8i16(<vscale x 8 x i16> %val, ptr %a, i32 2, <vscale x 8 x i1> %mask)
154  ret void
155}
156
157define void @masked_store_nxv16i8(ptr %a, <vscale x 16 x i8> %val, <vscale x 16 x i1> %mask) nounwind {
158; CHECK-LABEL: masked_store_nxv16i8:
159; CHECK-NEXT: st1b { z0.b }, p0, [x0]
160; CHECK-NEXT: ret
161  call void @llvm.masked.store.nxv16i8(<vscale x 16 x i8> %val, ptr %a, i32 1, <vscale x 16 x i1> %mask)
162  ret void
163}
164
165define void @masked_store_nxv2f64(ptr %a, <vscale x 2 x double> %val, <vscale x 2 x i1> %mask) nounwind {
166; CHECK-LABEL: masked_store_nxv2f64:
167; CHECK-NEXT: st1d { z0.d }, p0, [x0]
168; CHECK-NEXT: ret
169  call void @llvm.masked.store.nxv2f64(<vscale x 2 x double> %val, ptr %a, i32 8, <vscale x 2 x i1> %mask)
170  ret void
171}
172
173define void @masked_store_nxv2f32(ptr %a, <vscale x 2 x float> %val, <vscale x 2 x i1> %mask) nounwind {
174; CHECK-LABEL: masked_store_nxv2f32:
175; CHECK-NEXT: st1w { z0.d }, p0, [x0]
176; CHECK-NEXT: ret
177  call void @llvm.masked.store.nxv2f32(<vscale x 2 x float> %val, ptr %a, i32 4, <vscale x 2 x i1> %mask)
178  ret void
179}
180
181define void @masked_store_nxv2f16(ptr %a, <vscale x 2 x half> %val, <vscale x 2 x i1> %mask) nounwind {
182; CHECK-LABEL: masked_store_nxv2f16:
183; CHECK-NEXT: st1h { z0.d }, p0, [x0]
184; CHECK-NEXT: ret
185  call void @llvm.masked.store.nxv2f16(<vscale x 2 x half> %val, ptr %a, i32 4, <vscale x 2 x i1> %mask)
186  ret void
187}
188
189define void @masked_store_nxv4f32(ptr %a, <vscale x 4 x float> %val, <vscale x 4 x i1> %mask) nounwind {
190; CHECK-LABEL: masked_store_nxv4f32:
191; CHECK-NEXT: st1w { z0.s }, p0, [x0]
192; CHECK-NEXT: ret
193  call void @llvm.masked.store.nxv4f32(<vscale x 4 x float> %val, ptr %a, i32 4, <vscale x 4 x i1> %mask)
194  ret void
195}
196
197define void @masked_store_nxv4f16(ptr %a, <vscale x 4 x half> %val, <vscale x 4 x i1> %mask) nounwind {
198; CHECK-LABEL: masked_store_nxv4f16:
199; CHECK-NEXT: st1h { z0.s }, p0, [x0]
200; CHECK-NEXT: ret
201  call void @llvm.masked.store.nxv4f16(<vscale x 4 x half> %val, ptr %a, i32 2, <vscale x 4 x i1> %mask)
202  ret void
203}
204
205define void @masked_store_nxv8f16(ptr %a, <vscale x 8 x half> %val, <vscale x 8 x i1> %mask) nounwind {
206; CHECK-LABEL: masked_store_nxv8f16:
207; CHECK-NEXT: st1h { z0.h }, p0, [x0]
208; CHECK-NEXT: ret
209  call void @llvm.masked.store.nxv8f16(<vscale x 8 x half> %val, ptr %a, i32 2, <vscale x 8 x i1> %mask)
210  ret void
211}
212
213define void @masked_store_nxv2bf16(ptr %a, <vscale x 2 x bfloat> %val, <vscale x 2 x i1> %mask) nounwind #0 {
214; CHECK-LABEL: masked_store_nxv2bf16:
215; CHECK-NEXT: st1h { z0.d }, p0, [x0]
216; CHECK-NEXT: ret
217  call void @llvm.masked.store.nxv2bf16(<vscale x 2 x bfloat> %val, ptr %a, i32 2, <vscale x 2 x i1> %mask)
218  ret void
219}
220
221define void @masked_store_nxv4bf16(ptr %a, <vscale x 4 x bfloat> %val, <vscale x 4 x i1> %mask) nounwind #0 {
222; CHECK-LABEL: masked_store_nxv4bf16:
223; CHECK-NEXT: st1h { z0.s }, p0, [x0]
224; CHECK-NEXT: ret
225  call void @llvm.masked.store.nxv4bf16(<vscale x 4 x bfloat> %val, ptr %a, i32 2, <vscale x 4 x i1> %mask)
226  ret void
227}
228
229define void @masked_store_nxv8bf16(ptr %a, <vscale x 8 x bfloat> %val, <vscale x 8 x i1> %mask) nounwind #0 {
230; CHECK-LABEL: masked_store_nxv8bf16:
231; CHECK-NEXT: st1h { z0.h }, p0, [x0]
232; CHECK-NEXT: ret
233  call void @llvm.masked.store.nxv8bf16(<vscale x 8 x bfloat> %val, ptr %a, i32 2, <vscale x 8 x i1> %mask)
234  ret void
235}
236
237;
238; Masked load store of pointer data type
239;
240
241; Pointer of integer type
242
243define <vscale x 2 x ptr> @masked.load.nxv2p0i8(ptr %vector_ptr, <vscale x 2 x i1> %mask) nounwind {
244; CHECK-LABEL: masked.load.nxv2p0i8:
245; CHECK-NEXT:    ld1d { z0.d }, p0/z, [x0]
246; CHECK-NEXT:    ret
247  %v = call <vscale x 2 x ptr> @llvm.masked.load.nxv2p0.p0(ptr %vector_ptr, i32 8, <vscale x 2 x i1> %mask, <vscale x 2 x ptr> undef)
248  ret <vscale x 2 x ptr> %v
249}
250define <vscale x 2 x ptr> @masked.load.nxv2p0i16(ptr %vector_ptr, <vscale x 2 x i1> %mask) nounwind {
251; CHECK-LABEL: masked.load.nxv2p0i16:
252; CHECK-NEXT:    ld1d { z0.d }, p0/z, [x0]
253; CHECK-NEXT:    ret
254  %v = call <vscale x 2 x ptr> @llvm.masked.load.nxv2p0.p0(ptr %vector_ptr, i32 8, <vscale x 2 x i1> %mask, <vscale x 2 x ptr> undef)
255  ret <vscale x 2 x ptr> %v
256}
257define <vscale x 2 x ptr> @masked.load.nxv2p0i32(ptr %vector_ptr, <vscale x 2 x i1> %mask) nounwind {
258; CHECK-LABEL: masked.load.nxv2p0i32:
259; CHECK-NEXT:    ld1d { z0.d }, p0/z, [x0]
260; CHECK-NEXT:    ret
261  %v = call <vscale x 2 x ptr> @llvm.masked.load.nxv2p0.p0(ptr %vector_ptr, i32 8, <vscale x 2 x i1> %mask, <vscale x 2 x ptr> undef)
262  ret <vscale x 2 x ptr> %v
263}
264define <vscale x 2 x ptr> @masked.load.nxv2p0i64(ptr %vector_ptr, <vscale x 2 x i1> %mask) nounwind {
265; CHECK-LABEL: masked.load.nxv2p0i64:
266; CHECK-NEXT:    ld1d { z0.d }, p0/z, [x0]
267; CHECK-NEXT:    ret
268  %v = call <vscale x 2 x ptr> @llvm.masked.load.nxv2p0.p0(ptr %vector_ptr, i32 8, <vscale x 2 x i1> %mask, <vscale x 2 x ptr> undef)
269  ret <vscale x 2 x ptr> %v
270}
271
272; Pointer of floating-point type
273
274define <vscale x 2 x ptr> @masked.load.nxv2p0bf16(ptr %vector_ptr, <vscale x 2 x i1> %mask) nounwind #0 {
275; CHECK-LABEL: masked.load.nxv2p0bf16:
276; CHECK-NEXT:    ld1d { z0.d }, p0/z, [x0]
277; CHECK-NEXT:    ret
278  %v = call <vscale x 2 x ptr> @llvm.masked.load.nxv2p0.p0(ptr %vector_ptr, i32 8, <vscale x 2 x i1> %mask, <vscale x 2 x ptr> undef)
279  ret <vscale x 2 x ptr> %v
280}
281define <vscale x 2 x ptr> @masked.load.nxv2p0f16(ptr %vector_ptr, <vscale x 2 x i1> %mask) nounwind {
282; CHECK-LABEL: masked.load.nxv2p0f16:
283; CHECK-NEXT:    ld1d { z0.d }, p0/z, [x0]
284; CHECK-NEXT:    ret
285  %v = call <vscale x 2 x ptr> @llvm.masked.load.nxv2p0.p0(ptr %vector_ptr, i32 8, <vscale x 2 x i1> %mask, <vscale x 2 x ptr> undef)
286  ret <vscale x 2 x ptr> %v
287}
288define <vscale x 2 x ptr> @masked.load.nxv2p0f32(ptr %vector_ptr, <vscale x 2 x i1> %mask) nounwind {
289; CHECK-LABEL: masked.load.nxv2p0f32:
290; CHECK-NEXT:    ld1d { z0.d }, p0/z, [x0]
291; CHECK-NEXT:    ret
292  %v = call <vscale x 2 x ptr> @llvm.masked.load.nxv2p0.p0(ptr %vector_ptr, i32 8, <vscale x 2 x i1> %mask, <vscale x 2 x ptr> undef)
293  ret <vscale x 2 x ptr> %v
294}
295define <vscale x 2 x ptr> @masked.load.nxv2p0f64(ptr %vector_ptr, <vscale x 2 x i1> %mask) nounwind {
296; CHECK-LABEL: masked.load.nxv2p0f64:
297; CHECK-NEXT:    ld1d { z0.d }, p0/z, [x0]
298; CHECK-NEXT:    ret
299  %v = call <vscale x 2 x ptr> @llvm.masked.load.nxv2p0.p0(ptr %vector_ptr, i32 8, <vscale x 2 x i1> %mask, <vscale x 2 x ptr> undef)
300  ret <vscale x 2 x ptr> %v
301}
302
303; Pointer of array type
304
305define void @masked.store.nxv2p0a64i16(<vscale x 2 x ptr> %data, ptr %vector_ptr, <vscale x 2 x i1> %mask) nounwind {
306; CHECK-LABEL: masked.store.nxv2p0a64i16:
307; CHECK-NEXT:    st1d { z0.d }, p0, [x0]
308; CHECK-NEXT:    ret
309  call void @llvm.masked.store.nxv2p0.p0(<vscale x 2 x ptr> %data, ptr %vector_ptr, i32 8, <vscale x 2 x i1> %mask)
310  ret void
311}
312
313; Pointer of struct type
314
315%struct = type { ptr, i32 }
316define void @masked.store.nxv2p0s_struct(<vscale x 2 x ptr> %data, ptr %vector_ptr, <vscale x 2 x i1> %mask) nounwind {
317; CHECK-LABEL: masked.store.nxv2p0s_struct:
318; CHECK-NEXT:    st1d { z0.d }, p0, [x0]
319; CHECK-NEXT:    ret
320  call void @llvm.masked.store.nxv2p0.p0(<vscale x 2 x ptr> %data, ptr %vector_ptr, i32 8, <vscale x 2 x i1> %mask)
321  ret void
322}
323
324
325declare <vscale x 2 x i64> @llvm.masked.load.nxv2i64(ptr, i32, <vscale x 2 x i1>, <vscale x 2 x i64>)
326declare <vscale x 4 x i32> @llvm.masked.load.nxv4i32(ptr, i32, <vscale x 4 x i1>, <vscale x 4 x i32>)
327declare <vscale x 2 x i16> @llvm.masked.load.nxv2i16(ptr, i32, <vscale x 2 x i1>, <vscale x 2 x i16>)
328declare <vscale x 8 x i16> @llvm.masked.load.nxv8i16(ptr, i32, <vscale x 8 x i1>, <vscale x 8 x i16>)
329declare <vscale x 16 x i8> @llvm.masked.load.nxv16i8(ptr, i32, <vscale x 16 x i1>, <vscale x 16 x i8>)
330
331declare <vscale x 2 x double> @llvm.masked.load.nxv2f64(ptr, i32, <vscale x 2 x i1>, <vscale x 2 x double>)
332declare <vscale x 2 x float> @llvm.masked.load.nxv2f32(ptr, i32, <vscale x 2 x i1>, <vscale x 2 x float>)
333declare <vscale x 2 x half> @llvm.masked.load.nxv2f16(ptr, i32, <vscale x 2 x i1>, <vscale x 2 x half>)
334declare <vscale x 4 x float> @llvm.masked.load.nxv4f32(ptr, i32, <vscale x 4 x i1>, <vscale x 4 x float>)
335declare <vscale x 4 x half> @llvm.masked.load.nxv4f16(ptr, i32, <vscale x 4 x i1>, <vscale x 4 x half>)
336declare <vscale x 8 x half> @llvm.masked.load.nxv8f16(ptr, i32, <vscale x 8 x i1>, <vscale x 8 x half>)
337declare <vscale x 2 x bfloat> @llvm.masked.load.nxv2bf16(ptr, i32, <vscale x 2 x i1>, <vscale x 2 x bfloat>)
338declare <vscale x 4 x bfloat> @llvm.masked.load.nxv4bf16(ptr, i32, <vscale x 4 x i1>, <vscale x 4 x bfloat>)
339declare <vscale x 8 x bfloat> @llvm.masked.load.nxv8bf16(ptr, i32, <vscale x 8 x i1>, <vscale x 8 x bfloat>)
340
341declare void @llvm.masked.store.nxv2i64(<vscale x 2 x i64>, ptr, i32, <vscale x 2 x i1>)
342declare void @llvm.masked.store.nxv4i32(<vscale x 4 x i32>, ptr, i32, <vscale x 4 x i1>)
343declare void @llvm.masked.store.nxv8i16(<vscale x 8 x i16>, ptr, i32, <vscale x 8 x i1>)
344declare void @llvm.masked.store.nxv16i8(<vscale x 16 x i8>, ptr, i32, <vscale x 16 x i1>)
345
346declare void @llvm.masked.store.nxv2f64(<vscale x 2 x double>, ptr, i32, <vscale x 2 x i1>)
347declare void @llvm.masked.store.nxv2f32(<vscale x 2 x float>, ptr, i32, <vscale x 2 x i1>)
348declare void @llvm.masked.store.nxv2f16(<vscale x 2 x half>, ptr, i32, <vscale x 2 x i1>)
349declare void @llvm.masked.store.nxv4f32(<vscale x 4 x float>, ptr, i32, <vscale x 4 x i1>)
350declare void @llvm.masked.store.nxv4f16(<vscale x 4 x half>, ptr, i32, <vscale x 4 x i1>)
351declare void @llvm.masked.store.nxv8f16(<vscale x 8 x half>, ptr, i32, <vscale x 8 x i1>)
352declare void @llvm.masked.store.nxv2bf16(<vscale x 2 x bfloat>, ptr, i32, <vscale x 2 x i1>)
353declare void @llvm.masked.store.nxv4bf16(<vscale x 4 x bfloat>, ptr, i32, <vscale x 4 x i1>)
354declare void @llvm.masked.store.nxv8bf16(<vscale x 8 x bfloat>, ptr, i32, <vscale x 8 x i1>)
355
356declare <vscale x 2 x ptr> @llvm.masked.load.nxv2p0.p0(ptr, i32 immarg, <vscale x 2 x i1>, <vscale x 2 x ptr>)
357
358
359declare void @llvm.masked.store.nxv2p0.p0(<vscale x 2 x ptr>, ptr, i32 immarg, <vscale x 2 x i1>)
360
361
362; +bf16 is required for the bfloat version.
363attributes #0 = { "target-features"="+sve,+bf16" }
364