xref: /llvm-project/llvm/test/CodeGen/AArch64/sve-masked-int-arith.ll (revision 6082051da158699864fc873df494ad66e271ee22) 
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple=aarch64--linux-gnu -mattr=+sve < %s | FileCheck %s
3
4;
5; Masked Additions
6;
7
8define <vscale x 16 x i8> @masked_add_nxv16i8(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b, <vscale x 16 x i1> %mask) {
9; CHECK-LABEL: masked_add_nxv16i8:
10; CHECK:       // %bb.0:
11; CHECK-NEXT:    add z0.b, p0/m, z0.b, z1.b
12; CHECK-NEXT:    ret
13  %select = select <vscale x 16 x i1> %mask, <vscale x 16 x i8> %b, <vscale x 16 x i8> zeroinitializer
14  %ret = add <vscale x 16 x i8> %a, %select
15  ret <vscale x 16 x i8> %ret
16}
17
18define <vscale x 8 x i16> @masked_add_nxv8i16(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b, <vscale x 8 x i1> %mask) {
19; CHECK-LABEL: masked_add_nxv8i16:
20; CHECK:       // %bb.0:
21; CHECK-NEXT:    add z0.h, p0/m, z0.h, z1.h
22; CHECK-NEXT:    ret
23  %select = select <vscale x 8 x i1> %mask, <vscale x 8 x i16> %b, <vscale x 8 x i16> zeroinitializer
24  %ret = add <vscale x 8 x i16> %a, %select
25  ret <vscale x 8 x i16> %ret
26}
27
28define <vscale x 4 x i32> @masked_add_nxv4i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b, <vscale x 4 x i1> %mask) {
29; CHECK-LABEL: masked_add_nxv4i32:
30; CHECK:       // %bb.0:
31; CHECK-NEXT:    add z0.s, p0/m, z0.s, z1.s
32; CHECK-NEXT:    ret
33  %select = select <vscale x 4 x i1> %mask, <vscale x 4 x i32> %b, <vscale x 4 x i32> zeroinitializer
34  %ret = add <vscale x 4 x i32> %a, %select
35  ret <vscale x 4 x i32> %ret
36}
37
38define <vscale x 2 x i64> @masked_add_nxv2i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b, <vscale x 2 x i1> %mask) {
39; CHECK-LABEL: masked_add_nxv2i64:
40; CHECK:       // %bb.0:
41; CHECK-NEXT:    add z0.d, p0/m, z0.d, z1.d
42; CHECK-NEXT:    ret
43  %select = select <vscale x 2 x i1> %mask, <vscale x 2 x i64> %b, <vscale x 2 x i64> zeroinitializer
44  %ret = add <vscale x 2 x i64> %a, %select
45  ret <vscale x 2 x i64> %ret
46}
47
48;
49; Masked Subtractions
50;
51
52define <vscale x 16 x i8> @masked_sub_nxv16i8(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b, <vscale x 16 x i1> %mask) {
53; CHECK-LABEL: masked_sub_nxv16i8:
54; CHECK:       // %bb.0:
55; CHECK-NEXT:    sub z0.b, p0/m, z0.b, z1.b
56; CHECK-NEXT:    ret
57  %select = select <vscale x 16 x i1> %mask, <vscale x 16 x i8> %b, <vscale x 16 x i8> zeroinitializer
58  %ret = sub <vscale x 16 x i8> %a, %select
59  ret <vscale x 16 x i8> %ret
60}
61
62define <vscale x 8 x i16> @masked_sub_nxv8i16(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b, <vscale x 8 x i1> %mask) {
63; CHECK-LABEL: masked_sub_nxv8i16:
64; CHECK:       // %bb.0:
65; CHECK-NEXT:    sub z0.h, p0/m, z0.h, z1.h
66; CHECK-NEXT:    ret
67  %select = select <vscale x 8 x i1> %mask, <vscale x 8 x i16> %b, <vscale x 8 x i16> zeroinitializer
68  %ret = sub <vscale x 8 x i16> %a, %select
69  ret <vscale x 8 x i16> %ret
70}
71
72define <vscale x 4 x i32> @masked_sub_nxv4i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b, <vscale x 4 x i1> %mask) {
73; CHECK-LABEL: masked_sub_nxv4i32:
74; CHECK:       // %bb.0:
75; CHECK-NEXT:    sub z0.s, p0/m, z0.s, z1.s
76; CHECK-NEXT:    ret
77  %select = select <vscale x 4 x i1> %mask, <vscale x 4 x i32> %b, <vscale x 4 x i32> zeroinitializer
78  %ret = sub <vscale x 4 x i32> %a, %select
79  ret <vscale x 4 x i32> %ret
80}
81
82define <vscale x 2 x i64> @masked_sub_nxv2i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b, <vscale x 2 x i1> %mask) {
83; CHECK-LABEL: masked_sub_nxv2i64:
84; CHECK:       // %bb.0:
85; CHECK-NEXT:    sub z0.d, p0/m, z0.d, z1.d
86; CHECK-NEXT:    ret
87  %select = select <vscale x 2 x i1> %mask, <vscale x 2 x i64> %b, <vscale x 2 x i64> zeroinitializer
88  %ret = sub <vscale x 2 x i64> %a, %select
89  ret <vscale x 2 x i64> %ret
90}
91
92;
93; Masked multiply-add
94;
95
96define <vscale x 16 x i8> @masked_mla_nxv16i8(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b, <vscale x 16 x i8> %c, <vscale x 16 x i1> %mask) {
97; CHECK-LABEL: masked_mla_nxv16i8:
98; CHECK:       // %bb.0:
99; CHECK-NEXT:    mla z0.b, p0/m, z1.b, z2.b
100; CHECK-NEXT:    ret
101  %mul = mul nsw <vscale x 16 x i8> %b, %c
102  %sel = select <vscale x 16 x i1> %mask, <vscale x 16 x i8> %mul, <vscale x 16 x i8> zeroinitializer
103  %add = add <vscale x 16 x i8> %a, %sel
104  ret <vscale x 16 x i8> %add
105}
106
107define <vscale x 8 x i16> @masked_mla_nxv8i16(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b, <vscale x 8 x i16> %c, <vscale x 8 x i1> %mask) {
108; CHECK-LABEL: masked_mla_nxv8i16:
109; CHECK:       // %bb.0:
110; CHECK-NEXT:    mla z0.h, p0/m, z1.h, z2.h
111; CHECK-NEXT:    ret
112  %mul = mul nsw <vscale x 8 x i16> %b, %c
113  %sel = select <vscale x 8 x i1> %mask, <vscale x 8 x i16> %mul, <vscale x 8 x i16> zeroinitializer
114  %add = add <vscale x 8 x i16> %a, %sel
115  ret <vscale x 8 x i16> %add
116}
117
118define <vscale x 4 x i32> @masked_mla_nxv4i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b, <vscale x 4 x i32> %c, <vscale x 4 x i1> %mask) {
119; CHECK-LABEL: masked_mla_nxv4i32:
120; CHECK:       // %bb.0:
121; CHECK-NEXT:    mla z0.s, p0/m, z1.s, z2.s
122; CHECK-NEXT:    ret
123  %mul = mul nsw <vscale x 4 x i32> %b, %c
124  %sel = select <vscale x 4 x i1> %mask, <vscale x 4 x i32> %mul, <vscale x 4 x i32> zeroinitializer
125  %add = add <vscale x 4 x i32> %a, %sel
126  ret <vscale x 4 x i32> %add
127}
128
129define <vscale x 2 x i64> @masked_mla_nxv2i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b, <vscale x 2 x i64> %c, <vscale x 2 x i1> %mask) {
130; CHECK-LABEL: masked_mla_nxv2i64:
131; CHECK:       // %bb.0:
132; CHECK-NEXT:    mla z0.d, p0/m, z1.d, z2.d
133; CHECK-NEXT:    ret
134  %mul = mul nsw <vscale x 2 x i64> %b, %c
135  %sel = select <vscale x 2 x i1> %mask, <vscale x 2 x i64> %mul, <vscale x 2 x i64> zeroinitializer
136  %add = add <vscale x 2 x i64> %a, %sel
137  ret <vscale x 2 x i64> %add
138}
139
140;
141; Masked multiply-subtract
142;
143
144define <vscale x 16 x i8> @masked_mls_nxv16i8(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b, <vscale x 16 x i8> %c, <vscale x 16 x i1> %mask) {
145; CHECK-LABEL: masked_mls_nxv16i8:
146; CHECK:       // %bb.0:
147; CHECK-NEXT:    mls z0.b, p0/m, z1.b, z2.b
148; CHECK-NEXT:    ret
149  %mul = mul nsw <vscale x 16 x i8> %b, %c
150  %sel = select <vscale x 16 x i1> %mask, <vscale x 16 x i8> %mul, <vscale x 16 x i8> zeroinitializer
151  %sub = sub <vscale x 16 x i8> %a, %sel
152  ret <vscale x 16 x i8> %sub
153}
154
155define <vscale x 8 x i16> @masked_mls_nxv8i16(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b, <vscale x 8 x i16> %c, <vscale x 8 x i1> %mask) {
156; CHECK-LABEL: masked_mls_nxv8i16:
157; CHECK:       // %bb.0:
158; CHECK-NEXT:    mls z0.h, p0/m, z1.h, z2.h
159; CHECK-NEXT:    ret
160  %mul = mul nsw <vscale x 8 x i16> %b, %c
161  %sel = select <vscale x 8 x i1> %mask, <vscale x 8 x i16> %mul, <vscale x 8 x i16> zeroinitializer
162  %sub = sub <vscale x 8 x i16> %a, %sel
163  ret <vscale x 8 x i16> %sub
164}
165
166define <vscale x 4 x i32> @masked_mls_nxv4i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b, <vscale x 4 x i32> %c, <vscale x 4 x i1> %mask) {
167; CHECK-LABEL: masked_mls_nxv4i32:
168; CHECK:       // %bb.0:
169; CHECK-NEXT:    mls z0.s, p0/m, z1.s, z2.s
170; CHECK-NEXT:    ret
171  %mul = mul nsw <vscale x 4 x i32> %b, %c
172  %sel = select <vscale x 4 x i1> %mask, <vscale x 4 x i32> %mul, <vscale x 4 x i32> zeroinitializer
173  %sub = sub <vscale x 4 x i32> %a, %sel
174  ret <vscale x 4 x i32> %sub
175}
176
177define <vscale x 2 x i64> @masked_mls_nxv2i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b, <vscale x 2 x i64> %c, <vscale x 2 x i1> %mask) {
178; CHECK-LABEL: masked_mls_nxv2i64:
179; CHECK:       // %bb.0:
180; CHECK-NEXT:    mls z0.d, p0/m, z1.d, z2.d
181; CHECK-NEXT:    ret
182  %mul = mul nsw <vscale x 2 x i64> %b, %c
183  %sel = select <vscale x 2 x i1> %mask, <vscale x 2 x i64> %mul, <vscale x 2 x i64> zeroinitializer
184  %sub = sub <vscale x 2 x i64> %a, %sel
185  ret <vscale x 2 x i64> %sub
186}
187