xref: /llvm-project/llvm/test/CodeGen/AArch64/sve-localstackalloc.mir (revision d4d3239d982e15e039d3958b4202b13203df26bd) 
1# RUN: llc -mtriple=aarch64--linux-gnu -mattr=+sve -run-pass=localstackalloc -o - %s | FileCheck %s
2# RUN: llc -mtriple=aarch64--linux-gnu -mattr=+sve -passes=localstackalloc -o - %s | FileCheck %s
3
4--- |
5  ; ModuleID = '<stdin>'
6  source_filename = "<stdin>"
7  target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"
8  target triple = "aarch64-unknown-linux-gnu"
9
10  define <vscale x 32 x i8> @insert_32i8_idx(<vscale x 32 x i8> %a, i8 %elt, i64 %idx) #0 {
11    %ins = insertelement <vscale x 32 x i8> %a, i8 %elt, i64 %idx
12    ret <vscale x 32 x i8> %ins
13  }
14
15  attributes #0 = { "target-features"="+sve" }
16
17...
18---
19name:            insert_32i8_idx
20alignment:       4
21tracksRegLiveness: true
22registers:
23  - { id: 0, class: zpr, preferred-register: '' }
24  - { id: 1, class: zpr, preferred-register: '' }
25  - { id: 2, class: gpr32, preferred-register: '' }
26  - { id: 3, class: gpr64, preferred-register: '' }
27  - { id: 5, class: ppr_3b, preferred-register: '' }
28  - { id: 6, class: gpr64sp, preferred-register: '' }
29  - { id: 7, class: zpr, preferred-register: '' }
30  - { id: 8, class: zpr, preferred-register: '' }
31liveins:
32  - { reg: '$z0', virtual-reg: '%0' }
33  - { reg: '$z1', virtual-reg: '%1' }
34  - { reg: '$w0', virtual-reg: '%2' }
35frameInfo:
36  maxAlignment:    1
37  maxCallFrameSize: 0
38# CHECK-LABEL: name: insert_32i8_idx
39# CHECK: localFrameSize:  0
40stack:
41  - { id: 0, name: '', type: default, offset: 0, size: 32, alignment: 16,
42      stack-id: scalable-vector, callee-saved-register: '', callee-saved-restored: true,
43      debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
44machineFunctionInfo: {}
45body:             |
46  bb.0 (%ir-block.0):
47    liveins: $z0, $z1, $w0
48
49    %2:gpr32 = COPY $w0
50    %1:zpr = COPY $z1
51    %0:zpr = COPY $z0
52    %5:ppr_3b = PTRUE_B 31, implicit $vg
53    %6:gpr64sp = ADDXri %stack.0, 0, 0
54    ST1B_IMM %1, %5, %6, 1 :: (store unknown-size, align 16)
55    ST1B_IMM %0, %5, %stack.0, 0 :: (store unknown-size into %stack.0, align 16)
56    %7:zpr = LD1B_IMM %5, %6, 1 :: (load unknown-size from %stack.0 + 16, align 16)
57    %8:zpr = LD1B_IMM %5, %stack.0, 0 :: (load unknown-size from %stack.0, align 16)
58    $z0 = COPY %8
59    $z1 = COPY %7
60    RET_ReallyLR implicit $z0, implicit $z1
61
62...
63